Difference between revisions of "GPU Classes"

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Line 80: Line 80:
 
| 0x3F2 || SampleMask2 || 1 || ||
 
| 0x3F2 || SampleMask2 || 1 || ||
 
|-
 
|-
−
| 0x3F5 || Multisample_Related2 || 1 || ||
+
| 0x3F5 || Multisample_Related2 || 1 || || TODO
 
|-
 
|-
 
| 0x3F6 || CoverageModulationEnable || 1 || bool ||
 
| 0x3F6 || CoverageModulationEnable || 1 || bool ||
Line 94: Line 94:
 
| 0x4B3 || DepthTestEnable || 1 || bool || Enables DepthWriteEnable and DepthFunc.
 
| 0x4B3 || DepthTestEnable || 1 || bool || Enables DepthWriteEnable and DepthFunc.
 
|-
 
|-
−
| 0x4B8 || Multisample_Config2 || 1 || bool ||
+
| 0x4B8 || Multisample_Config2 || 1 || bool || TODO
 
|-
 
|-
 
| 0x4BA || DepthWriteEnable || 1 || bool ||
 
| 0x4BA || DepthWriteEnable || 1 || bool ||
Line 124: Line 124:
 
| 0x4C7 || BlendColor || 4 || float[4] ||
 
| 0x4C7 || BlendColor || 4 || float[4] ||
 
|-
 
|-
−
| 0x47C || || 1 || || BindProgram writes 0 here sometimes.
+
| 0x47C || || 1 || trigger || BindProgram writes 0 here sometimes.
 
|-
 
|-
−
| 0x47F || DepthBuffer_Resolve || 1 || || 1 is written here to trigger.
+
| 0x47F || DepthBufferResolve || 1 || trigger || 1 is written here to trigger.
 
|-
 
|-
−
| 0x519 || ZCullCtx_Save || 1 || || 0 is written here to trigger ctx-save, uses both ZCullCtx_Addr0/1.
+
| 0x519 || ZCullContextSave || 1 || trigger || 0 is written here to trigger ctx-save, uses ZCullContextStartAddr.
 
|-
 
|-
 
| 0x51F || PolygonOffsetClamp0 || 1 || float ||
 
| 0x51F || PolygonOffsetClamp0 || 1 || float ||
 
|-
 
|-
−
| 0x540 || ZCullCtx_Restore || 1 || || 0 is written here to trigger ctx-restore, uses both ZCullCtx_Addr0/1.
+
| 0x540 || ZCullContextRestore || 1 || trigger || 0 is written here to trigger ctx-restore, uses ZCullContextStartAddr.
 
|-
 
|-
 
| 0x546 || PointSize || 1 || float ||
 
| 0x546 || PointSize || 1 || float ||
 
|-
 
|-
−
| 0x554 || RendererEnableConditionAddr || 2 || gpuva ||
+
| 0x554 || RendererConditionAddr || 2 || gpuva ||
 
|-
 
|-
−
| 0x556 || RendererEnable || 1 || || 0=disabled unconditional, 1=enabled unconditional, 3=unknown conditional, 4=unknown conditional,  
+
| 0x556 || RendererConditionMode || 1 || || 0=disabled unconditional, 1=enabled unconditional, 3=unknown conditional, 4=unknown conditional,  
 
|-
 
|-
−
| 0x54C || Counter_Reset || 1 || || Value written decides which counter to reset.
+
| 0x54C || CounterReset || 1 || || Value written decides which counter to reset.
 
|-
 
|-
 
| 0x54D || MultisampleEnable || 1 || ||
 
| 0x54D || MultisampleEnable || 1 || ||
 
|-
 
|-
−
| 0x54F || MultisampleAlphaToCoverageEnable || 1 || bool ||
+
| 0x54F || MultisampleAlphaToCoverageEnable || 1 || bool || TODO: Has more fields?
 
|-
 
|-
−
| 0x55B || PolygonOffsetClamp1 || 1 || float ||
+
| 0x55B || PolygonOffsetFactor || 1 || float ||
 
|-
 
|-
−
| 0x56F || PolygonOffsetClamp2 || 1 || float || Float multiplied by 2 is written here.
+
| 0x56F || PolygonOffsetOffset || 1 || float || Float multiplied by 2 is written here.
 
|-
 
|-
−
| 0x591 || PrimitiveRestart_Enable || 1 || bool ||
+
| 0x591 || PrimitiveRestartEnable || 1 || bool ||
 
|-
 
|-
−
| 0x592 || PrimitiveRestart_Value || 1 || ||
+
| 0x592 || PrimitiveRestartIndex || 1 || uint ||
 
|-
 
|-
 
| 0x646 || PolygonCullFaceEnable || 1 || bool ||
 
| 0x646 || PolygonCullFaceEnable || 1 || bool ||
Line 158: Line 158:
 
| 0x647 || PolygonFrontFace || 1 || bitfield || Bit0: Enable. Always ORR'd with 0x9000.
 
| 0x647 || PolygonFrontFace || 1 || bitfield || Bit0: Enable. Always ORR'd with 0x9000.
 
|-
 
|-
−
| 0x648 || PolygonCullFaceConfig || 1 || bitfield || 0x404/0x405/0x408
+
| 0x648 || PolygonCullFaceConfig || 1 || bitfield || TODO: 0x404/0x405/0x408
 
|-
 
|-
−
| 0x64F || DepthClamp || 1 || || 0x101A is written when enabled, 0x181D when disabled.
+
| 0x64F || DepthClamp || 1 || || TODO: 0x101A is written when enabled, 0x181D when disabled.
 
|-
 
|-
−
| 0x66F || DepthBounds_Enable || 1 || bool ||
+
| 0x66F || DepthBoundsEnable || 1 || bool ||
 
|-
 
|-
−
| 0x671 || ColorStateLogicOpEnable || 1 || bool || Used for all LogicOps except 3.
+
| 0x671 || ColorLogicOpEnable || 1 || bool || Used for all LogicOps except 3.
 
|-
 
|-
−
| 0x672 || ColorStateLogicOpType || 1 || || Bit0-7: LogicOp, bit8-15: unknown, always 0x15.
+
| 0x672 || ColorLogicOpType || 1 || bitfield || Bit0-7: LogicOp, bit8-15: unknown, always 0x15.
 
|-
 
|-
 
| 0x68B || Barrier? || 1 || trigger || Always 0 is written here. During zcull ctx-save, spammed when enabling raster, ...
 
| 0x68B || Barrier? || 1 || trigger || Always 0 is written here. During zcull ctx-save, spammed when enabling raster, ...
 
|-
 
|-
−
| 0x6C0 || Poke_Addr || 2 || gpuva ||
+
| 0x6C0 || QueryAddr || 2 || gpuva ||
 
|-
 
|-
−
| 0x6C2 || Poke_WriteVal || 1 || || 0 is written here during most queries.
+
| 0x6C2 || QuerySequence || 1 || || 0 is written here during most queries.
 
|-
 
|-
−
| 0x6C3 || Poke_Control || 1 || || Big bitfield. After write, the result of query is written to 4 bytes at Poke_Addr.
+
| 0x6C3 || QueryControl || 1 || bitfield || After write, the result of query is written to 4 bytes at QueryAddr.
 
|-
 
|-
−
| 0x701+2*N || VertexBufferStartAddr || 2 || gpuva ||
+
| 0x701+2*N || VertexBufferStartAddr || 2 || gpuva || TODO: Doesn't match nouveau
 
|-
 
|-
 
| 0x7C0+2*N || VertexBufferEndAddr || 2 || gpuva ||
 
| 0x7C0+2*N || VertexBufferEndAddr || 2 || gpuva ||

Revision as of 20:59, 18 March 2018

Subchannels:

Id Subchannel (nvn) Name
0xB197 0 3D
0xB1C0 1 Compute
0xA140 2 Inline-to-Memory
0x902D 3 2D
0xB0B5 4 DMA

3D

Register Name Size Type Notes
0xC9 TesselationOuterLevels 4 float[4]
0xCD TesselationInnerLevels 2 float[2]
0xDF RasterizerEnable 1 bool
0xE0+8*N TransformFeedbackBufferEnable 1 bool
0xE1+8*N TransformFeedbackBufferAddr 2 gpuva
0xE3+8*N TransformFeedbackBufferFlags 1
0x1D1 TransformFeedbackEnable 1 bool
0x1FA ZCullContextStartAddr 2 gpuva
0x1FC ZCullContextEndAddr 2 gpuva
0x285+8*N DepthRange_Unk0_N 1 ?
0x302+4*N DepthRangeNear 1 float
0x303+4*N DepthRangeFar 1 float
0x36B PolygonModeFront 1 bitfield 0x1B00/0x1B01/0x1B02
0x36C PolygonModeBack 1 bitfield 0x1B00/0x1B01/0x1B02
0x370 PolygonOffsetPointEnable 1 bool
0x371 PolygonOffsetLineEnable 1 bool
0x372 PolygonOffsetFillEnable 1 bool
0x373 PatchSize 1 Small value, always fits in 12 bits. In number of vertices.
0x374 1 0 written here for "simple" BlendState.
0x381+4*N ScissorNHorizontal 1 bitfield Bit0-15: min, bit16-31: max
0x382+4*N ScissorNVertical 1 bitfield Bit0-15: min, bit16-31: max
0x3D5 StencilMask1RefValue 1
0x3D6 StencilMask1Enable 1 bool
0x3D7 StencilMask1ValueMask 1
0x3E7 DepthBounds 2 float[2]
0x3ED MultisampleRasterEnable 1 bool
0x3EE MultisampleRasterSamples 1 bitfield 2=Four, 4=Eight, 5=?, 6=Sixteen
0x3EF MultisampleCoverageModulationMode 1
0x3F0 SampleMask0 1
0x3F1 SampleMask1 1
0x3F2 SampleMask2 1
0x3F5 Multisample_Related2 1 TODO
0x3F6 CoverageModulationEnable 1 bool
0x40C CoverageModulationTable 1 float[4]
0x452 RasterEnable 1 bool
0x478 MultisampleGrid 3 bitfield[3] Bit0-3: x0, bit4-7: y0, bit8-11: x1, etc..
0x47E MultisampleCoverageToColor 1 bitfield Bit0: Enable, bit4-6: ?
0x4B3 DepthTestEnable 1 bool Enables DepthWriteEnable and DepthFunc.
0x4B8 Multisample_Config2 1 bool TODO
0x4BA DepthWriteEnable 1 bool
0x4C3 DepthFunc 1 bitfield Bit0-3: DepthFunc
0x4B8 MultisampleAlphaToCoverageDither 1 bool
0x4B9 BlendIndependent 1 bool 1 written here for "simple" BlendState.
0x4BB AlphaTestEnable 1 bool
0x4C5 AlphaTestFunc 1 bitfield Bit0-3: AlphaTestFunc
0x4E0 StencilEnable 1 bool
0x4E5 StencilFrontRefValue 1
0x4E6 StencilFrontMaskValue 1
0x4E7 StencilFrontEnable 1 bool
0x4EC LineWidthSmooth 1 float
0x4ED LineWidthAliased 1 float
0x4C4 AlphaTestRefValue 1 float
0x4C7 BlendColor 4 float[4]
0x47C 1 trigger BindProgram writes 0 here sometimes.
0x47F DepthBufferResolve 1 trigger 1 is written here to trigger.
0x519 ZCullContextSave 1 trigger 0 is written here to trigger ctx-save, uses ZCullContextStartAddr.
0x51F PolygonOffsetClamp0 1 float
0x540 ZCullContextRestore 1 trigger 0 is written here to trigger ctx-restore, uses ZCullContextStartAddr.
0x546 PointSize 1 float
0x554 RendererConditionAddr 2 gpuva
0x556 RendererConditionMode 1 0=disabled unconditional, 1=enabled unconditional, 3=unknown conditional, 4=unknown conditional,
0x54C CounterReset 1 Value written decides which counter to reset.
0x54D MultisampleEnable 1
0x54F MultisampleAlphaToCoverageEnable 1 bool TODO: Has more fields?
0x55B PolygonOffsetFactor 1 float
0x56F PolygonOffsetOffset 1 float Float multiplied by 2 is written here.
0x591 PrimitiveRestartEnable 1 bool
0x592 PrimitiveRestartIndex 1 uint
0x646 PolygonCullFaceEnable 1 bool
0x647 PolygonFrontFace 1 bitfield Bit0: Enable. Always ORR'd with 0x9000.
0x648 PolygonCullFaceConfig 1 bitfield TODO: 0x404/0x405/0x408
0x64F DepthClamp 1 TODO: 0x101A is written when enabled, 0x181D when disabled.
0x66F DepthBoundsEnable 1 bool
0x671 ColorLogicOpEnable 1 bool Used for all LogicOps except 3.
0x672 ColorLogicOpType 1 bitfield Bit0-7: LogicOp, bit8-15: unknown, always 0x15.
0x68B Barrier? 1 trigger Always 0 is written here. During zcull ctx-save, spammed when enabling raster, ...
0x6C0 QueryAddr 2 gpuva
0x6C2 QuerySequence 1 0 is written here during most queries.
0x6C3 QueryControl 1 bitfield After write, the result of query is written to 4 bytes at QueryAddr.
0x701+2*N VertexBufferStartAddr 2 gpuva TODO: Doesn't match nouveau
0x7C0+2*N VertexBufferEndAddr 2 gpuva
0x781+8*N SimpleBlend0_BlendEquation0 1 bitfield Bit0-2: BlendEquation0
0x782+8*N SimpleBlend0_BlendFunctionA 1 bitfield Bit0-4: ?, bit14-15: ?
0x783+8*N SimpleBlend0_BlendFunctionB 1 bitfield Bit0-4: ?, bit14-15: ?
0x784+8*N SimpleBlend0_BlendEquation1 1 bitfield Bit0-2: BlendEquation1
0x785+8*N SimpleBlend0_BlendFunctionC 1 bitfield Bit0-4: ?, bit14-15: ?
0x786+8*N SimpleBlend0_BlendFunctionD 1 bitfield Bit0-4: ?, bit14-15: ?
0x820 1 BindProgram writes here.
0x821 1 BindProgram writes here.
0x830 1 BindProgram writes here.
0x840 1 BindProgram writes here.
0x850 1 BindProgram writes here.
0x8E0 BindUniformBuffer_Size? 1 BindUniformBuffer writes here.
0x8E1 BindUniformBuffer_Addr 2 gpuva
0x8E3 BindImage_Config 1 BindImage writes "8*i + 0x120" here. BindSeparateSampler writes "8*i + 0x568" here. BindSeparateTexture uses "8*i + 0x168". BindTexture uses 8*i + 32.
0x8E4 BindImage_ValueLo 1 This might be an addr but it's swapped opposite to other addrs. BindSeparateSampler/BindSeparateTexture writes something here. BindStorageBuffer writes something here.
0x8E5 BindImage_ValueHi 1 BindStorageBuffer writes something here.
0x8E6 1 BindStorageBuffer writes something here.
0x8E4,0x8EB Multisample_ConfigX 1 What? Overlap.
0x904 UniformBuffer0_Control 1
0x90C UniformBuffer3_Control 1
0x914 UniformBuffer4_Control 1
0x91C UniformBuffer2_Control 1
0x924 UniformBuffer1_Control 1
0xD1E 1 BindProgram writes 0 here, trigger?
0xD34 1 Used by SetConservativeRasterDilate.
0xD35 BlendStateAdvanced 1 bitfield Bit0: NormalizedDst, bit1: PremultipliedSrc, bit2-3: BlendTarget, Bit4-9: Mode
0xE00 TransformFeedback_Addr 2 gpuaddr
0xE0A 1 Used by SetConservativeRasterDilate.
0xE0B 1 Used by SetConservativeRasterDilate.
0xE0E 1 BindImage/BindSeparateSampler/BindSeparateTexture writes 0-4 here.
0xE10 ColorStateLogicOp3 1 bitfield Bit8: BlendEnable, bit16-23: LogicOp, bit28-31: AlphaTest. BindColorState this when LogicOp == 3.
0xE12 BindChannelMaskState_Unk0 1
0xE13 BindChannelMaskState_Unk1 1
0xE1A StencilConfig 1 bitfield Bit0-3: StencilFunc0, bit4-7: StencilOp0_A, bit8-11: StencilOp0_B, bit12-15: StencilFunc1, bit16-19: StencilOp1_A, bit20-23: StencilOp1_B
0xE1E Multisample_Config7 1 Also written to by BindStorageBuffer
0xE20 1 Another barrier? Used by SetConservativeRasterDilate.
0xE2A DebugGroupPush_DynamicControl 1
0xE2B DebugGroupPush_DynamicValue 1 This one can be written a variable number of times.
0xE2C DebugGroupPush_StaticControl 1
0xE2D DebugGroupPush_StaticValue 1 This is written 3 times after DebugGroupPush_StaticControl.
0xE2E DebugGroupPop_Control 1
0xE2F DebugGroupPop_GroupId 1 This is written once after DebugGroupPop_Control.

TODO: SetRenderTargets, SetSubpixelPrecisionBias, SetTiledCacheAction, SetTiledCacheTileSize, SetViewports, UpdateUniformBuffer, TiledDownSample, BindVertexAttribState, BindVertexStreamState, Clear*, Copy*, Discard*, Dispatch*, Downsample, Draw*

DMA

Register Name Notes
0x0C0 CopyControl With 0x186 Src/DstStride is not used.
0x100 CopySrcAddrHi
0x101 CopySrcAddrLo
0x102 CopyDstAddrHi
0x103 CopyDstAddrLo
0x104 CopySrcStride?
0x105 CopyDstStride?
0x106 CopyCount At most 0x3FFFFF.
Retrieved from "https://switchbrew.org/w/index.php?title=GPU_Classes&oldid=4161"