TSEC: Difference between revisions

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During the transfer, the TSEC_DMA_CMD_BUSY bit is set.
During the transfer, the TSEC_DMA_CMD_BUSY bit is set.
Accessing an invalid address causes bit TSEC_DMA_CMD_ERROR to be set.


=== TSEC_DMA_ADDR ===
=== TSEC_DMA_ADDR ===