TSEC: Difference between revisions
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| Line 755: | Line 755: | ||
| 0x04 | | 0x04 | ||
|- | |- | ||
| [[# | | [[#TSEC_TFBIF_MMU_APERTURE_CTL|TSEC_TFBIF_MMU_APERTURE_CTL]] | ||
| 0x54501648 | | 0x54501648 | ||
| 0x04 | | 0x04 | ||
| Line 2,676: | Line 2,676: | ||
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout. | [6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout. | ||
=== | === TSEC_TFBIF_MMU_APERTURE_CTL === | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Bits | ! Bits | ||
! Description | ! Description | ||
|- | |- | ||
| 0- | | 0-2 | ||
| | | Aperture ID for CTXDMA port 0 | ||
|- | |- | ||
| 4- | | 4-6 | ||
| | | Aperture ID for CTXDMA port 1 | ||
|- | |- | ||
| 8- | | 8-10 | ||
| | | Aperture ID for CTXDMA port 2 | ||
|- | |- | ||
| 12- | | 12-14 | ||
| | | Aperture ID for CTXDMA port 3 | ||
|- | |- | ||
| 16- | | 16-18 | ||
| | | Aperture ID for CTXDMA port 4 | ||
|- | |- | ||
| 20- | | 20-22 | ||
| | | Aperture ID for CTXDMA port 5 | ||
|- | |- | ||
| 24- | | 24-26 | ||
| | | Aperture ID for CTXDMA port 6 | ||
|- | |- | ||
| 28- | | 28-30 | ||
| | | Aperture ID for CTXDMA port 7 | ||
|} | |} | ||
Controls | Controls the aperture ID of memory requests. Accessible in HS mode only. | ||
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout. | [6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout. | ||