TSEC: Difference between revisions
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| 0x04 | | 0x04 | ||
|- | |- | ||
| | | TSEC_TFBIF_CTL | ||
| 0x54501600 | | 0x54501600 | ||
| 0x04 | | 0x04 | ||
| Line 703: | Line 703: | ||
| 0x04 | | 0x04 | ||
|- | |- | ||
| | | TSEC_TFBIF_CTL1 | ||
| 0x54501630 | | 0x54501630 | ||
| 0x04 | | 0x04 | ||
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| 0x04 | | 0x04 | ||
|- | |- | ||
| | | [[#TSEC_TFBIF_MMU_PHYS_PROT|TSEC_TFBIF_MMU_PHYS_PROT]] | ||
| 0x54501640 | | 0x54501640 | ||
| 0x04 | | 0x04 | ||
|- | |- | ||
| [[# | | [[#TSEC_TFBIF_MMU_PHYS_SEC|TSEC_TFBIF_MMU_PHYS_SEC]] | ||
| 0x54501644 | | 0x54501644 | ||
| 0x04 | | 0x04 | ||
|- | |- | ||
| [[# | | [[#TSEC_TFBIF_MMU_PHYS_LIMIT|TSEC_TFBIF_MMU_PHYS_LIMIT]] | ||
| 0x54501648 | | 0x54501648 | ||
| 0x04 | |||
|- | |||
| TSEC_TFBIF_UNK_4C | |||
| 0x5450164C | |||
| 0x04 | |||
|- | |||
| TSEC_TFBIF_UNK_50 | |||
| 0x54501650 | |||
| 0x04 | |||
|- | |||
| TSEC_TFBIF_UNK_54 | |||
| 0x54501654 | |||
| 0x04 | | 0x04 | ||
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|} | |} | ||
=== | === TSEC_TFBIF_MMU_PHYS_PROT === | ||
{| class="wikitable" border="1" | |||
! Bits | |||
! Description | |||
|- | |||
| 0-3 | |||
| Read access level | |||
|- | |||
| 4-7 | |||
| Write access level | |||
|} | |||
Controls accesses to external memory in MMU physical mode. | |||
=== TSEC_TFBIF_MMU_PHYS_SEC === | |||
{| class="wikitable" border="1" | |||
! Bits | |||
! Description | |||
|- | |||
| 0 | |||
| Bypass MMU translation on CTXDMA port 0 | |||
|- | |||
| 4 | |||
| Bypass MMU translation on CTXDMA port 1 | |||
|- | |||
| 8 | |||
| Bypass MMU translation on CTXDMA port 2 | |||
|- | |||
| 12 | |||
| Bypass MMU translation on CTXDMA port 3 | |||
|- | |||
| 16 | |||
| Bypass MMU translation on CTXDMA port 4 | |||
|- | |||
| 20 | |||
| Bypass MMU translation on CTXDMA port 5 | |||
|- | |||
| 24 | |||
| Bypass MMU translation on CTXDMA port 6 | |||
|- | |||
| 28 | |||
| Bypass MMU translation on CTXDMA port 7 | |||
|} | |||
Configures MMU physical mode. | |||
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout. | [6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout. | ||
=== | === TSEC_TFBIF_MMU_PHYS_LIMIT === | ||
Configures the limit of the access window in MMU physical mode. | |||
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout. | [6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout. | ||