Difference between revisions of "GPU Classes"

From Nintendo Switch Brew
Jump to navigation Jump to search
Line 29: Line 29:
 
|-
 
|-
 
| 0xCE || Tesselation_InnerLevel1 ||
 
| 0xCE || Tesselation_InnerLevel1 ||
 +
|-
 +
| 0xDF || RasterizerDiscard_Enable || 1 means enabled, 0 means disabled.
 
|-
 
|-
 
| 0x1D1 || Transform_Pause ||
 
| 0x1D1 || Transform_Pause ||
Line 43: Line 45:
 
|-
 
|-
 
| 0x302+4*N || DepthRange_Unk1_N
 
| 0x302+4*N || DepthRange_Unk1_N
 +
|-
 +
| 0x303+4*N || DepthRange_Unk2_N
 
|-
 
|-
 
| 0x373 || PatchSize || Small value, always fits in 12 bits.
 
| 0x373 || PatchSize || Small value, always fits in 12 bits.
 +
|-
 +
| 0x381+4*N || Scissor0_N
 +
|-
 +
| 0x382+4*N || Scissor1_N
 +
|-
 +
| 0x3D5 || StencilMask1_Ref || 1 means enabled, 0 means disabled.
 +
|-
 +
| 0x3D6 || StencilMask1_Enable || 1 means enabled, 0 means disabled.
 +
|-
 +
| 0x3D7 || StencilMask1_ValueMask || 1 means enabled, 0 means disabled.
 
|-
 
|-
 
| 0x3E7 || DepthBounds_Bound0 || Float is written here.
 
| 0x3E7 || DepthBounds_Bound0 || Float is written here.
 
|-
 
|-
 
| 0x3E8 || DepthBounds_Bound1 || Float is written here.
 
| 0x3E8 || DepthBounds_Bound1 || Float is written here.
 +
|-
 +
| 0x3EF || SampleMask0 ||
 +
|-
 +
| 0x3F0 || SampleMask1 ||
 +
|-
 +
| 0x3F1 || SampleMask2 ||
 +
|-
 +
| 0x3F2 || SampleMask3 ||
 
|-
 
|-
 
| 0x452 || Raster_Enable || 1 means enabled, 0 means disabled.
 
| 0x452 || Raster_Enable || 1 means enabled, 0 means disabled.
 +
|-
 +
| 0x4E5 || StencilMask0_Ref || 1 means enabled, 0 means disabled.
 +
|-
 +
| 0x4E6 || StencilMask0_ValueMask || 1 means enabled, 0 means disabled.
 +
|-
 +
| 0x4E7 || StencilMask0_Enable || 1 means enabled, 0 means disabled.
 
|-
 
|-
 
| 0x4EC || LineWidth0 ||
 
| 0x4EC || LineWidth0 ||
Line 69: Line 97:
 
|-
 
|-
 
| 0x519 || ZCullCtx_Save || 0 is written here to trigger ctx-save, uses both ZCullCtx_Addr0/1.
 
| 0x519 || ZCullCtx_Save || 0 is written here to trigger ctx-save, uses both ZCullCtx_Addr0/1.
 +
|-
 +
| 0x51F || PolygonOffsetClamp0 || Float is written here.
 
|-
 
|-
 
| 0x540 || ZCullCtx_Restore || 0 is written here to trigger ctx-restore, uses both ZCullCtx_Addr0/1.
 
| 0x540 || ZCullCtx_Restore || 0 is written here to trigger ctx-restore, uses both ZCullCtx_Addr0/1.
 
|-
 
|-
 
| 0x546 || PointSize || Float is written here.
 
| 0x546 || PointSize || Float is written here.
 +
|-
 +
| 0x554 || RendererEnableConditionAddrHi ||
 +
|-
 +
| 0x555 || RendererEnableConditionAddrLo ||
 +
|-
 +
| 0x556 || RendererEnable || 0=disabled unconditional, 1=enabled unconditional, 3=unknown conditional, 4=unknown conditional,
 
|-
 
|-
 
| 0x54C || Counter_Reset || Value written decides which counter to reset.
 
| 0x54C || Counter_Reset || Value written decides which counter to reset.
 +
|-
 +
| 0x55B || PolygonOffsetClamp1 || Float is written here.
 +
|-
 +
| 0x56F || PolygonOffsetClamp2 || Float multiplied by 2 is written here.
 +
|-
 +
| 0x591 || PrimitiveRestart_Enable || 1 means enabled, 0 means disabled.
 +
|-
 +
| 0x592 || PrimitiveRestart_Value ||
 
|-
 
|-
 
| 0x64F || DepthClamp || 0x101A is written when enabled, 0x181D when disabled.
 
| 0x64F || DepthClamp || 0x101A is written when enabled, 0x181D when disabled.
Line 111: Line 155:
 
|}
 
|}
  
 +
TODO: SetRenderTargets, SetSubpixelPrecisionBias, SetTiledCacheAction, SetTiledCacheTileSize, SetViewports, UpdateUniformBuffer, TiledDownSample
  
 
= DMA =
 
= DMA =

Revision as of 02:44, 18 March 2018

Subchannels:

Id Subchannel (nvn) Name
0xB197 0 3D
0xB1C0 1 Compute
0xA140 2 Inline-to-Memory
0x902D 3 2D
0xB0B5 4 DMA

3D

Register Name Notes
0xC9 Tesselation_OuterLevel0
0xCA Tesselation_OuterLevel1
0xCB Tesselation_OuterLevel2
0xCC Tesselation_OuterLevel3
0xCD Tesselation_InnerLevel0
0xCE Tesselation_InnerLevel1
0xDF RasterizerDiscard_Enable 1 means enabled, 0 means disabled.
0x1D1 Transform_Pause
0x1FA ZCullCtx_Addr0Hi
0x1FB ZCullCtx_Addr0Lo
0x1FC ZCullCtx_Addr1Hi
0x1FD ZCullCtx_Addr1Lo
0x285+8*N DepthRange_Unk0_N
0x302+4*N DepthRange_Unk1_N
0x303+4*N DepthRange_Unk2_N
0x373 PatchSize Small value, always fits in 12 bits.
0x381+4*N Scissor0_N
0x382+4*N Scissor1_N
0x3D5 StencilMask1_Ref 1 means enabled, 0 means disabled.
0x3D6 StencilMask1_Enable 1 means enabled, 0 means disabled.
0x3D7 StencilMask1_ValueMask 1 means enabled, 0 means disabled.
0x3E7 DepthBounds_Bound0 Float is written here.
0x3E8 DepthBounds_Bound1 Float is written here.
0x3EF SampleMask0
0x3F0 SampleMask1
0x3F1 SampleMask2
0x3F2 SampleMask3
0x452 Raster_Enable 1 means enabled, 0 means disabled.
0x4E5 StencilMask0_Ref 1 means enabled, 0 means disabled.
0x4E6 StencilMask0_ValueMask 1 means enabled, 0 means disabled.
0x4E7 StencilMask0_Enable 1 means enabled, 0 means disabled.
0x4EC LineWidth0
0x4ED LineWidth1
0x4C4 AlphaRef Float is written here.
0x4C7 BlendColor0
0x4C8 BlendColor1
0x4C9 BlendColor2
0x4CA BlendColor3
0x47F DepthBuffer_Resolve 1 is written here to trigger.
0x519 ZCullCtx_Save 0 is written here to trigger ctx-save, uses both ZCullCtx_Addr0/1.
0x51F PolygonOffsetClamp0 Float is written here.
0x540 ZCullCtx_Restore 0 is written here to trigger ctx-restore, uses both ZCullCtx_Addr0/1.
0x546 PointSize Float is written here.
0x554 RendererEnableConditionAddrHi
0x555 RendererEnableConditionAddrLo
0x556 RendererEnable 0=disabled unconditional, 1=enabled unconditional, 3=unknown conditional, 4=unknown conditional,
0x54C Counter_Reset Value written decides which counter to reset.
0x55B PolygonOffsetClamp1 Float is written here.
0x56F PolygonOffsetClamp2 Float multiplied by 2 is written here.
0x591 PrimitiveRestart_Enable 1 means enabled, 0 means disabled.
0x592 PrimitiveRestart_Value
0x64F DepthClamp 0x101A is written when enabled, 0x181D when disabled.
0x66F DepthBounds_Enable 1 means enabled, 0 means disabled.
0x68B Barrier? Always 0 is written here. During zcull ctx-save, spammed when enabling raster, ...
0x6C0 Poke_AddrHi
0x6C1 Poke_AddrLo
0x6C2 Poke_WriteVal 0 is written here during most queries.
0x6C3 Poke_Control Big bitfield. After write, the result of query is written to 4 bytes at Poke_Addr.
0xD34 Used by SetConservativeRasterDilate.
0xE0A Used by SetConservativeRasterDilate.
0xE0B Used by SetConservativeRasterDilate.
0xE20 Another barrier? Used by SetConservativeRasterDilate.
0xE2A DebugGroupPush_DynamicControl
0xE2B DebugGroupPush_DynamicValue This one can be written a variable number of times.
0xE2C DebugGroupPush_StaticControl
0xE2D DebugGroupPush_StaticValue This is written 3 times after DebugGroupPush_StaticControl.
0xE2E DebugGroupPop_Control
0xE2F DebugGroupPop_GroupId This is written once after DebugGroupPop_Control.

TODO: SetRenderTargets, SetSubpixelPrecisionBias, SetTiledCacheAction, SetTiledCacheTileSize, SetViewports, UpdateUniformBuffer, TiledDownSample

DMA

Register Name Notes
0x0C0 Dma_Control With 0x186 Src/DstStride is not used.
0x100 Dma_SrcAddrHi
0x101 Dma_SrcAddrLo
0x102 Dma_DstAddrHi
0x103 Dma_DstAddrLo
0x104 Dma_SrcStride?
0x105 Dma_DstStride?
0x106 Dma_Count At most 0x3FFFFF.
Retrieved from "https://switchbrew.org/w/index.php?title=GPU_Classes&oldid=4131"