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|-
|-
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]
|-
| 0xC010002A || Inout || 16 || [S2]
|}
|}


Line 640: Line 642:
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
|-
|-
| ([1.0.0-3.0.0] 0xC0040217) || ([1.0.0-3.0.0] Inout) || ([1.0.0-3.0.0] 4) || ([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_OUT_EVENT)
| 0xC0040217 || Inout || 4 || [1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_OUT_EVENT
|-
|-
| 0xC0100218 || Inout || 16 || NVDISP_CTRL_GET_VBLANK_HEAD0_EVENT
| 0xC0100218 || Inout || 16 || NVDISP_CTRL_GET_VBLANK_HEAD0_EVENT
Line 1,540: Line 1,542:
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
|-
|-
| 0xC0684413 || Inout || 104 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
| 0xC0684413</br>[S2] 0xC0304413 || Inout || 104</br>48 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
|-
|-
| 0xC0184414 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
| 0xC0184414</br>[S2] 0xC0084414 || Inout || 24</br>8 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
|-
|-
| 0xC0184415 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
| 0xC0184415</br>[S2] 0xC0084415 || Inout || 24</br>8 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
|-
|-
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
Line 1,564: Line 1,566:
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
|-
|-
| [S2] 0xC0184421 || || ||
| 0x4008441F || In || 8 || [S2]  
|-
| 0x00004420 || None || 0 || [S2]
|-
| 0xC0184421 || Inout || 24 || [S2]
|-
| 0x40084422 || In || 8 || [S2]
|-
|-
| [S2] 0x40084422 || || ||
| 0xC0084423 || Inout || 8 || [S2]
|-
|-
| [S2] 0xC0084423 || || ||
| 0x40084424 || In || 8 || [S2]
|-
|-
| [S2] 0x40084424 || || ||
| 0xC0104425 || Inout || 16 || [S2]
|-
|-
| [S2] 0xC0104425 || || ||
| 0xC0184426 || Inout || 24 || [S2]
|-
|-
| [S2] 0x40084427 || || ||
| 0x40084427 || In || 8 || [S2]
|-
|-
| [S2] 0x40044428 || || ||
| 0x40044428 || In || 4 || [S2]
|-
|-
| [S2] 0xC0184429 || || ||
| 0xC0184429 || Inout || 24 || [S2]
|-
|-
| [S2] 0x4010442A || || ||
| 0x4010442A || In || 16 || [S2]
|-
|-
| [S2] 0x4010442B || || ||
| 0x4010442B || In || 16 || [S2]
|}
|}


Line 1,619: Line 1,627:
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
|-
|-
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
| 0xC0B04705</br>[S2] 0xC0E04705 || Inout || 176</br>[S2] 224|| [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
|-
|-
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
Line 1,637: Line 1,645:
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
|-
|-
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
| 0xC0044713</br>[S2] 0xC0084713 || Inout || 4</br>[S2] 8 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
|-
|-
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
Line 1,658: Line 1,666:
|-
|-
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|-
| 0xC010471E || Inout || 16 || [S2]
|-
| 0xC010471F || Inout || 16 || [S2]
|}
|}


Line 1,713: Line 1,725:


   struct gpu_characteristics {
   struct gpu_characteristics {
     u32 arch;                       // 0x120 (NVGPU_GPU_ARCH_GM200)
     u32 arch;                         // 0x120 (NVGPU_GPU_ARCH_GM200)
     u32 impl;                       // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
     u32 impl;                         // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
     u32 rev;                       // 0xA1 (Revision A1)
     u32 rev;                         // 0xA1 (Revision A1)
     u32 num_gpc;                   // 0x1
     u32 num_gpc;                     // 0x1
     u64 l2_cache_size;             // 0x40000
     u64 l2_cache_size;               // 0x40000
     u64 on_board_video_memory_size; // 0x0 (not used)
     u64 on_board_video_memory_size;   // 0x0 (not used)
     u32 num_tpc_per_gpc;           // 0x2
     u32 num_tpc_per_gpc;             // 0x2
     u32 bus_type;                   // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
     u32 bus_type;                     // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
     u32 big_page_size;             // 0x20000
     u32 big_page_size;               // 0x20000
     u32 compression_page_size;     // 0x20000
     u32 compression_page_size;       // 0x20000
     u32 pde_coverage_bit_count;     // 0x1B
     u32 pde_coverage_bit_count;       // 0x1B
     u32 available_big_page_sizes;   // 0x30000
     u32 available_big_page_sizes;     // 0x30000
     u32 gpc_mask;                   // 0x1
     u32 gpc_mask;                     // 0x1
     u32 sm_arch_sm_version;         // 0x503 (Maxwell Generation 5.0.3)
     u32 sm_arch_sm_version;           // 0x503 (Maxwell Generation 5.0.3)
     u32 sm_arch_spa_version;       // 0x503 (Maxwell Generation 5.0.3)
     u32 sm_arch_spa_version;         // 0x503 (Maxwell Generation 5.0.3)
     u32 sm_arch_warp_count;         // 0x80
     u32 sm_arch_warp_count;           // 0x80
     u32 gpu_va_bit_count;           // 0x28
     u32 gpu_va_bit_count;             // 0x28
     u32 reserved;                   // 0x0
     u32 reserved;                     // 0x0
     u64 flags;                     // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
     u64 flags;                       // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
     u32 twod_class;                 // 0x902D (FERMI_TWOD_A)
     u32 twod_class;                   // 0x902D (FERMI_TWOD_A)
     u32 threed_class;               // 0xB197 (MAXWELL_B)
     u32 threed_class;                 // 0xB197 (MAXWELL_B)
     u32 compute_class;             // 0xB1C0 (MAXWELL_COMPUTE_B)
     u32 compute_class;               // 0xB1C0 (MAXWELL_COMPUTE_B)
     u32 gpfifo_class;               // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
     u32 gpfifo_class;                 // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
     u32 inline_to_memory_class;     // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
     u32 inline_to_memory_class;       // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
     u32 dma_copy_class;             // 0xB0B5 (MAXWELL_DMA_COPY_A)
     u32 dma_copy_class;               // 0xB0B5 (MAXWELL_DMA_COPY_A)
     u32 max_fbps_count;             // 0x1
     u32 max_fbps_count;               // 0x1
     u32 fbp_en_mask;               // 0x0 (disabled)
     u32 fbp_en_mask;                 // 0x0 (disabled)
     u32 max_ltc_per_fbp;           // 0x2
     u32 max_ltc_per_fbp;             // 0x2
     u32 max_lts_per_ltc;           // 0x1
     u32 max_lts_per_ltc;             // 0x1
     u32 max_tex_per_tpc;           // 0x0 (not supported)
     u32 max_tex_per_tpc;             // 0x0 (not supported)
     u32 max_gpc_count;             // 0x1
     u32 max_gpc_count;               // 0x1
     u32 rop_l2_en_mask_0;           // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
     u32 rop_l2_en_mask_0;             // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
     u32 rop_l2_en_mask_1;           // 0x0
     u32 rop_l2_en_mask_1;             // 0x0
     u64 chipname;                   // 0x6230326D67 ("gm20b")
     u64 chipname;                     // 0x6230326D67 ("gm20b")
     u64 gr_compbit_store_base_hw;   // 0x0 (not supported)
     u64 gr_compbit_store_base_hw;     // 0x0 (not supported)
   };
   };
   
   
Line 1,759: Line 1,771:


   struct gpu_characteristics {
   struct gpu_characteristics {
     u32 arch;                       // 0x170
     u32 arch;                         // 0x170
     u32 impl;                       // 0xE
     u32 impl;                         // 0xE
     u32 rev;                       // 0xA1 (Revision A1)
     u32 rev;                         // 0xA1 (Revision A1)
     u32 num_gpc;                   // 0x1
     u32 num_gpc;                     // 0x1
     u64 l2_cache_size;             // 0x100000
     u64 l2_cache_size;               // 0x100000
     u64 on_board_video_memory_size; // 0x0 (not used)
     u64 on_board_video_memory_size;   // 0x0 (not used)
     u32 num_tpc_per_gpc;           // 0x6
     u32 num_tpc_per_gpc;             // 0x6
     u32 bus_type;                   // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
     u32 bus_type;                     // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
     u32 big_page_size;             // 0x0
     u32 big_page_size;               // 0x0
     u32 compression_page_size;     // 0x10000
     u32 compression_page_size;       // 0x10000
     u32 pde_coverage_bit_count;     // 0x15
     u32 pde_coverage_bit_count;       // 0x15
     u32 available_big_page_sizes;   // 0x0
     u32 available_big_page_sizes;     // 0x0
     u32 gpc_mask;                   // 0x1
     u32 gpc_mask;                     // 0x1
     u32 sm_arch_sm_version;         // 0x808
     u32 sm_arch_sm_version;           // 0x808
     u32 sm_arch_spa_version;       // 0x806
     u32 sm_arch_spa_version;         // 0x806
     u32 sm_arch_warp_count;         // 0x60
     u32 sm_arch_warp_count;           // 0x60
     u32 gpu_va_bit_count;           // 0x28
     u32 gpu_va_bit_count;             // 0x28
     u32 reserved;                   // 0x0
     u32 reserved;                     // 0x0
     u64 flags;                     // 0x935FAF1EDC0155
     u64 flags;                       // 0x935FAF1EDC0155
     u32 twod_class;                 // 0x902D (FERMI_TWOD_A)
     u32 twod_class;                   // 0x902D (FERMI_TWOD_A)
     u32 threed_class;               // 0xC797 (AMPERE_B)
     u32 threed_class;                 // 0xC797 (AMPERE_B)
     u32 compute_class;             // 0xC7C0 (AMPERE_COMPUTE_B)
     u32 compute_class;               // 0xC7C0 (AMPERE_COMPUTE_B)
     u32 gpfifo_class;               // 0xC76F (AMPERE_CHANNEL_GPFIFO_B)
     u32 gpfifo_class;                 // 0xC76F (AMPERE_CHANNEL_GPFIFO_B)
     u32 inline_to_memory_class;     // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
     u32 inline_to_memory_class;       // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
     u32 dma_copy_class;             // 0xC7B5 (AMPERE_DMA_COPY_B)
     u32 dma_copy_class;               // 0xC7B5 (AMPERE_DMA_COPY_B)
     u32 unk0;                       // 0xF001F
     s16 gpu_ioctl_nr_last;            // 0x1F
     u32 unk1;                       // 0x21002B
    s16 tsg_ioctl_nr_last;            // 0xF
     u32 unk2;                       // 0xFFFF000D
    s16 dbg_gpu_ioctl_nr_last;        // 0x2B
     u32 unk3;                       // 0xFFFFFFFF
    s16 ioctl_channel_nr_last;        // 0x21
     u32 unk4;                       // 0x0
    s16 as_ioctl_nr_last;             // 0xD
     u32 unk5;                       // 0x1
     s16 unk0_ioctl_nr_last;           // 0xFFFF
     u32 unk6;                       // 0x1
     s16 unk1_ioctl_nr_last;           // 0xFFFF
     u32 unk7;                       // 0x1
     s16 unk2_ioctl_nr_last;           // 0xFFFF
     u32 unk8;                       // 0x4
     u32 max_fbps_count;               // 0x0
     u32 unk9;                       // 0x0
     u32 fbp_en_mask;                 // 0x1
     u32 unk10;                     // 0x1
     u32 emc_en_mask;                 // 0x1
     u32 unk11;                     // 0x0
     u32 max_ltc_per_fbp;             // 0x1
     u32 unk12;                     // 0x0
     u32 max_lts_per_ltc;             // 0x4
     u64 chipname;                   // 0x6761313066 ("ga10f")
     u32 max_tex_per_tpc;             // 0x0
     u32 unk13;                     // 0x0
     u32 max_gpc_count;               // 0x1
     u32 unk14;                     // 0x2
     u32 rop_l2_en_mask_DEPRECATED_0; // 0x0
     u32 unk15;                     // 0x40
     u32 rop_l2_en_mask_DEPRECATED_1; // 0x0
     u32 unk16;                     // 0x3
     u64 chipname;                     // 0x6761313066 ("ga10f")
     u32 unk17;                     // 0x7
     u32 unk0;                         // 0x0
     u32 unk18;                     // 0x1
     u32 unk1;                         // 0x2
     u32 unk19;                     // 0x1
     u32 unk2;                         // 0x40
     u32 unk20;                     // 0x0
     u32 unk3;                         // 0x3
     u32 unk21;                     // 0x0
     u32 unk4;                         // 0x7
     u32 unk5;                         // 0x1
     u32 unk6;                         // 0x1
     u32 unk7;                         // 0x0
     u32 unk8;                         // 0x0
   };
   };
    
    
Line 1,993: Line 2,009:
   __in u32    source_id;                            // cpu clock source id (must be 1)
   __in u32    source_id;                            // cpu clock source id (must be 1)
  };
  };
== (Switch 2) /dev/nvhost-prof-dev-gpu ==                                                                                                         
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0x40085001 || In || 8 ||
|-
| 0x40105002 || In || 16 ||
|-
| 0xC0305004 || Inout || 48 ||
|-
| 0x00005005 || None || 0 ||
|-
| 0x00005006 || None || 0 ||
|-
| 0x00005007 || None || 0 ||
|-
| 0xC0285008 || Inout || 40 ||
|-
| 0xC0205009 || Inout || 32 ||
|-
| 0x0000500A || None || 0 ||
|-
| 0x4010500B || In || 16 ||
|-
| 0x0000500C || None || 0 ||
|-
| 0x4010500D || In || 16 || 
|}
== (Switch 2) /dev/nvhost-tsg-gpu ==                                                                                   
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0xC0045401 || Inout || 4 || NVGPU_TSG_IOCTL_BIND_CHANNEL
|-
| 0xC0045402 || Inout || 4 || NVGPU_TSG_IOCTL_UNBIND_CHANNEL
|-
| 0x00005403 || None || 0 || NVGPU_IOCTL_TSG_ENABLE
|-
| 0x00005404 || None || 0 || NVGPU_IOCTL_TSG_DISABLE
|-
| 0x00005405 || None || 0 || NVGPU_IOCTL_TSG_PREEMPT
|-
| 0xC0085407 || Inout || 8 || NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE
|-
| 0xC0045408 || Inout || 4 || NVGPU_IOCTL_TSG_SET_TIMESLICE
|-
| 0xC0105409 || Inout || 16 ||
|-
| 0x8004540A || Out || 4 ||
|-
| 0xC018540B || Inout || 24 ||
|-
| 0xC018540C || Inout || 24 ||
|-
| 0xC008540D || Inout || 8 ||
|}


= Channels =
= Channels =
Line 2,017: Line 2,091:
== Ioctls ==
== Ioctls ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Value || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
| 0xC0??0001 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
|-
|-
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
| 0xC0080002 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
|-
|-
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
| 0xC0080003 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
|-
|-
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
| 0xC0080004 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
|-
|-
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
| 0x40040007 || In || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
|-
|-
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
| 0x40080008 || In || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
|-
|-
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
| 0xC0??0009 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
|-
|-
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
| 0xC0??000A || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
|-
|-
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
| 0x00000013 || None || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
|-
|-
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
|-
|-
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
| 0xC0??0024 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
|-
|-
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
| 0xC0??0025 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
|-
|-
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
| 0xC0??0026 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
|- style="border-top: double"
|- style="border-top: double"
| 0x40044801 [S2] 0x40044101 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
| 0x40044801 || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
|-
|-
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
| 0x40044803 || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
|-
|-
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
| 0x40084805 || In || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
|-
|-
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
| 0x40184806 || In || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
|-
|-
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
| 0xC0044807 || Inout || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
|-
|-
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
| 0xC0??4808 || Inout || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
|-
|-
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
| 0xC0104809 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
|-
|-
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
| 0x4008480A || In || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
|-
|-
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
| 0xC010480B || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
|-
|-
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
| 0xC018480C || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
|-
|-
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
| 0x4004480D || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
|-
|-
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
| 0x0000480E || None || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
|-
|-
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
| 0x0000480F || None || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
|-
|-
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
| 0x00004810 || None || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
|-
|-
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
| 0x00004811 || None ||  0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
|-
|-
| 0x40084812 [S2] 0x40104812 || 8 [S2] 16 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
| 0x40084812</br>[S2] 0x40104812 || In || 8</br>[S2] 16 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
|-
|-
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
| 0xC0104813 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
|-
|-
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
| 0x40084714 || In || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
|-
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
| 0x80084715 || Out || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|-
|-
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
| 0x80804816 || Out || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
|-
|-
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
| 0xC0104817 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
|-
|-
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
| 0x40204818 || In || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
|-
|-
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
| 0xC0??4819 || Inout || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
|-
|-
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
| 0xC020481A || Inout || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
|-
|-
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
| 0xC018481B || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
|-
|-
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
| 0xC018481C || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
|-
|-
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
| 0xC004481D || Inout || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
|- style="border-top: double"
|-
| [S2] 0xC010481E || 16 ||
| 0xC010481E || Inout || 16 || [S2]
|-
|-
| [S2] 0xC008481F || 8 ||
| 0xC008481F || Inout || 8 || [S2]
|-
|-
| [S2] 0x40044820 || 4 ||  
| 0x40044820 || In || 4 || [S2]
|-
|-
| [S2] 0xC0504821 || 80 ||  
| 0xC0504821 || Inout || 80 || [S2]
|}
|}


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