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Line 16: Line 16:
! Cmd || Name
! Cmd || Name
|-
|-
| 0 || [[#Open]]
| 0 || [[#Open|Open]]
|-
|-
| 1 || [[#Ioctl]]
| 1 || [[#Ioctl|Ioctl]]
|-
|-
| 2 || [[#Close]]
| 2 || [[#Close|Close]]
|-
|-
| 3 || [[#Initialize]]
| 3 || [[#Initialize|Initialize]]
|-
|-
| 4 || [[#QueryEvent]]
| 4 || [[#QueryEvent|QueryEvent]]
|-
|-
| 5 || [[#MapSharedMem]]
| 5 || [[#MapSharedMem|MapSharedMem]]
|-
|-
| 6 || [[#GetStatus]]
| 6 || [[#GetStatus|GetStatus]]
|-
|-
| 7 || [[#SetAruidWithoutCheck]]
| 7 || [[#SetAruidWithoutCheck|SetAruidWithoutCheck]]
|-
|-
| 8 || [[#SetAruid]]
| 8 || [[#SetAruid|SetAruid]]
|-
|-
| 9 || [[#DumpStatus]]
| 9 || [[#DumpStatus|DumpStatus]]
|-
|-
| 10 || [3.0.0+] [[#InitializeDevtools]]
| 10 || [3.0.0+] [[#InitializeDevtools|InitializeDevtools]]
|-
|-
| 11 || [3.0.0+] [[#Ioctl2]]
| 11 || [3.0.0+] [[#Ioctl2|Ioctl2]]
|-
|-
| 12 || [3.0.0+] [[#Ioctl3]]
| 12 || [3.0.0+] [[#Ioctl3|Ioctl3]]
|-
|-
| 13 || [3.0.0+] [[#SetGraphicsFirmwareMemoryMarginEnabled]]
| 13 || [3.0.0+] [[#SetGraphicsFirmwareMemoryMarginEnabled|SetGraphicsFirmwareMemoryMarginEnabled]]
|}
|}


Line 146: Line 146:


== SetGraphicsFirmwareMemoryMarginEnabled ==
== SetGraphicsFirmwareMemoryMarginEnabled ==
Unofficial name.
Takes an input u64. No output.
Takes an input u64. No output.


Line 179: Line 181:
! Cmd || Name
! Cmd || Name
|-
|-
| 0 || [[#DebugFSOpen]]
| 0 || [[#DebugFSOpen|DebugFSOpen]]
|-
|-
| 1 || [[#DebugFSClose]]
| 1 || [[#DebugFSClose|DebugFSClose]]
|-
|-
| 2 || [[#GetDebugFSKeys]]
| 2 || [[#GetDebugFSKeys|GetDebugFSKeys]]
|-
|-
| 3 || [[#GetDebugFSValue]]
| 3 || [[#GetDebugFSValue|GetDebugFSValue]]
|-
|-
| 4 || [[#SetDebugFSValue]]
| 4 || [[#SetDebugFSValue|SetDebugFSValue]]
|}
|}


Line 296: Line 298:


This service has no commands.
This service has no commands.
= (S2) INvDrv2User =
This is "nn::nvdrv::INvDrv2User".
{| class="wikitable" border="1"
|-
! Cmd || Name
|-
| 0 || Open
|-
| 1 || Ioctl
|-
| 2 || Close
|-
| 4 || QueryEvent
|-
| 9 || DumpStatus
|-
| 10 || InitializeDevtools
|-
| 11 || Ioctl2
|-
| 12 || Ioctl3
|-
| 13 || [[#SetConfiguration|SetConfiguration]]
|}
== SetConfiguration ==
Unofficial name.
Takes an input u64 '''Configuration'''. No output.
Bit 0 in '''Configuration''' represents the old '''GraphicsFirmwareMemoryMarginEnabled''' option.


= Ioctls =
= Ioctls =
Line 309: Line 344:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0xC0080014 || Inout || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_READ]]
| 0xC0080014 || Inout || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_READ|NVHOST_IOCTL_CTRL_SYNCPT_READ]]
|-
|-
| 0x40040015 || In || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_INCR]]
| 0x40040015 || In || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_INCR|NVHOST_IOCTL_CTRL_SYNCPT_INCR]]
|-
|-
| 0xC00C0016 || Inout || 12 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT]]
| 0xC00C0016 || Inout || 12 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT]]
|-
|-
| 0x40080017 || In || 8 || [[#NVHOST_IOCTL_CTRL_MODULE_MUTEX]]
| 0x40080017 || In || 8 || [[#NVHOST_IOCTL_CTRL_MODULE_MUTEX|NVHOST_IOCTL_CTRL_MODULE_MUTEX]]
|-
|-
| 0xC0180018 || Inout || 24 || [[#NVHOST_IOCTL_CTRL_MODULE_REGRDWR]]
| 0xC0180018 || Inout || 24 || [[#NVHOST_IOCTL_CTRL_MODULE_REGRDWR|NVHOST_IOCTL_CTRL_MODULE_REGRDWR]]
|-
|-
| 0xC0100019 || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]]
| 0xC0100019 || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]]
|-
|-
| 0xC008001A || Inout || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_READ_MAX]]
| 0xC008001A || Inout || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_READ_MAX|NVHOST_IOCTL_CTRL_SYNCPT_READ_MAX]]
|-
|-
| 0xC183001B || Inout || 387 || [[#NVHOST_IOCTL_CTRL_GET_CONFIG]]
| 0xC183001B || Inout || 387 || [[#NVHOST_IOCTL_CTRL_GET_CONFIG|NVHOST_IOCTL_CTRL_GET_CONFIG]]
|-
|-
| 0xC004001C || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT]]
| 0xC004001C || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT|NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT]]
|-
|-
| 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]
| 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]
|-
|-
| 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]]
| 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]]
|-
|-
| 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT]]
| 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT]]
|-
|-
| 0xC0040020 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT]]
| 0xC0040020 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT]]
|-
|-
| 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH]]
| 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH|NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH]]
|-
|-
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT|NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]
|-
|-
| 0xC0080027 || Inout || 8 || [S2] NVHOST_IOCTL_CTRL_ALLOC_SYNCPT
| 0xC0080027 || Inout || 8 || [S2] NVHOST_IOCTL_CTRL_ALLOC_SYNCPT
Line 468: Line 503:


=== NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT ===
=== NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT ===
Unofficial name.
Returns the syncpt shift value.
Returns the syncpt shift value.


Line 478: Line 515:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0xC0080101 || Inout || 8 || [[#NVMAP_IOC_CREATE]]
| 0xC0080101 || Inout || 8 || [[#NVMAP_IOC_CREATE|NVMAP_IOC_CREATE]]
|-
|-
| 0x00000102 || - || 0 || [[#NVMAP_IOC_CLAIM]]
| 0x00000102 || - || 0 || [[#NVMAP_IOC_CLAIM|NVMAP_IOC_CLAIM]]
|-
|-
| 0xC0080103 || Inout || 8 || [[#NVMAP_IOC_FROM_ID]]
| 0xC0080103 || Inout || 8 || [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]]
|-
|-
| 0xC0200104 || Inout || 32 || [[#NVMAP_IOC_ALLOC]]
| 0xC0200104 || Inout || 32 || [[#NVMAP_IOC_ALLOC|NVMAP_IOC_ALLOC]]
|-
|-
| 0xC0180105 || Inout || 24 || [[#NVMAP_IOC_FREE]]
| 0xC0180105 || Inout || 24 || [[#NVMAP_IOC_FREE|NVMAP_IOC_FREE]]
|-
|-
| 0xC0280106 || Inout || 40 || [[#NVMAP_IOC_MMAP]]
| 0xC0280106 || Inout || 40 || [[#NVMAP_IOC_MMAP|NVMAP_IOC_MMAP]]
|-
|-
| 0xC0280107 || Inout || 40 || [[#NVMAP_IOC_WRITE]]
| 0xC0280107 || Inout || 40 || [[#NVMAP_IOC_WRITE|NVMAP_IOC_WRITE]]
|-
|-
| 0xC0280108 || Inout || 40 || [[#NVMAP_IOC_READ]]
| 0xC0280108 || Inout || 40 || [[#NVMAP_IOC_READ|NVMAP_IOC_READ]]
|-
|-
| 0xC00C0109 || Inout || 12 || [[#NVMAP_IOC_PARAM]]
| 0xC00C0109 || Inout || 12 || [[#NVMAP_IOC_PARAM|NVMAP_IOC_PARAM]]
|-
|-
| 0xC010010A || Inout || 16 || [[#NVMAP_IOC_PIN_MULT]]
| 0xC010010A || Inout || 16 || [[#NVMAP_IOC_PIN_MULT|NVMAP_IOC_PIN_MULT]]
|-
|-
| 0xC010010B || Inout || 16 || [[#NVMAP_IOC_UNPIN_MULT]]
| 0xC010010B || Inout || 16 || [[#NVMAP_IOC_UNPIN_MULT|NVMAP_IOC_UNPIN_MULT]]
|-
|-
| 0xC008010C || Inout || 8 || [[#NVMAP_IOC_CACHE]]
| 0xC008010C || Inout || 8 || [[#NVMAP_IOC_CACHE|NVMAP_IOC_CACHE]]
|-
|-
| 0xC004010D || Inout || 4 || [[#NVMAP_IOC_GET_IVC_ID]]
| 0xC004010D || Inout || 4 || [[#NVMAP_IOC_GET_IVC_ID|NVMAP_IOC_GET_IVC_ID]]
|-
|-
| 0xC008010E || Inout || 8 || [[#NVMAP_IOC_GET_ID]]
| 0xC008010E || Inout || 8 || [[#NVMAP_IOC_GET_ID|NVMAP_IOC_GET_ID]]
|-
|-
| 0xC004010F || Inout || 4 || [[#NVMAP_IOC_FROM_IVC_ID]]
| 0xC004010F || Inout || 4 || [[#NVMAP_IOC_FROM_IVC_ID|NVMAP_IOC_FROM_IVC_ID]]
|-
|-
| 0x40040110 || In || 4 || [[#NVMAP_IOC_SET_ALLOCATION_TAG_LABEL]]
| 0x40040110 || In || 4 || [[#NVMAP_IOC_SET_ALLOCATION_TAG_LABEL|NVMAP_IOC_SET_ALLOCATION_TAG_LABEL]]
|-
|-
| 0x00000111 || - || 0 || [[#NVMAP_IOC_RESERVE]]
| 0x00000111 || - || 0 || [[#NVMAP_IOC_RESERVE|NVMAP_IOC_RESERVE]]
|-
|-
| 0x40100112 || In || 16 || [[#NVMAP_IOC_EXPORT_FOR_ARUID]]
| 0x40100112 || In || 16 || [[#NVMAP_IOC_EXPORT_FOR_ARUID|NVMAP_IOC_EXPORT_FOR_ARUID]]
|-
|-
| 0x40100113 || In || 16 || [[#NVMAP_IOC_IS_OWNED_BY_ARUID]]
| 0x40100113 || In || 16 || [[#NVMAP_IOC_IS_OWNED_BY_ARUID|NVMAP_IOC_IS_OWNED_BY_ARUID]]
|-
|-
| 0x40100114 || In || 16 || [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]]
| 0x40100114 || In || 16 || [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID|NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]]
|}
|}


Line 547: Line 584:
     __inout u32 align;
     __inout u32 align;
     __in u8  kind;
     __in u8  kind;
     u8       pad[7];
     __in u8 pad[7];
     __in u64 addr;
     __in u64 addr;
   };
   };
Line 556: Line 593:
   struct {
   struct {
     __in  u32 handle;
     __in  u32 handle;
     u32       pad;
     __in  u32 pad;
     __out u64 address;  // 0 if the handle wasn't yet freed
     __out u64 address;  // 0 if the handle wasn't yet freed
     __out u32 size;
     __out u32 size;
Line 615: Line 652:
     __in  u64 aruid;
     __in  u64 aruid;
     __in  u32 handle;
     __in  u32 handle;
     u8       pad[4];
     __in  u8 pad[4];
   };
   };


Line 624: Line 661:
     __in  u64 aruid;
     __in  u64 aruid;
     __in  u32 handle;
     __in  u32 handle;
     u8       pad[4];
     __in  u8 pad[4];
   };
   };


Line 633: Line 670:
     __in  u64 aruid;
     __in  u64 aruid;
     __in  u32 handle;
     __in  u32 handle;
     u8       pad[4];
     __in  u8 pad[4];
   };
   };


Line 640: Line 677:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0x80040212 || Out || 4 || [[#NVDISP_CTRL_NUM_OUTPUTS]]
| 0x80040212 || Out || 4 || [[#NVDISP_CTRL_NUM_OUTPUTS|NVDISP_CTRL_NUM_OUTPUTS]]
|-
|-
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES
Line 656: Line 693:
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND
|-
|-
| 0x80010224 || Out || 1 || [11.0.0+] [[#NVDISP_CTRL_IS_DISPLAY_OLED]]
| 0x80010224 || Out || 1 || [11.0.0+] [[#NVDISP_CTRL_IS_DISPLAY_OLED|NVDISP_CTRL_IS_DISPLAY_OLED]]
|}
|}


=== NVDISP_CTRL_NUM_OUTPUTS ===
=== NVDISP_CTRL_NUM_OUTPUTS ===
Returns the number of display outputs available.


   struct {
   struct {
Line 666: Line 704:


=== NVDISP_CTRL_IS_DISPLAY_OLED ===
=== NVDISP_CTRL_IS_DISPLAY_OLED ===
Unofficial name.


This sets a boolean value based on the values of the system configuration.
This sets a boolean value based on the values of the system configuration.
Line 685: Line 724:
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
|-
|-
| 0x80380204 || Out || 56 || [[#NVDISP_GET_MODE]]
| 0x80380204 || Out || 56 || [[#NVDISP_GET_MODE|NVDISP_GET_MODE]]
|-
|-
| 0x40380205 || In || 56 || [[#NVDISP_SET_MODE]]
| 0x40380205 || In || 56 || [[#NVDISP_SET_MODE|NVDISP_SET_MODE]]
|-
|-
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
Line 697: Line 736:
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
|-
|-
| 0xC038020A || Inout || 56 || [[#NVDISP_VALIDATE_MODE]]
| 0xC038020A || Inout || 56 || [[#NVDISP_VALIDATE_MODE|NVDISP_VALIDATE_MODE]]
|-
|-
| 0x4018020B || In || 24 || NVDISP_SET_CSC
| 0x4018020B || In || 24 || NVDISP_SET_CSC
Line 709: Line 748:
| 0xC004020F || Inout || 4 || NVDISP_DPMS
| 0xC004020F || Inout || 4 || NVDISP_DPMS
|-
|-
| 0x80600210 || Out || 96 || [[#NVDISP_GET_AVI_INFOFRAME]]
| 0x80600210 || Out || 96 || [[#NVDISP_GET_AVI_INFOFRAME|NVDISP_GET_AVI_INFOFRAME]]
|-
|-
| 0x40600211 || In || 96 || [[#NVDISP_SET_AVI_INFOFRAME]]
| 0x40600211 || In || 96 || [[#NVDISP_SET_AVI_INFOFRAME|NVDISP_SET_AVI_INFOFRAME]]
|-
|-
| 0xEBFC0215 || Inout || 11260 || [[#NVDISP_GET_MODE_DB]]
| 0xEBFC0215 || Inout || 11260 || [[#NVDISP_GET_MODE_DB|NVDISP_GET_MODE_DB]]
|-
|-
| 0xC003021A || Inout || 3 || [[#NVDISP_PANEL_GET_VENDOR_ID]]
| 0xC003021A || Inout || 3 || [[#NVDISP_PANEL_GET_VENDOR_ID|NVDISP_PANEL_GET_VENDOR_ID]]
|-
|-
| 0x803C021B || Out || 60 || [[#NVDISP_GET_MODE2]]
| 0x803C021B || Out || 60 || [[#NVDISP_GET_MODE2|NVDISP_GET_MODE2]]
|-
|-
| 0x403C021C || In || 60 || [[#NVDISP_SET_MODE2]]
| 0x403C021C || In || 60 || [[#NVDISP_SET_MODE2|NVDISP_SET_MODE2]]
|-
|-
| 0xC03C021D || Inout || 60 || [[#NVDISP_VALIDATE_MODE2]]
| 0xC03C021D || Inout || 60 || [[#NVDISP_VALIDATE_MODE2|NVDISP_VALIDATE_MODE2]]
|-
|-
| 0xEF20021E || Inout || 12064 || [[#NVDISP_GET_MODE_DB2]]
| 0xEF20021E || Inout || 12064 || [[#NVDISP_GET_MODE_DB2|NVDISP_GET_MODE_DB2]]
|-
|-
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
|-
|-
| 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE]]
| 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE|NVDISP_GET_BACKLIGHT_RANGE]]
|-
|-
| 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MAX]]
| 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MAX|NVDISP_SET_BACKLIGHT_RANGE_MAX]]
|-
|-
| 0x40040223 || In || 4 || [11.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MIN]]
| 0x40040223 || In || 4 || [11.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MIN|NVDISP_SET_BACKLIGHT_RANGE_MIN]]
|-
|-
| 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG]]
| 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG|NVDISP_SEND_PANEL_MSG]]
|-
|-
| 0xC01C0226 || Inout || 28 || [11.0.0+] [[#NVDISP_GET_PANEL_DATA]]
| 0xC01C0226 || Inout || 28 || [11.0.0+] [[#NVDISP_GET_PANEL_DATA|NVDISP_GET_PANEL_DATA]]
|}
|}


Line 884: Line 923:


=== NVDISP_PANEL_GET_VENDOR_ID ===
=== NVDISP_PANEL_GET_VENDOR_ID ===
Returns display panel's informations.
Returns display panel's informations.


Line 979: Line 1,017:


=== NVDISP_GET_BACKLIGHT_RANGE ===
=== NVDISP_GET_BACKLIGHT_RANGE ===
Unofficial name.
Returns the minimum and maximum values for the intensity of the display's backlight.
Returns the minimum and maximum values for the intensity of the display's backlight.


Line 987: Line 1,027:


=== NVDISP_SET_BACKLIGHT_RANGE_MAX ===
=== NVDISP_SET_BACKLIGHT_RANGE_MAX ===
Unofficial name.
Sets the maximum value for the intensity of the display's backlight.
Sets the maximum value for the intensity of the display's backlight.


Line 994: Line 1,036:


=== NVDISP_SET_BACKLIGHT_RANGE_MIN ===
=== NVDISP_SET_BACKLIGHT_RANGE_MIN ===
Unofficial name.
Sets the minimum value for the intensity of the display's backlight.
Sets the minimum value for the intensity of the display's backlight.


Line 1,001: Line 1,045:


=== NVDISP_SEND_PANEL_MSG ===
=== NVDISP_SEND_PANEL_MSG ===
Unofficial name.
Sends raw data to the display panel over DPAUX.
Sends raw data to the display panel over DPAUX.


Line 1,011: Line 1,057:


=== NVDISP_GET_PANEL_DATA ===
=== NVDISP_GET_PANEL_DATA ===
Unofficial name.
Receives raw data from the display panel over DPAUX.
Receives raw data from the display panel over DPAUX.


Line 1,060: Line 1,108:
| 0x40010501 || In || 1 || NVDCUTIL_ENABLE_CRC
| 0x40010501 || In || 1 || NVDCUTIL_ENABLE_CRC
|-
|-
| 0x40010502 || In || 1 || [[#NVDCUTIL_VIRTUAL_EDID_ENABLE]]
| 0x40010502 || In || 1 || [[#NVDCUTIL_VIRTUAL_EDID_ENABLE|NVDCUTIL_VIRTUAL_EDID_ENABLE]]
|-
|-
| 0x42040503 || In || 516 || [[#NVDCUTIL_VIRTUAL_EDID_SET_DATA]]
| 0x42040503 || In || 516 || [[#NVDCUTIL_VIRTUAL_EDID_SET_DATA|NVDCUTIL_VIRTUAL_EDID_SET_DATA]]
|-
|-
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
Line 1,082: Line 1,130:


=== NVDCUTIL_VIRTUAL_EDID_ENABLE ===
=== NVDCUTIL_VIRTUAL_EDID_ENABLE ===
Enables virtual EDID.


   struct {
   struct {
Line 1,088: Line 1,137:


=== NVDCUTIL_VIRTUAL_EDID_SET_DATA ===
=== NVDCUTIL_VIRTUAL_EDID_SET_DATA ===
Sets virtual EDID data.


   struct {
   struct {
Line 1,102: Line 1,152:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE]]
| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE|NVSCHED_CTRL_ENABLE]]
|-
|-
| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE]]
| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE|NVSCHED_CTRL_DISABLE]]
|-
|-
| 0x40180603 || In || 24 || [[#NVSCHED_CTRL_ADD_APPLICATION]]
| 0x40180603 || In || 24 || [[#NVSCHED_CTRL_ADD_APPLICATION|NVSCHED_CTRL_ADD_APPLICATION]]
|-
|-
| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION]]
| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION|NVSCHED_CTRL_UPDATE_APPLICATION]]
|-
|-
| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION]]
| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION|NVSCHED_CTRL_REMOVE_APPLICATION]]
|-
|-
| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID]]
| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID|NVSCHED_CTRL_GET_ID]]
|-
|-
| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST]]
| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST|NVSCHED_CTRL_ADD_RUNLIST]]
|-
|-
| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST]]
| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST|NVSCHED_CTRL_UPDATE_RUNLIST]]
|-
|-
| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST]]
| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST|NVSCHED_CTRL_LINK_RUNLIST]]
|-
|-
| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST]]
| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST|NVSCHED_CTRL_UNLINK_RUNLIST]]
|-
|-
| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST]]
| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST|NVSCHED_CTRL_REMOVE_RUNLIST]]
|-
|-
| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]]
| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT|NVSCHED_CTRL_HAS_OVERRUN_EVENT]]
|-
|-
| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]
| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT|NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]
|-
|-
| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]
| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE|NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]
|-
|-
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION|NVSCHED_CTRL_DETACH_APPLICATION]]
|-
|-
| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT
| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT
Line 1,255: Line 1,305:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA]]
| 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA|NVERPT_TELEMETRY_SUBMIT_DATA]]
|-
|-
| 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]]
| 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA|NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]]
|}
|}


=== NVERPT_TELEMETRY_SUBMIT_DATA ===
=== NVERPT_TELEMETRY_SUBMIT_DATA ===
Unofficial name.
Sends test data for creating a new [[Error_Report_services|Error Report]].
Sends test data for creating a new [[Error_Report_services|Error Report]].


Line 1,288: Line 1,340:


=== NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA ===
=== NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA ===
Unofficial name.
Sends display data for creating a new [[Error_Report_services|Error Report]].
Sends display data for creating a new [[Error_Report_services|Error Report]].


Line 1,322: Line 1,376:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL]]
| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL|NVGPU_AS_IOCTL_BIND_CHANNEL]]
|-
|-
| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE]]
| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE|NVGPU_AS_IOCTL_ALLOC_SPACE]]
|-
|-
| 0xC0104103 || Inout || 16 || [[#NVGPU_AS_IOCTL_FREE_SPACE]]
| 0xC0104103 || Inout || 16 || [[#NVGPU_AS_IOCTL_FREE_SPACE|NVGPU_AS_IOCTL_FREE_SPACE]]
|-
|-
| 0xC0184104 || Inout || 24 || [[#NVGPU_AS_IOCTL_MAP_BUFFER]]
| 0xC0184104 || Inout || 24 || [[#NVGPU_AS_IOCTL_MAP_BUFFER|NVGPU_AS_IOCTL_MAP_BUFFER]]
|-
|-
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER|NVGPU_AS_IOCTL_UNMAP_BUFFER]]
|-
|-
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX|NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
|-
|-
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS|NVGPU_AS_IOCTL_ALLOC_AS]]
|-
|-
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS]]
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS|NVGPU_AS_IOCTL_GET_VA_REGIONS]]
|-
|-
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX|NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
|-
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2|NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
|-
|-
| 0x8010410B || Out || 16 || [S2] NVGPU_AS_IOCTL_GET_SYNC_RO_MAP
| 0x8010410B || Out || 16 || [S2] [[#NVGPU_AS_IOCTL_GET_SYNC_RO_MAP|NVGPU_AS_IOCTL_GET_SYNC_RO_MAP]]
|-
|-
| 0xC020410C || Inout || 32 || [S2] NVGPU_AS_IOCTL_MAPPING_MODIFY
| 0xC020410C || Inout || 32 || [S2] [[#NVGPU_AS_IOCTL_MAPPING_MODIFY|NVGPU_AS_IOCTL_MAPPING_MODIFY]]
|-
|-
| 0xC???410D || Inout || Variable || [S2] NVGPU_AS_IOCTL_REMAP
| 0xC???410D || Inout || Variable || [S2] [[#NVGPU_AS_IOCTL_REMAP|NVGPU_AS_IOCTL_REMAP]]
|-
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP_2|NVGPU_AS_IOCTL_REMAP]]
|}
|}


Line 1,365: Line 1,419:
     __in u32 page_size;
     __in u32 page_size;
     __in u32 flags;
     __in u32 flags;
     u32     padding;
     __in u32 padding;
     union {
     union {
       __out u64 offset;
       __out u64 offset;
Line 1,390: Line 1,444:
   struct {
   struct {
     __in    u32 flags;        // bit0: fixed_offset, bit2: cacheable
     __in    u32 flags;        // bit0: fixed_offset, bit2: cacheable
     u32         reserved0;
     __inout u32 reserved0;
     __in    u32 mem_id;      // nvmap handle
     __in    u32 mem_id;      // nvmap handle
     u32         reserved1;
     __inout u32 reserved1;
     union {
     union {
       __out u64 offset;
       __out u64 offset;
Line 1,410: Line 1,464:
     __inout  u32 kind;          // -1 is default
     __inout  u32 kind;          // -1 is default
     __in      u32 mem_id;        // nvmap handle
     __in      u32 mem_id;        // nvmap handle
     u32           reserved;
     __inout  u32 reserved;
     __in      u64 buffer_offset;
     __in      u64 buffer_offset;
     __in      u64 mapping_size;
     __in      u64 mapping_size;
Line 1,422: Line 1,476:
Unmaps a memory region from the device address space.
Unmaps a memory region from the device address space.


struct {
  struct {
     __in u64 offset;
     __in u64 offset;
   };
   };
Line 1,448: Line 1,502:
    
    
   struct {
   struct {
     u64           buf_addr;    // (contained output user ptr on linux, ignored)
     __inout u64   buf_addr;    // (contained output user ptr on linux, ignored)
     __inout u32  buf_size;    // forced to 2*sizeof(struct va_region)
     __inout u32  buf_size;    // forced to 2*sizeof(struct va_region)
     u32           reserved;
     __inout u32   reserved;
     __out struct  va_region regions[2];
     __out struct  va_region regions[2];
   };
   };
Line 1,478: Line 1,532:
     __inout  u32 kind;          // -1 is default
     __inout  u32 kind;          // -1 is default
     __in      u32 mem_id;        // nvmap handle
     __in      u32 mem_id;        // nvmap handle
     u32           reserved0;
     __inout  u32 reserved0;
     __in      u64 buffer_offset;
     __in      u64 buffer_offset;
     __in      u64 mapping_size;
     __in      u64 mapping_size;
Line 1,487: Line 1,541:
     __in      u64 vma_addr;
     __in      u64 vma_addr;
     __in      u32 pages;
     __in      u32 pages;
     u32           reserved1;
     __inout  u32 reserved1;
  };
 
=== NVGPU_AS_IOCTL_GET_SYNC_RO_MAP ===
Returns the GPU virtual address to the read-only syncpoint-semaphore shim.
 
  struct {
    __out    u64 base_gpuva;
    __out    u32 sync_size;
    __out    u32 num_syncpoints;
  };
 
=== NVGPU_AS_IOCTL_MAPPING_MODIFY ===
Changes the kind of an existing mapped buffer region.
 
  struct {
    __in      s16 compr_kind;
    __in      s16 incompr_kind;
    __in      u64 buffer_offset;
    __in      u64 buffer_size;
    __in      u64 map_address;
   };
   };


Line 1,494: Line 1,568:


   struct remap_op {
   struct remap_op {
     __in u16 flags;                      // bit2: cacheable
     u16 flags;                      // bit2: cacheable
     __in u16 kind;           
     u16 kind;           
     __in u32 mem_handle;
     u32 mem_handle;
     __in u32 mem_offset_in_pages;
     u32 mem_offset_in_pages;
     __in u32 virt_offset_in_pages;      // (alloc_space_offset >> 0x10)
     u32 virt_offset_in_pages;      // (alloc_space_offset >> 0x10)
     __in u32 num_pages;                  // alloc_space_pages
     u32 num_pages;                  // alloc_space_pages
   };
   };
   
   
struct {
  struct {
     __in struct remap_op entries[];
     __in struct remap_op entries[];
  };
  };
 
=== NVGPU_AS_IOCTL_REMAP ===
Switch 2 variation of [[#NVGPU_AS_IOCTL_REMAP|NVGPU_AS_IOCTL_REMAP]].
 
  struct remap_op {
    u32 flags;
    s16 compr_kind; 
    s16 incompr_kind;       
    u32 mem_handle;
    u32 reserved;
    u64 mem_offset_in_pages;
    u64 virt_offset_in_pages;
    u64 num_pages;
  };
   
  struct {
    __in struct remap_op entries[];
  };


== /dev/nvhost-dbg-gpu ==
== /dev/nvhost-dbg-gpu ==
Line 1,536: Line 1,628:
| 0x8004440C || Out || 4 || NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT_SIZE
| 0x8004440C || Out || 4 || NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT_SIZE
|-
|-
| 0x0000440D || None || 0 || [[#NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT]]
| 0x0000440D || None || 0 || [[#NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT|NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT]]
|-
|-
| 0xC018440E || Inout || 24 || NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
| 0xC018440E || Inout || 24 || NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
Line 1,542: Line 1,634:
| 0xC018440F || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PDES
| 0xC018440F || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PDES
|-
|-
| 0xC0104410 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES]]
| 0xC0104410 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES|NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES]]
|-
|-
| 0xC0184411 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PTES
| 0xC0184411 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PTES
|-
|-
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES|NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
|-
|-
| 0xC0684413</br>[S2] 0xC0304413 || Inout || 104</br>48 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
| 0xC0684413</br>[S2] 0xC0304413 || Inout || 104</br>48 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
|-
|-
| 0xC0184414</br>[S2] 0xC0084414 || Inout || 24</br>8 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
| 0xC0184414</br>[S2] 0xC0084414 || Inout || 24</br>8 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS|NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
|-
|-
| 0xC0184415</br>[S2] 0xC0084415 || Inout || 24</br>8 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
| 0xC0184415</br>[S2] 0xC0084415 || Inout || 24</br>8 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS|NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
|-
|-
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
Line 1,578: Line 1,670:
| 0xC0184421 || Inout || 24 || [S2]  
| 0xC0184421 || Inout || 24 || [S2]  
|-
|-
| 0x40084422 || In || 8 || [S2]  
| 0x40084422 || In || 8 || [S2] NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE
|-
|-
| 0xC0084423 || Inout || 8 || [S2]  
| 0xC0084423 || Inout || 8 || [S2] NVGPU_DBG_GPU_IOCTL_HWPM_CTXSW_MODE
|-
|-
| 0x40084424 || In || 8 || [S2]  
| 0x40084424 || In || 8 || [S2] NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK
|-
|-
| 0xC0104425 || Inout || 16 || [S2]  
| 0xC0104425 || Inout || 16 || [S2] NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_CONTEXTS
|-
|-
| 0xC0184426 || Inout || 24 || [S2]  
| 0xC0184426 || Inout || 24 || [S2] NVGPU_DBG_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE
|-
|-
| 0x40084427 || In || 8 || [S2]  
| 0x40084427 || In || 8 || [S2] NVGPU_DBG_GPU_IOCTL_CLEAR_SINGLE_SM_ERROR_STATE
|-
|-
| 0x40044428 || In || 4 || [S2]  
| 0x40044428 || In || 4 || [S2] NVGPU_DBG_GPU_IOCTL_SET_SCHED_EXIT_WAIT_FOR_ERRBAR
|-
|-
| 0xC0184429 || Inout || 24 || [S2]  
| 0xC0184429 || Inout || 24 || [S2]  
Line 1,625: Line 1,717:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0x80044701 || Out || 4 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE]]
| 0x80044701 || Out || 4 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE|NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE]]
|-
|-
| 0x80284702 || Out || 40 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_INFO]]
| 0x80284702 || Out || 40 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_INFO|NVGPU_GPU_IOCTL_ZCULL_GET_INFO]]
|-
|-
| 0x402C4703 || In || 44 || [[#NVGPU_GPU_IOCTL_ZBC_SET_TABLE]]
| 0x402C4703 || In || 44 || [[#NVGPU_GPU_IOCTL_ZBC_SET_TABLE|NVGPU_GPU_IOCTL_ZBC_SET_TABLE]]
|-
|-
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE|NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
|-
|-
| 0xC0B04705</br>[S2] 0xC0E04705 || Inout || 176</br>[S2] 224|| [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
| 0xC0B04705</br>[S2] 0xC0E04705 || Inout || 176</br>[S2] 224|| [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS|NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
|-
|-
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS|NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
|-
|-
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2|NVGPU_GPU_IOCTL_FLUSH_L2]]
|-
|-
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE|NVGPU_GPU_IOCTL_INVAL_ICACHE]]
|-
|-
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE|NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
|-
|-
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE|NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
|-
|-
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710)</br>[S2] 0xC0084710 || Inout || 48</br>([1.0.0-6.1.0] 8)</br>[S2] 8 || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE|NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
|-
|-
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS|NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
|-
|-
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS|NVGPU_GPU_IOCTL_NUM_VSMS]]
|-
|-
| 0xC0044713</br>[S2] 0xC0084713 || Inout || 4</br>[S2] 8 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
| 0xC0044713</br>[S2] 0xC0084713 || Inout || 4</br>[S2] 8 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING|NVGPU_GPU_IOCTL_VSMS_MAPPING]]
|-
|-
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK|NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
|-
|-
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD|NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
|-
|-
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS|NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
|-
|-
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS|NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
|-
|-
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS|NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
|-
|-
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS|NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
|-
|-
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING|NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
|-
|-
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA|NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
|-
|-
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME|NVGPU_GPU_IOCTL_GET_GPU_TIME]]
|-
|-
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO|NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|-
|-
| 0xC010471E || Inout || 16 || [S2] NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS
| 0xC010471E || Inout || 16 || [S2] [[#NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS|NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS]]
|-
|-
| 0xC010471F || Inout || 16 || [S2]
| 0xC010471F || Inout || 16 || [S2]
Line 1,681: Line 1,773:
Returns the GPU's ZCULL context size. Identical to Linux driver.
Returns the GPU's ZCULL context size. Identical to Linux driver.


struct {
  struct {
     __out u32 size;
     __out u32 size;
   };
   };
Line 1,688: Line 1,780:
Returns GPU's ZCULL information. Identical to Linux driver.
Returns GPU's ZCULL information. Identical to Linux driver.


struct {
  struct {
     __out u32 width_align_pixels;
     __out u32 width_align_pixels;
     __out u32 height_align_pixels;
     __out u32 height_align_pixels;
Line 1,704: Line 1,796:
Sets the active ZBC table. Identical to Linux driver.
Sets the active ZBC table. Identical to Linux driver.


struct {
  struct {
     __in u32 color_ds[4];
     __in u32 color_ds[4];
     __in u32 color_l2[4];
     __in u32 color_l2[4];
Line 1,715: Line 1,807:
Queries the active ZBC table. Identical to Linux driver.
Queries the active ZBC table. Identical to Linux driver.


struct {
  struct {
     __out u32 color_ds[4];
     __out u32 color_ds[4];
     __out u32 color_l2[4];
     __out u32 color_l2[4];
Line 1,832: Line 1,924:
    
    
   struct in_buf {
   struct in_buf {
    __in   u64 gpu_characteristics_buf_size;  // must not be NULL, but gets overwritten with 0xD0=max_size
    __in u64 gpu_characteristics_buf_size;  // must not be NULL, but gets overwritten with 0xD0=max_size
    __in   u8 reserved[0xD8];
    __in u8 reserved[0xD8];
   };
   };
    
    
   struct out_buf {
   struct out_buf {
    __out   u8 reserved[0xE0];
    __out u8 reserved[0xE0];
   };
   };
    
    
   struct out_buf2 {
   struct out_buf2 {
    __out struct gpu_characteristics gc;
    __out struct gpu_characteristics gc;
   };
   };


Line 1,851: Line 1,943:
   struct {
   struct {
     __in u32 mask_buf_size;      // ignored, but must not be NULL
     __in u32 mask_buf_size;      // ignored, but must not be NULL
     __in u32 reserved[3];
     __inout u32 reserved[3];
     __out u64 mask_buf;          // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
     __out u64 mask_buf;          // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
   };
   };
Line 2,005: Line 2,097:
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.


struct time_correlation_sample {
  struct time_correlation_sample {
  u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register
    u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register
  u64 gpu_timestamp;                                  // from GPU's PTIMER registers
    u64 gpu_timestamp;                                  // from GPU's PTIMER registers
};
  };
   
   
struct {
  struct {
  __out struct time_correlation_sample samples[16];  // timestamp pairs
    __out struct time_correlation_sample samples[16];  // timestamp pairs
  __in u32    count;                                // number of pairs to read
    __in u32    count;                                // number of pairs to read
  __in u32    source_id;                            // cpu clock source id (must be 1)
    __in u32    source_id;                            // cpu clock source id (must be 1)
};
  };


== (Switch 2) /dev/nvhost-prof-dev-gpu ==                                                                                                           
=== NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS ===
Adjusts options of deterministic channels in channel batches.
 
Uses [[#Ioctl2|Ioctl2]].
 
  struct deterministic_opts {
    __inout u32 num_channels;
    __in u32 flags;
    __in u64 channels;                          // ignored
  };
 
  struct in_buf {
    __in struct deterministic_opts opts;
  };
 
  struct in_buf2 {
    __in u32 channels[];
  };
 
  struct out_buf {
    __out struct deterministic_opts opts;
  };
 
== (S2) /dev/nvhost-prof-dev-gpu ==                                                                                                           
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Value || Direction || Size || Description
! Value || Direction || Size || Description
Line 2,047: Line 2,162:
|}
|}


== (Switch 2) /dev/nvhost-tsg-gpu ==                                                                                     
== (S2) /dev/nvhost-tsg-gpu ==                                                                                     
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0xC0045401 || Inout || 4 || NVGPU_TSG_IOCTL_BIND_CHANNEL
| 0xC0045401 || Inout || 4 || [[#NVGPU_TSG_IOCTL_BIND_CHANNEL|NVGPU_TSG_IOCTL_BIND_CHANNEL]]
|-
|-
| 0xC0045402 || Inout || 4 || NVGPU_TSG_IOCTL_UNBIND_CHANNEL
| 0xC0045402 || Inout || 4 || [[#NVGPU_TSG_IOCTL_UNBIND_CHANNEL|NVGPU_TSG_IOCTL_UNBIND_CHANNEL]]
|-
|-
| 0x00005403 || None || 0 || NVGPU_TSG_IOCTL_ENABLE
| 0x00005403 || None || 0 || [[#NVGPU_TSG_IOCTL_ENABLE|NVGPU_TSG_IOCTL_ENABLE]]
|-
|-
| 0x00005404 || None || 0 || NVGPU_TSG_IOCTL_DISABLE
| 0x00005404 || None || 0 || [[#NVGPU_TSG_IOCTL_DISABLE|NVGPU_TSG_IOCTL_DISABLE]]
|-
|-
| 0x00005405 || None || 0 || NVGPU_TSG_IOCTL_PREEMPT
| 0x00005405 || None || 0 || [[#NVGPU_TSG_IOCTL_PREEMPT|NVGPU_TSG_IOCTL_PREEMPT]]
|-
|-
| 0xC0085407 || Inout || 8 || NVGPU_TSG_IOCTL_SET_RUNLIST_INTERLEAVE
| 0xC0085407 || Inout || 8 || [[#NVGPU_TSG_IOCTL_SET_RUNLIST_INTERLEAVE|NVGPU_TSG_IOCTL_SET_RUNLIST_INTERLEAVE]]
|-
|-
| 0xC0045408 || Inout || 4 || NVGPU_TSG_IOCTL_SET_TIMESLICE
| 0xC0045408 || Inout || 4 || [[#NVGPU_TSG_IOCTL_SET_TIMESLICE|NVGPU_TSG_IOCTL_SET_TIMESLICE]]
|-
|-
| 0xC0105409 || Inout || 16 || NVGPU_TSG_IOCTL_EVENT_ID_CTRL
| 0xC0105409 || Inout || 16 || [[#NVGPU_TSG_IOCTL_EVENT_ID_CTRL|NVGPU_TSG_IOCTL_EVENT_ID_CTRL]]
|-
|-
| 0x8004540A || Out || 4 || NVGPU_TSG_IOCTL_GET_TIMESLICE
| 0x8004540A || Out || 4 || [[#NVGPU_TSG_IOCTL_GET_TIMESLICE|NVGPU_TSG_IOCTL_GET_TIMESLICE]]
|-
|-
| 0xC018540B || Inout || 24 || NVGPU_TSG_IOCTL_BIND_CHANNEL_EX
| 0xC018540B || Inout || 24 || [[#NVGPU_TSG_IOCTL_BIND_CHANNEL_EX|NVGPU_TSG_IOCTL_BIND_CHANNEL_EX]]
|-
|-
| 0xC018540C || Inout || 24 || NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE
| 0xC018540C || Inout || 24 || [[#NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE|NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE]]
|-
|-
| 0xC008540D || Inout || 8 || NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION
| 0xC008540D || Inout || 8 || [[#NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION|NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION]]
|}
|}


= Channels =
=== NVGPU_TSG_IOCTL_BIND_CHANNEL ===
Channels are a concept for NVIDIA hardware blocks that share a common interface.
Binds a channel to the TSG.
 
  struct {
    __in s32 channel_fd;
  };
 
=== NVGPU_TSG_IOCTL_UNBIND_CHANNEL ===
Unbinds a channel from the TSG.


{| class="wikitable" border="1"
  struct {
! Path || Name
    __in s32 channel_fd;
|-
  };
| /dev/nvhost-gpu || GPU
 
|-
=== NVGPU_TSG_IOCTL_ENABLE ===
| /dev/nvhost-msenc || Video Encoder
Enables the TSG in runlist.
 
=== NVGPU_TSG_IOCTL_DISABLE ===
Disables the TSG in runlist.
 
=== NVGPU_TSG_IOCTL_PREEMPT ===
Preempts the TSG.
 
=== NVGPU_TSG_IOCTL_SET_RUNLIST_INTERLEAVE ===
Configures interleaving channels in a runlist.
 
  struct {
    __in u32 level;
    __in u32 reserved;
  };
 
=== NVGPU_TSG_IOCTL_SET_TIMESLICE ===
Sets how long a channel occupies an engine uninterrupted.
 
  struct {
    __in u32 timeslice_us;
  };
 
=== NVGPU_TSG_IOCTL_EVENT_ID_CTRL ===
Controls event notifications.
 
  struct {
    __in u32 cmd;
    __in u32 event_id;
    __out s32 event_fd;
    __in u32 padding;
  };
 
=== NVGPU_TSG_IOCTL_GET_TIMESLICE ===
Gets how long a channel occupies an engine uninterrupted.
 
  struct {
    __out u32 timeslice_us;
  };
 
=== NVGPU_TSG_IOCTL_BIND_CHANNEL_EX ===
Binds a channel to the TSG of the node receiving the command.
 
  struct {
    __in s32 channel_fd;
    __in u32 subcontext_id;
    __in u32 reserved[4];
  };
 
=== NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE ===
Reads the error state of a single SM.
 
Uses [[#Ioctl3|Ioctl3]].
 
  struct single_sm_error_state {
    __in u32 sm_id;
    __inout u32 reserved;
    __inout u64 record_mem;
    __in u64 record_size;
  };
 
  struct in_buf {
    __in struct single_sm_error_state state;
  };
 
  struct out_buf {
    __out struct single_sm_error_state state;
  };
 
  struct out_buf2 {
    __out u8 state[];
  };
 
=== NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION ===
Configures L2 sector promotion.
 
  struct {
    __in u32 promotion_flag;
    __in u32 reserved;
  };
 
= Channels =
Channels are a concept for NVIDIA hardware blocks that share a common interface.
 
{| class="wikitable" border="1"
! Path || Name
|-
| /dev/nvhost-gpu || GPU
|-
| /dev/nvhost-msenc || Video Encoder
|-
| /dev/nvhost-nvdec || Video Decoder
|-
| /dev/nvhost-nvjpg || JPEG Decoder
|-
| /dev/nvhost-vic || Video Image Compositor
|-
| /dev/nvhost-display || Display
|-
| /dev/nvhost-tsec || TSEC
|}
 
== Ioctls ==
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0xC0??0001 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT|NVHOST_IOCTL_CHANNEL_SUBMIT]]
|-
| 0xC0080002 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT|NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
|-
| 0xC0080003 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE|NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
|-
| 0xC0080004 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX|NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
|-
| 0x40040007 || In || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT|NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
|-
| 0x40080008 || In || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE|NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
|-
| 0xC0??0009 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
|-
| 0xC0??000A || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
|-
| 0x00000013 || None || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX|NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
|-
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE|NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
|-
| 0xC0??0024 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX|NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
|-
| 0xC0??0025 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX|NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
|-
| 0xC0??0026 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX|NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
|- style="border-top: double"
| 0x40044801 || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD|NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
|-
| 0x40044803 || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT|NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
|-
| 0x40084805 || In || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
|-
| 0x40184806 || In || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT|NVGPU_IOCTL_CHANNEL_WAIT]]
|-
| 0xC0044807 || Inout || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS|NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
|-
| 0xC0??4808 || Inout || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
|-
| 0xC0104809 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX|NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
|-
| 0x4008480A || In || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX|NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
|-
| 0xC010480B || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND|NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
|-
| 0xC018480C || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER|NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
|-
| 0x4004480D || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY|NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
|-
| 0x0000480E || None || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE|NVGPU_IOCTL_CHANNEL_ENABLE]]
|-
| 0x0000480F || None || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE|NVGPU_IOCTL_CHANNEL_DISABLE]]
|-
| 0x00004810 || None || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT|NVGPU_IOCTL_CHANNEL_PREEMPT]]
|-
| 0x00004811 || None ||  0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET|NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
|-
| 0x40084812</br>[S2] 0x40104812 || In || 8</br>[S2] 16 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL|NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
|-
| 0xC0104813 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT|NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
|-
| 0x40084714 || In || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA|NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
| 0x80084715 || Out || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA|NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|-
|-
| /dev/nvhost-nvdec || Video Decoder
| 0x80804816 || Out || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO|NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
|-
|-
| /dev/nvhost-nvjpg || JPEG Decoder
| 0xC0104817 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION|NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
|-
|-
| /dev/nvhost-vic || Video Image Compositor
| 0x40204818 || In || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
|-
|-
| /dev/nvhost-display || Display
| 0xC0??4819 || Inout || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
|-
|-
| /dev/nvhost-tsec || TSEC
| 0xC020481A || Inout || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
|}
 
== Ioctls ==
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
|-
| 0xC0??0001 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
| 0xC018481B || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
|-
|-
| 0xC0080002 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
| 0xC018481C || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
|-
|-
| 0xC0080003 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
| 0xC004481D || Inout || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE|NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
|-
|-
| 0xC0080004 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
| 0xC010481E || Inout || 16 || [S2]  
|-
|-
| 0x40040007 || In || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
| 0xC008481F || Inout || 8 || [S2] [[#NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE|NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE]]
|-
|-
| 0x40080008 || In || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
| 0x40044820 || In || 4 || [S2]  
|-
|-
| 0xC0??0009 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
| 0xC0504821 || Inout || 80 || [S2] [[#NVGPU_IOCTL_CHANNEL_SETUP_BIND|NVGPU_IOCTL_CHANNEL_SETUP_BIND]]
|-
|}
| 0xC0??000A || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
 
|-
=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
| 0x00000013 || None || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
Submits data to the channel.
|-
 
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
   struct cmdbuf {
|-
     u32 mem;
| 0xC0??0024 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
     u32 offset;
|-
     u32 words;
| 0xC0??0025 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
   };
|-
    
| 0xC0??0026 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
|- style="border-top: double"
| 0x40044801 || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
|-
| 0x40044803 || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
|-
| 0x40084805 || In || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
|-
| 0x40184806 || In || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
|-
| 0xC0044807 || Inout || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
|-
| 0xC0??4808 || Inout || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
|-
| 0xC0104809 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
|-
| 0x4008480A || In || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
|-
| 0xC010480B || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
|-
| 0xC018480C || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
|-
| 0x4004480D || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
|-
| 0x0000480E || None || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
|-
| 0x0000480F || None || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
|-
| 0x00004810 || None || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
|-
| 0x00004811 || None ||  0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
|-
| 0x40084812</br>[S2] 0x40104812 || In || 8</br>[S2] 16 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
|-
| 0xC0104813 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
|-
| 0x40084714 || In || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
| 0x80084715 || Out || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|-
| 0x80804816 || Out || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
|-
| 0xC0104817 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
|-
| 0x40204818 || In || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
|-
| 0xC0??4819 || Inout || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
|-
| 0xC020481A || Inout || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
|-
| 0xC018481B || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
|-
| 0xC018481C || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
|-
| 0xC004481D || Inout || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
|-
| 0xC010481E || Inout || 16 || [S2]  
|-
| 0xC008481F || Inout || 8 || [S2] NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE
|-
| 0x40044820 || In || 4 || [S2]
|-
| 0xC0504821 || Inout || 80 || [S2] NVGPU_IOCTL_CHANNEL_SETUP_BIND
|}
 
=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
Submits data to the channel.
 
   struct cmdbuf {
     u32 mem;
     u32 offset;
     u32 words;
   };
    
   struct reloc {
   struct reloc {
     u32 cmdbuf_mem;
     u32 cmdbuf_mem;
Line 2,269: Line 2,480:
     u32 phys_addr_out;                // returned device physical address mapped to the handle
     u32 phys_addr_out;                // returned device physical address mapped to the handle
   };
   };
 
   struct {
   struct {
     __in    u32 num_handles;          // number of nvmap handles to map
     __in    u32 num_handles;          // number of nvmap handles to map
Line 2,285: Line 2,496:
     u32 reserved;                    // ignored
     u32 reserved;                    // ignored
   };
   };
 
   struct {
   struct {
     __in    u32 num_handles;          // number of nvmap handles to unmap
     __in    u32 num_handles;          // number of nvmap handles to unmap
Line 2,405: Line 2,616:
Binds a ZCULL context to the channel. Identical to Linux driver.
Binds a ZCULL context to the channel. Identical to Linux driver.


struct {
  struct {
     __in u64 gpu_va;
     __in u64 gpu_va;
     __in u32 mode;        // 0=global, 1=no_ctxsw, 2=separate_buffer, 3=part_of_regular_buf
     __in u32 mode;        // 0=global, 1=no_ctxsw, 2=separate_buffer, 3=part_of_regular_buf
Line 2,477: Line 2,688:
   };  
   };  


GR Error Interrupt Bits:
{| class="wikitable"
{| class="wikitable"
|+ GR Error Interrupt Bits
! Bits
|-
! Bit(s)
! Description
! Description
|-
|-
Line 2,490: Line 2,700:
|-
|-
| 2
| 2
| unknown
|  
|-
|-
| 3
| 3
| unknown
|  
|-
|-
| 4
| 4
Line 2,505: Line 2,715:
|-
|-
| 7
| 7
| unknown
|  
|-
|-
| 8
| 8
Line 2,511: Line 2,721:
|-
|-
| 9–18
| 9–18
| unknown
|  
|-
|-
| 19
| 19
Line 2,523: Line 2,733:
|-
|-
| 22–31
| 22–31
| unknown
|  
|}
|}


Line 2,539: Line 2,749:
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.


struct fence {
  struct fence {
     u32 id;
     u32 id;
     u32 value;
     u32 value;
};
  };
   
   
struct {
  struct {
  __in    u32 num_entries;
    __in    u32 num_entries;
  __in    u32 num_jobs;
    __in    u32 num_jobs;
  __in    u32 flags;                      // bit0: vpr_enabled
    __in    u32 flags;                      // bit0: vpr_enabled
  __out  struct fence fence_out;          // returned new fence object for others to wait on
    __out  struct fence fence_out;          // returned new fence object for others to wait on
  __in    u32 reserved[3];                // ignored
    __in    u32 reserved[3];                // ignored
};
  };


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY ===
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY ===
Line 2,583: Line 2,793:
   struct {
   struct {
     __out u64 data;
     __out u64 data;
  };
=== NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE ===
Sets the channel preemption modes.
  struct {
    __in u32 graphics_preempt_mode;
    __in u32 compute_preempt_mode;
  };
=== NVGPU_IOCTL_CHANNEL_SETUP_BIND ===
Allocates or assigns the control buffers for the channel.
  struct {
    __in u32 num_gpfifo_entries;
    __in u32 num_inflight_jobs;
    __in u32 flags;
    __in s32 userd_dmabuf_fd;
    __in s32 gpfifo_dmabuf_fd;
    __out u32 work_submit_token;
    __in u64 userd_dmabuf_offset;
    __in u64 gpfifo_dmabuf_offset;
    __out u64 gpfifo_gpu_va;
    __out u64 userd_gpu_va;
    __out u64 usermode_mmio_gpu_va;
    __out u32 hw_channel_id;
    __in u32 reserved[3];
   };
   };


Retrieved from "https://switchbrew.org/wiki/NV_services"