NV services: Difference between revisions

| 0 || [[#Open]]

| 1 || [[#Ioctl]]

| 2 || [[#Close]]

| 3 || [[#Initialize]]

| 4 || [[#QueryEvent]]

| 5 || [[#MapSharedMem]]

| 6 || [[#GetStatus]]

| 7 || [[#SetAruidWithoutCheck]]

| 8 || [[#SetAruid]]

| 9 || [[#DumpStatus]]

| 10 || [3.0.0+] [[#InitializeDevtools]]

| 11 || [3.0.0+] [[#Ioctl2]]

| 12 || [3.0.0+] [[#Ioctl3]]

| 13 || [3.0.0+] [[#SetGraphicsFirmwareMemoryMarginEnabled]]

QueryEvent is only supported on (and implemented differently on):

* /dev/nvhost-gpu

** EvtId=1: SmException_BptIntReport

** EvtId=2: SmException_BptPauseReport

* /dev/nvhost-ctrl: Used to get events for syncpts.

** EvtId=(event_slot | ((syncpt_id & 0xFFF) << 16) | (is_valid << 28)): New format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]/[[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]].

** EvtId=(event_slot | (syncpt_id << 4)): Old format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]].

* /dev/nvhost-ctrl-gpu

** EvtId=1: Returns error_event_handle.

** EvtId=2: Returns unknown event.

* /dev/nvhost-dbg-gpu

** Ignores EvtId.

| 0 || [[#DebugFSOpen]]

| 1 || [[#DebugFSClose]]

| 2 || [[#GetDebugFSKeys]]

| 3 || [[#GetDebugFSValue]]

| 4 || [[#SetDebugFSValue]]

| 0xC0080014 || Inout || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_READ]]

| 0x40040015 || In || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_INCR]]

| 0xC00C0016 || Inout || 12 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT]]

| 0x40080017 || In || 8 || [[#NVHOST_IOCTL_CTRL_MODULE_MUTEX]]

| 0xC0180018 || Inout || 24 || [[#NVHOST_IOCTL_CTRL_MODULE_REGRDWR]]

| 0xC0100019 || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]]

| 0xC008001A || Inout || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_READ_MAX]]

| 0xC183001B || Inout || 387 || [[#NVHOST_IOCTL_CTRL_GET_CONFIG]]

| 0xC004001C || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT]]

| 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]

| 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]]

| 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT]]

| 0xC0040020 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT]]

| 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH]]

| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]

|}

| 0xC0080101 || Inout || 8 || [[#NVMAP_IOC_CREATE]]

| 0x00000102 || - || 0 || [[#NVMAP_IOC_CLAIM]]

| 0xC0080103 || Inout || 8 || [[#NVMAP_IOC_FROM_ID]]

| 0xC0200104 || Inout || 32 || [[#NVMAP_IOC_ALLOC]]

| 0xC0180105 || Inout || 24 || [[#NVMAP_IOC_FREE]]

| 0xC0280106 || Inout || 40 || [[#NVMAP_IOC_MMAP]]

| 0xC0280107 || Inout || 40 || [[#NVMAP_IOC_WRITE]]

| 0xC0280108 || Inout || 40 || [[#NVMAP_IOC_READ]]

| 0xC00C0109 || Inout || 12 || [[#NVMAP_IOC_PARAM]]

| 0xC010010A || Inout || 16 || [[#NVMAP_IOC_PIN_MULT]]

| 0xC010010B || Inout || 16 || [[#NVMAP_IOC_UNPIN_MULT]]

| 0xC008010C || Inout || 8 || [[#NVMAP_IOC_CACHE]]

| 0xC004010D || Inout || 4 || [[#NVMAP_IOC_GET_IVC_ID]]

| 0xC008010E || Inout || 8 || [[#NVMAP_IOC_GET_ID]]

| 0xC004010F || Inout || 4 || [[#NVMAP_IOC_FROM_IVC_ID]]

| 0x40040110 || In || 4 || [[#NVMAP_IOC_SET_ALLOCATION_TAG_LABEL]]

| 0x00000111 || - || 0 || [[#NVMAP_IOC_RESERVE]]

| 0x40100112 || In || 16 || [[#NVMAP_IOC_EXPORT_FOR_ARUID]]

| 0x40100113 || In || 16 || [[#NVMAP_IOC_IS_OWNED_BY_ARUID]]

| 0x40100114 || In || 16 || [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]]

     u8       pad[7];

     u32       pad;

     u8       pad[4];

     u8       pad[4];

     u8       pad[4];

| 0x80040212 || Out || 4 || [[#NVDISP_CTRL_NUM_OUTPUTS]]

| ([1.0.0-3.0.0] 0xC0040217) || ([1.0.0-3.0.0] Inout) || ([1.0.0-3.0.0] 4) || ([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_OUT_EVENT)

| 0x80010224 || Out || 1 || [11.0.0+] NVDISP_CTRL_IS_DISPLAY_OLED

| 0x80380204 || Out || 56 || [[#NVDISP_GET_MODE]]

| 0x40380205 || In || 56 || [[#NVDISP_SET_MODE]]

| 0xC038020A || Inout || 56 || [[#NVDISP_VALIDATE_MODE]]

| 0x80600210 || Out || 96 || [[#NVDISP_GET_AVI_INFOFRAME]]

| 0x40600211 || In || 96 || [[#NVDISP_SET_AVI_INFOFRAME]]

| 0xEBFC0215 || Inout || 11260 || [[#NVDISP_GET_MODE_DB]]

| 0xC003021A || Inout || 3 || [[#NVDISP_PANEL_GET_VENDOR_ID]]

| 0x803C021B || Out || 60 || [[#NVDISP_GET_MODE2]]

| 0x403C021C || In || 60 || [[#NVDISP_SET_MODE2]]

| 0xC03C021D || Inout || 60 || [[#NVDISP_VALIDATE_MODE2]]

| 0xEF20021E || Inout || 12064 || [[#NVDISP_GET_MODE_DB2]]

| 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE]]

| 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MAX]]

| 0x40040223 || In || 4 || [11.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MIN]]

| 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG]]

| 0xC01C0226 || Inout || 28 || [11.0.0+] [[#NVDISP_GET_PANEL_DATA]]

| 0x40010502 || In || 1 || [[#NVDCUTIL_VIRTUAL_EDID_ENABLE]]

| 0x42040503 || In || 516 || [[#NVDCUTIL_VIRTUAL_EDID_SET_DATA]]

| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE]]

| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE]]

| 0x40180603 || In || 24 || [[#NVSCHED_CTRL_ADD_APPLICATION]]

| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION]]

| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION]]

| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID]]

| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST]]

| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST]]

| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST]]

| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST]]

| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST]]

| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]]

| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]

| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]

| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]

| 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA]]

| 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]]

| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL]]

| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE]]

| 0xC0104103 || Inout || 16 || [[#NVGPU_AS_IOCTL_FREE_SPACE]]

| 0xC0184104 || Inout || 24 || [[#NVGPU_AS_IOCTL_MAP_BUFFER]]

| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]

| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]

| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]

| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS]]

| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]

| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]

| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]

     u32     padding;

     u32         reserved0;

     u32         reserved1;

     u32           reserved;

struct {

     u64           buf_addr;    // (contained output user ptr on linux, ignored)

     u32           reserved;

     u32           reserved0;

     u32           reserved1;

     __in u16 flags;                      // bit2: cacheable

     __in u16 kind;           

     __in u32 mem_handle;

     __in u32 mem_offset_in_pages;

     __in u32 virt_offset_in_pages;      // (alloc_space_offset >> 0x10)

     __in u32 num_pages;                  // alloc_space_pages

struct {

  };

| 0x0000440D || None || 0 || [[#NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT]]

| 0xC0104410 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES]]

| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]

| 0xC0684413 || Inout || 104 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO

| 0xC0184414 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]

| 0xC0184415 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]

|}

 

=== NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT ===

Uses [[#Ioctl3|Ioctl3]].

 

| 0x80044701 || Out || 4 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE]]

| 0x80284702 || Out || 40 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_INFO]]

| 0x402C4703 || In || 44 || [[#NVGPU_GPU_IOCTL_ZBC_SET_TABLE]]

| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]

| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]

| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]

| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]

| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]

| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]

| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]

| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]

| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]

| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]

| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]

| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]

| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]

| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]

| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]

| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]

| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]

| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]

| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]

| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]

| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]

struct {

struct {

struct {

struct {

     u32 arch;                       // 0x120 (NVGPU_GPU_ARCH_GM200)

     u32 impl;                       // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)

     u32 rev;                       // 0xA1 (Revision A1)

     u32 num_gpc;                   // 0x1

     u64 l2_cache_size;             // 0x40000

     u64 on_board_video_memory_size; // 0x0 (not used)

     u32 num_tpc_per_gpc;           // 0x2

     u32 bus_type;                   // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)

     u32 big_page_size;             // 0x20000

     u32 compression_page_size;     // 0x20000

     u32 pde_coverage_bit_count;     // 0x1B

     u32 available_big_page_sizes;   // 0x30000

     u32 gpc_mask;                   // 0x1

     u32 sm_arch_sm_version;         // 0x503 (Maxwell Generation 5.0.3)

     u32 sm_arch_spa_version;       // 0x503 (Maxwell Generation 5.0.3)

     u32 sm_arch_warp_count;         // 0x80

     u32 gpu_va_bit_count;           // 0x28

     u32 reserved;                   // NULL

     u64 flags;                     // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)

     u32 twod_class;                 // 0x902D (FERMI_TWOD_A)

     u32 threed_class;               // 0xB197 (MAXWELL_B)

     u32 compute_class;             // 0xB1C0 (MAXWELL_COMPUTE_B)

     u32 gpfifo_class;               // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)

     u32 inline_to_memory_class;     // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)

     u32 dma_copy_class;             // 0xB0B5 (MAXWELL_DMA_COPY_A)

     u32 max_fbps_count;             // 0x1

     u32 fbp_en_mask;               // 0x0 (disabled)

     u32 max_ltc_per_fbp;           // 0x2

     u32 max_lts_per_ltc;           // 0x1

     u32 max_tex_per_tpc;           // 0x0 (not supported)

     u32 max_gpc_count;             // 0x1

     u32 rop_l2_en_mask_0;           // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)

     u32 rop_l2_en_mask_1;           // 0x0

     u64 chipname;                   // 0x6230326D67 ("gm20b")

     u64 gr_compbit_store_base_hw;   // 0x0 (not supported)

     __in u32 reserved[3];

struct time_correlation_sample {

  u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register

  u64 gpu_timestamp;                                  // from GPU's PTIMER registers

};

struct {

  __out struct time_correlation_sample samples[16];  // timestamp pairs

  __in u32    count;                                // number of pairs to read

  __in u32    source_id;                            // cpu clock source id (must be 1)

};

! Path || Name

| /dev/nvhost-gpu || GPU

| /dev/nvhost-msenc || Video Encoder

| /dev/nvhost-nvdec || Video Decoder

| /dev/nvhost-nvjpg || JPEG Decoder

| /dev/nvhost-vic || Video Image Compositor

| /dev/nvhost-display || Display

| /dev/nvhost-tsec || TSEC

|}

 

{| class="wikitable" border="1"

! Value || Size || Description

| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]

| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]

| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]

| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]

| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]

| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]

|-

| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]

|-

| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]

|-

| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]

|-

| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]

|-

| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]

|-

| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]

|-

| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]

|- style="border-top: double"

| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]

|-

| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]

|-

| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]

|-

| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]

|-

| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]

|-

| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]

|-

| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]

|-

| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]

|-

| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]

|-

| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]

|-

| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]

|-

| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]

|-

| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]

|-

| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]

|-

| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]

|-

| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]

|-

| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]

|-

| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]

|-

| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]

|-

| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]

|-

| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]

|-

| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]

|-

| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]

|-

| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]

|-

| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]

|- style="border-top: double"

| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]

|-

| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]

|}