NV services: Difference between revisions

QueryEvent is only supported on (and implemented differently on):

* /dev/nvhost-gpu

** EvtId=1: SmException_BptIntReport

** EvtId=2: SmException_BptPauseReport

* /dev/nvhost-ctrl: Used to get events for syncpts.

** EvtId=(event_slot | ((syncpt_id & 0xFFF) << 16) | (is_valid << 28)): New format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]/[[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]].

** EvtId=(event_slot | (syncpt_id << 4)): Old format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]].

* /dev/nvhost-ctrl-gpu

** EvtId=1: Returns error_event_handle.

** EvtId=2: Returns unknown event.

* /dev/nvhost-dbg-gpu

** Ignores EvtId.

| 0x80040212 || Out || 4 || NVDISP_CTRL_NUM_OUTPUTS

| 0xC1100214 || Inout || 272 || NVDISP_CTRL_QUERY_EDID

| ([1.0.0-3.0.0] 0xC0040217) || ([1.0.0-3.0.0] Inout) || ([1.0.0-3.0.0] 4) || ([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_OUT_EVENT)

| 0x80010224 || Out || 1 || [11.0.0+] NVDISP_CTRL_IS_DISPLAY_OLED

| 0x80600210 || Out || 96 || NVDISP_GET_AVI_INFOFRAME

| 0x40600211 || In || 96 || NVDISP_SET_AVI_INFOFRAME

| 0xEBFC0215 || Inout || 11260 || NVDISP_GET_MODE_DB

| 0x803C021B || Out || 60 || NVDISP_GET_MODE2

| 0x403C021C || In || 60 || NVDISP_SET_MODE2

| 0xC03C021D || Inout || 60 || NVDISP_VALIDATE_MODE2

| 0xEF20021E || Inout || 12064 || NVDISP_GET_MODE_DB2

=== NVDISP_PANEL_GET_VENDOR_ID ===

 

Returns display panel's informations.

     __out u8 vendor; //0x10 - JDI, 0x20 - InnoLux, 0x30 - AUO, 0x40 - Sharp, 0x50 - Samsung

     __out u8 model;

     __out u8 board; //0xF - 6.2", 0x10 - 5.5", 0x20 - 7.0". JDI panels have nonstandard values

=== NVDISP_GET_BACKLIGHT_RANGE ===

Returns the minimum and maximum values for the intensity of the display's backlight.

 

     __out u32 min;

     __out u32 max;

=== NVDISP_SET_BACKLIGHT_RANGE_MAX ===

Sets the maximum value for the intensity of the display's backlight.

     __in u32 max;

=== NVDISP_SET_BACKLIGHT_RANGE_MIN ===

Sets the minimum value for the intensity of the display's backlight.

     __in u32 min;

=== NVDISP_SEND_PANEL_MSG ===

     __in u32 cmd;         // DPAUX AUXCTL command (1=unk, 2=I2CWR, 4=MOTWR, 7=AUXWR)

     __in u32 addr;         // DPAUX AUXADDR

     __in u32 size;         // message size

     __in u32 msg[4];       // raw AUXDATA message

=== NVDISP_GET_PANEL_DATA ===

     __in u32 cmd;         // DPAUX AUXCTL command (3=I2CRD, 5=MOTRD, 6=AUXRD)

     __in u32 addr;         // DPAUX AUXADDR

     __in u32 size;         // message size

     __out u32 msg[4];     // raw AUXDATA message

  };

 

|}

{| class="wikitable" border="1"

| 0xC020050A || Inout || 32 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_SETTINGS

|}

== /dev/nvsched-ctrl ==

This is a customized scheduler device.

The way this device is exposed and configured is exclusive to the Switch, since other sources don't have an actual interface for the scheduler.

{| class="wikitable" border="1"

| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE]]

| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE]]

|-

| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION]]

| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION]]

| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID]]

| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST]]

| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST]]

| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST]]

| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST]]

| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST]]

| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]]

| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]

| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]

| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]

| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT

| 0x40100611 || In || 16 || NVSCHED_CTRL_SET_RUNLIST_MAX_DEBT

| 0x40010612 || In || 1 || NVSCHED_CTRL_OVERRUN_EVENTS_ENABLE

=== NVSCHED_CTRL_ENABLE ===

 

 

   struct {

     __in u64 application_id;

    __in u64 timeslice;

=== NVSCHED_CTRL_UPDATE_APPLICATION ===

     __in u64 application_id;

     __in u64 priority;

    __in u64 timeslice;

=== NVSCHED_CTRL_REMOVE_APPLICATION ===

Removes the application from the scheduler.

=== NVSCHED_CTRL_GET_ID ===

 

 

=== NVSCHED_CTRL_ADD_RUNLIST ===

 

 

Updates the runlist parameters in the scheduler.

 

  };

=== NVSCHED_CTRL_LINK_RUNLIST ===

Links a runlist to a given application in the scheduler.

=== NVSCHED_CTRL_UNLINK_RUNLIST ===

Unlinks a runlist from a given application in the scheduler.

=== NVSCHED_CTRL_REMOVE_RUNLIST ===

Removes the runlist from the scheduler.

     __in u64 runlist_id;

=== NVSCHED_CTRL_HAS_OVERRUN_EVENT ===

Returns a boolean to tell if the scheduler has an overrun event or not.

     __out u8 has_overrun;

=== NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT ===

Returns the overrun event's data from the scheduler.

=== NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE ===

     __in u32 fence_id;

     __in u32 fence_value;

     __in u32 swap_interval;

=== NVSCHED_CTRL_DETACH_APPLICATION ===

Places the given application in detached state.

== /dev/nverpt-ctrl ==

Added in firmware version 3.0.0.

{| class="wikitable" border="1"

|}

=== NVERPT_TELEMETRY_SUBMIT_DATA ===

Sends test data for creating a new [[Error_Report_services|Error Report]].

     __in u64 TestU64;

    __in u32 TestU32Array_size;

     __in u8 padding1[5];

=== NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA ===

Sends display data for creating a new [[Error_Report_services|Error Report]].

     __in u32 CodecType;

     __in u32 DecodeBuffers;

     __in u32 FrameWidth;

    __in u8  TransferCharacteristics;

     __in u8  MatrixCoefficients;

    __in u8  ErrorString[64];      // must be "Error detected = 0x1000000"

== /dev/nvhost-as-gpu ==

Each fd opened to this device creates an address space. An address space is then later bound with a channel.

Once a nvgpu channel has been bound to an address space it cannot be unbound. There is no support for allowing an nvgpu channel to change from one address space to another (or from one to none).

{| class="wikitable" border="1"

| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL]]

| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE]]

| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]

|}

 

=== NVGPU_AS_IOCTL_BIND_CHANNEL ===

Identical to Linux driver.

 

     __in u32 channel_fd;

   };

 

=== NVGPU_AS_IOCTL_ALLOC_SPACE ===

Reserves pages in the device address space.

     __in u32 pages;

     __in u32 page_size;

     __in u32 flags;

     u32     padding;

     union {

       __out u64 offset;

      __in  u64 align;

     };

=== NVGPU_AS_IOCTL_FREE_SPACE ===

Frees pages from the device address space.

  struct {

 

=== NVGPU_AS_IOCTL_MAP_BUFFER ===

 

Unaligned size will cause a [[#Panic]].

 

On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.

 

  };

=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===

Maps a memory region in the device address space with extra params.

On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.

     __in     u32 flags;         // bit0: fixed_offset, bit2: cacheable

     __inout  u32 kind;           // -1 is default

     __in     u32 mem_id;         // nvmap handle

     u32           reserved;

    __in     u64 mapping_size;

       __out   u64 offset;

       __in   u64 align;

=== NVGPU_AS_IOCTL_UNMAP_BUFFER ===

Unmaps a memory region from the device address space.

struct {

=== NVGPU_AS_IOCTL_ALLOC_AS ===

Nintendo's custom implementation for allocating an address space.

     __in u32 big_page_size;   // depends on GPU's available_big_page_sizes; 0=default

     __in s32 as_fd;           // ignored; passes 0

     __in u64 reserved;       // ignored; passes 0

=== NVGPU_AS_IOCTL_GET_VA_REGIONS ===

Nintendo's custom implementation to get rid of pointer in struct.

Uses [[#Ioctl3|Ioctl3]].

     u64          buf_addr;   // (contained output user ptr on linux, ignored)

     __inout u32   buf_size;   // forced to 2*sizeof(struct va_region)

     __out struct va_region regions[2];

=== NVGPU_AS_IOCTL_ALLOC_AS_EX ===

Nintendo's custom implementation for allocating an address space with extra params.

| 0xC0684413 || Inout || 104 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO

| 0xC0184414 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]

| 0xC0184415 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]

| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]

| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]

     u32 arch;                       // 0x120 (NVGPU_GPU_ARCH_GM200)

     u32 impl;                       // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)

     u32 rev;                       // 0xA1 (Revision A1)

     u32 num_gpc;                   // 0x1

     u64 l2_cache_size;             // 0x40000

     u64 on_board_video_memory_size; // 0x0 (not used)

     u32 num_tpc_per_gpc;           // 0x2

     u32 bus_type;                   // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)

     u32 big_page_size;             // 0x20000

     u32 compression_page_size;     // 0x20000

     u32 pde_coverage_bit_count;     // 0x1B

     u32 available_big_page_sizes;   // 0x30000

     u32 gpc_mask;                   // 0x1

     u32 sm_arch_sm_version;         // 0x503 (Maxwell Generation 5.0.3)

     u32 sm_arch_spa_version;       // 0x503 (Maxwell Generation 5.0.3)

     u32 sm_arch_warp_count;         // 0x80

     u32 gpu_va_bit_count;           // 0x28

     u32 reserved;                   // NULL

     u64 flags;                     // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)

     u32 twod_class;                 // 0x902D (FERMI_TWOD_A)

     u32 threed_class;               // 0xB197 (MAXWELL_B)

     u32 compute_class;             // 0xB1C0 (MAXWELL_COMPUTE_B)

     u32 gpfifo_class;               // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)

     u32 inline_to_memory_class;     // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)

     u32 dma_copy_class;             // 0xB0B5 (MAXWELL_DMA_COPY_A)

     u32 max_fbps_count;             // 0x1

     u32 fbp_en_mask;               // 0x0 (disabled)

     u32 max_ltc_per_fbp;           // 0x2

     u32 max_lts_per_ltc;           // 0x1

     u32 max_tex_per_tpc;           // 0x0 (not supported)

     u32 max_gpc_count;             // 0x1

     u32 rop_l2_en_mask_0;           // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)

     u32 rop_l2_en_mask_1;           // 0x0

     u64 chipname;                   // 0x6230326D67 ("gm20b")

     u64 gr_compbit_store_base_hw;   // 0x0 (not supported)

= Channels =

Channels are a concept for NVIDIA hardware blocks that share a common interface.