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! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0x80040212 || Out || 4 || NVDISP_CTRL_NUM_OUTPUTS
| 0x80040212 || Out || 4 || [[#NVDISP_CTRL_NUM_OUTPUTS]]
|-
|-
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES
|-
|-
| 0xC1100214 || Inout || 272 || NVDISP_CTRL_QUERY_EDID
| 0xC2100214</br>([1.0.0-11.0.1] 0xC1100214) || Inout || 528</br>([1.0.0-11.0.1] 272) || NVDISP_CTRL_QUERY_EDID
|-
|-
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
Line 611: Line 611:
| 0x80010224 || Out || 1 || [11.0.0+] NVDISP_CTRL_IS_DISPLAY_OLED
| 0x80010224 || Out || 1 || [11.0.0+] NVDISP_CTRL_IS_DISPLAY_OLED
|}
|}
=== NVDISP_CTRL_NUM_OUTPUTS ===
  struct {
    __out u32 num_outputs;
  };


== /dev/nvdisp-disp0, /dev/nvdisp-disp1 ==
== /dev/nvdisp-disp0, /dev/nvdisp-disp1 ==
Line 622: Line 628:
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
|-
|-
| 0x80380204 || Out || 56 || NVDISP_GET_MODE
| 0x80380204 || Out || 56 || [[#NVDISP_GET_MODE]]
|-
|-
| 0x40380205 || Out || 56 || NVDISP_SET_MODE
| 0x40380205 || In || 56 || [[#NVDISP_SET_MODE]]
|-
|-
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
Line 634: Line 640:
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
|-
|-
| 0xC038020A || Inout || 56 || NVDISP_VALIDATE_MODE
| 0xC038020A || Inout || 56 || [[#NVDISP_VALIDATE_MODE]]
|-
|-
| 0x4018020B || In || 24 || NVDISP_SET_CSC
| 0x4018020B || In || 24 || NVDISP_SET_CSC
Line 646: Line 652:
| 0xC004020F || Inout || 4 || NVDISP_DPMS
| 0xC004020F || Inout || 4 || NVDISP_DPMS
|-
|-
| 0x80600210 || Out || 96 || NVDISP_GET_AVI_INFOFRAME
| 0x80600210 || Out || 96 || [[#NVDISP_GET_AVI_INFOFRAME]]
|-
|-
| 0x40600211 || In || 96 || NVDISP_SET_AVI_INFOFRAME
| 0x40600211 || In || 96 || [[#NVDISP_SET_AVI_INFOFRAME]]
|-
|-
| 0xEBFC0215 || Inout || 11260 || NVDISP_GET_MODE_DB
| 0xEBFC0215 || Inout || 11260 || [[#NVDISP_GET_MODE_DB]]
|-
|-
| 0xC003021A || Inout || 3 || NVDISP_PANEL_GET_VENDOR_ID
| 0xC003021A || Inout || 3 || [[#NVDISP_PANEL_GET_VENDOR_ID]]
|-
|-
| 0x803C021B || Out || 60 || NVDISP_GET_MODE2
| 0x803C021B || Out || 60 || [[#NVDISP_GET_MODE2]]
|-
|-
| 0x403C021C || In || 60 || NVDISP_SET_MODE2
| 0x403C021C || In || 60 || [[#NVDISP_SET_MODE2]]
|-
|-
| 0xC03C021D || Inout || 60 || NVDISP_VALIDATE_MODE2
| 0xC03C021D || Inout || 60 || [[#NVDISP_VALIDATE_MODE2]]
|-
|-
| 0xEF20021E || Inout || 12064 || NVDISP_GET_MODE_DB2
| 0xEF20021E || Inout || 12064 || [[#NVDISP_GET_MODE_DB2]]
|-
|-
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
Line 675: Line 681:
|}
|}


=== NVDISP_GET_BACKLIGHT_RANGE ===
=== NVDISP_GET_MODE ===
Returns the minimum and maximum values for the intensity of the display's backlight.
Almost identical to Linux driver.


   struct {
   struct {
     __out u32 min;
     __out u32 hActive;
     __out u32 max;
     __out u32 vActive;
    __out u32 hSyncWidth;
    __out u32 vSyncWidth;
    __out u32 hFrontPorch;
    __out u32 vFrontPorch;
    __out u32 hBackPorch;
    __out u32 vBackPorch;
    __out u32 hRefToSync;
    __out u32 vRefToSync;
    __out u32 pclkKHz;
    __out u32 bitsPerPixel;      // Always 0
    __out u32 vmode;            // Always 0
    __out u32 sync;
   };
   };


=== NVDISP_SET_BACKLIGHT_RANGE_MAX ===
=== NVDISP_SET_MODE ===
Sets the maximum value for the intensity of the display's backlight.
Almost identical to Linux driver.


   struct {
   struct {
     __in u32 max;
     __in u32 hActive;
    __in u32 vActive;
    __in u32 hSyncWidth;
    __in u32 vSyncWidth;
    __in u32 hFrontPorch;
    __in u32 vFrontPorch;
    __in u32 hBackPorch;
    __in u32 vBackPorch;
    __in u32 hRefToSync;
    __in u32 vRefToSync;
    __in u32 pclkKHz;
    __in u32 bitsPerPixel;
    __in u32 vmode;
    __in u32 sync;
   };
   };


=== NVDISP_SET_BACKLIGHT_RANGE_MIN ===
=== NVDISP_VALIDATE_MODE ===
Sets the minimum value for the intensity of the display's backlight.
Almost identical to Linux driver.


   struct {
   struct {
     __in u32 min;
     __inout u32 hActive;
    __inout u32 vActive;
    __inout u32 hSyncWidth;
    __inout u32 vSyncWidth;
    __inout u32 hFrontPorch;
    __inout u32 vFrontPorch;
    __inout u32 hBackPorch;
    __inout u32 vBackPorch;
    __inout u32 hRefToSync;
    __inout u32 vRefToSync;
    __inout u32 pclkKHz;
    __inout u32 bitsPerPixel;
    __inout u32 vmode;
    __inout u32 sync;
   };
   };


=== NVDISP_SEND_PANEL_MSG ===
=== NVDISP_GET_AVI_INFOFRAME ===
Sends raw data to the display panel over DPAUX.
Unpacked standard AVI infoframe struct (HDMI v1.4b/2.0)


   struct {
   struct {
     __in u32 cmd;         // DPAUX AUXCTL command (1=unk, 2=I2CWR, 4=MOTWR, 7=AUXWR)
     __out u32 csum;
     __in u32 addr;         // DPAUX AUXADDR
     __out u32 scan;
     __in u32 size;         // message size
     __out u32 bar_valid;
     __in u32 msg[4];       // raw AUXDATA message
     __out u32 act_fmt_valid;
    __out u32 rgb_ycc;
    __out u32 act_format;
    __out u32 aspect_ratio;
    __out u32 colorimetry;
    __out u32 scaling;
    __out u32 rgb_quant;
    __out u32 ext_colorimetry;
    __out u32 it_content;
    __out u32 video_format;
    __out u32 pix_rep;
    __out u32 it_content_type;
    __out u32 ycc_quant;
    __out u32 top_bar_end_line_lsb;
    __out u32 top_bar_end_line_msb;
    __out u32 bot_bar_start_line_lsb;
    __out u32 bot_bar_start_line_msb;
    __out u32 left_bar_end_pixel_lsb;
    __out u32 left_bar_end_pixel_msb;
    __out u32 right_bar_start_pixel_lsb;
    __out u32 right_bar_start_pixel_msb;
   };
   };


=== NVDISP_GET_PANEL_DATA ===
=== NVDISP_SET_AVI_INFOFRAME ===
Receives raw data from the display panel over DPAUX.
Unpacked standard AVI infoframe struct (HDMI v1.4b/2.0)


   struct {
   struct {
     __in u32 cmd;         // DPAUX AUXCTL command (3=I2CRD, 5=MOTRD, 6=AUXRD)
     __in u32 csum;
     __in u32 addr;         // DPAUX AUXADDR
     __in u32 scan;
     __in u32 size;         // message size
     __in u32 bar_valid;
     __out u32 msg[4];     // raw AUXDATA message
     __in u32 act_fmt_valid;
    __in u32 rgb_ycc;
    __in u32 act_format;
    __in u32 aspect_ratio;
    __in u32 colorimetry;
    __in u32 scaling;
    __in u32 rgb_quant;
    __in u32 ext_colorimetry;
    __in u32 it_content;
    __in u32 video_format;
    __in u32 pix_rep;
    __in u32 it_content_type;
    __in u32 ycc_quant;
    __in u32 top_bar_end_line_lsb;
    __in u32 top_bar_end_line_msb;
    __in u32 bot_bar_start_line_lsb;
    __in u32 bot_bar_start_line_msb;
    __in u32 left_bar_end_pixel_lsb;
    __in u32 left_bar_end_pixel_msb;
    __in u32 right_bar_start_pixel_lsb;
    __in u32 right_bar_start_pixel_msb;
   };
   };


== /dev/nvcec-ctrl ==
=== NVDISP_GET_MODE_DB ===
{| class="wikitable" border="1"
Almost identical to Linux driver.
! Value || Direction || Size || Description
 
|-
  struct mode {
| 0x40010301 || In || 1 || NVCEC_CTRL_ENABLE
    u32 hActive;
|-
    u32 vActive;
| 0x804C0302 || Out || 76 || NVCEC_CTRL_GET_PADDR
    u32 hSyncWidth;
|-
    u32 vSyncWidth;
| 0x40040303 || In || 4 || NVCEC_CTRL_SET_LADDR
    u32 hFrontPorch;
|-
    u32 vFrontPorch;
| 0xC04C0304 || Inout || 76 || NVCEC_CTRL_WRITE
    u32 hBackPorch;
|-
    u32 vBackPorch;
| 0xC04C0305 || Inout || 76 || NVCEC_CTRL_READ
    u32 hRefToSync;
|-
    u32 vRefToSync;
| 0x804C0306 || Out || 76 || NVCEC_CTRL_GET_CONNECTION_STATUS
    u32 pclkKHz;
|-
    u32 bitsPerPixel;
| 0x804C0307 || Out || 76 || NVCEC_CTRL_GET_WRITE_STATUS
    u32 vmode;
|}
    u32 sync;
  };
  struct {
    __out struct mode modes[201];
    __out u32 num_modes;
  };
 
=== NVDISP_PANEL_GET_VENDOR_ID ===
 
Returns display panel's informations.


== /dev/nvhdcp_up-ctrl ==
  struct {
{| class="wikitable" border="1"
    __out u8 vendor; //0x10 - JDI, 0x20 - InnoLux, 0x30 - AUO, 0x40 - Sharp, 0x50 - Samsung
! Value || Direction || Size || Description
    __out u8 model;
|-
    __out u8 board; //0xF - 6.2", 0x10 - 5.5", 0x20 - 7.0". JDI panels have nonstandard values
| 0xC4880401 || Inout || 1160 || NVHDCP_READ_STATUS
  };
|-
 
| 0xC4880402 || Inout || 1160 || NVHDCP_READ_M
=== NVDISP_GET_MODE2 ===
|-
 
| 0x40010403 || In || 1 || NVHDCP_ENABLE
  struct {
|-
    __out u32 unk0;              //Always 0
| 0xC0080404 || Inout || 8 || NVHDCP_CTRL_STATE_TRANSIT_EVENT_DATA
    __out u32 hActive;
|-
    __out u32 vActive;
| 0xC0010405 || Inout || 1 || NVHDCP_CTRL_STATE_CB
    __out u32 hSyncWidth;
|}
    __out u32 vSyncWidth;
    __out u32 hFrontPorch;
    __out u32 vFrontPorch;
    __out u32 hBackPorch;
    __out u32 vBackPorch;
    __out u32 pclkKHz;
    __out u32 bitsPerPixel;      // Always 0
    __out u32 vmode;            // Always 0
    __out u32 sync;
    __out u32 unk1;
    __out u32 reserved;
  };
 
=== NVDISP_SET_MODE2 ===


== /dev/nvdcutil-disp0, /dev/nvdcutil-disp1 ==
  struct {
{| class="wikitable" border="1"
    __in u32 unk0;
! Value || Direction || Size || Description
    __in u32 hActive;
|-
    __in u32 vActive;
| 0x40010501 || In || 1 || NVDCUTIL_ENABLE_CRC
    __in u32 hSyncWidth;
|-
    __in u32 vSyncWidth;
| 0x40010502 || In || 1 || NVDCUTIL_VIRTUAL_EDID_ENABLE
    __in u32 hFrontPorch;
|-
    __in u32 vFrontPorch;
| 0x42040503 || In || 1056 || NVDCUTIL_VIRTUAL_EDID_SET_DATA
    __in u32 hBackPorch;
|-
    __in u32 vBackPorch;
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
    __in u32 pclkKHz;
|-
    __in u32 bitsPerPixel;
| 0x40010505 || In || 1 || NVDCUTIL_BEGIN_TELEMETRY_TEST
    __in u32 vmode;
|-
    __in u32 sync;
| 0x400C0506 || In || 12 || NVDCUTIL_DSI_PACKET_TEST_SHORT_WRITE
    __in u32 unk1;
|-
    __in u32 reserved;
| 0x40F80507 || In || 248 || NVDCUTIL_DSI_PACKET_TEST_LONG_WRITE
  };
|-
 
| 0xC0F40508 || Inout || 244 || NVDCUTIL_DSI_PACKET_TEST_READ
=== NVDISP_VALIDATE_MODE2 ===
|-
| 0x40010509 || In || 1 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_EN
|-
| 0xC020050A || Inout || 32 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_SETTINGS
|-
| 0x8070050B || Out || 112 || [11.0.0+] NVDCUTIL_DP_CONF_READ
|}


== /dev/nvsched-ctrl ==
  struct {
This is a customized scheduler device.
    __inout u32 unk0;
    __inout u32 hActive;
    __inout u32 vActive;
    __inout u32 hSyncWidth;
    __inout u32 vSyncWidth;
    __inout u32 hFrontPorch;
    __inout u32 vFrontPorch;
    __inout u32 hBackPorch;
    __inout u32 vBackPorch;
    __inout u32 pclkKHz;
    __inout u32 bitsPerPixel;
    __inout u32 vmode;
    __inout u32 sync;
    __inout u32 unk1;
    __inout u32 reserved;
  };


The way this device is exposed and configured is exclusive to the Switch, since other sources don't have an actual interface for the scheduler.
=== NVDISP_GET_MODE_DB2 ===


{| class="wikitable" border="1"
  struct mode2 {
! Value || Direction || Size || Description
    u32 unk0;
|-
    u32 hActive;
| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE]]
    u32 vActive;
|-
    u32 hSyncWidth;
| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE]]
    u32 vSyncWidth;
|-
    u32 hFrontPorch;
| 0x40180603 || In || 24 || [[#NVSCHED_CTRL_ADD_APPLICATION]]
    u32 vFrontPorch;
|-
    u32 hBackPorch;
| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION]]
    u32 vBackPorch;
|-
    u32 pclkKHz;
| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION]]
    u32 bitsPerPixel;
|-
    u32 vmode;
| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID]]
    u32 sync;
|-
    u32 unk1;
| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST]]
    u32 reserved;
|-
  };
| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST]]
|-
  struct {
| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST]]
    __out struct mode2 modes[201];
|-
    __out u32 num_modes;
| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST]]
  };
|-
 
| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST]]
=== NVDISP_GET_BACKLIGHT_RANGE ===
|-
Returns the minimum and maximum values for the intensity of the display's backlight.
| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]]
 
|-
  struct {
| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]
    __out u32 min;
|-
    __out u32 max;
| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]
  };
|-
 
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]
=== NVDISP_SET_BACKLIGHT_RANGE_MAX ===
|-
Sets the maximum value for the intensity of the display's backlight.
| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT
 
|-
  struct {
| 0x40100611 || In || 16 || NVSCHED_CTRL_SET_RUNLIST_MAX_DEBT
    __in u32 max;
|-
  };
| 0x40010612 || In || 1 || NVSCHED_CTRL_OVERRUN_EVENTS_ENABLE
|}


=== NVSCHED_CTRL_ENABLE ===
=== NVDISP_SET_BACKLIGHT_RANGE_MIN ===
Enables the scheduler.
Sets the minimum value for the intensity of the display's backlight.
 
=== NVSCHED_CTRL_DISABLE ===
Disables the scheduler.
 
=== NVSCHED_CTRL_ADD_APPLICATION ===
Adds a new application to the scheduler.


   struct {
   struct {
     __in u64 application_id;
     __in u32 min;
    __in u64 priority;
    __in u64 timeslice;
   };
   };


=== NVSCHED_CTRL_UPDATE_APPLICATION ===
=== NVDISP_SEND_PANEL_MSG ===
Updates the application parameters in the scheduler.
Sends raw data to the display panel over DPAUX.


   struct {
   struct {
     __in u64 application_id;
     __in u32 cmd;         // DPAUX AUXCTL command (1=unk, 2=I2CWR, 4=MOTWR, 7=AUXWR)
     __in u64 priority;
     __in u32 addr;         // DPAUX AUXADDR
     __in u64 timeslice;
     __in u32 size;         // message size
    __in u32 msg[4];      // raw AUXDATA message
   };
   };


=== NVSCHED_CTRL_REMOVE_APPLICATION ===
=== NVDISP_GET_PANEL_DATA ===
Removes the application from the scheduler.
Receives raw data from the display panel over DPAUX.


   struct {
   struct {
     __in u64 application_id;
     __in u32 cmd;         // DPAUX AUXCTL command (3=I2CRD, 5=MOTRD, 6=AUXRD)
    __in u32 addr;        // DPAUX AUXADDR
    __in u32 size;        // message size
    __out u32 msg[4];      // raw AUXDATA message
   };
   };


=== NVSCHED_CTRL_GET_ID ===
== /dev/nvcec-ctrl ==
Returns the ID of the last scheduled object.
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0x40010301 || In || 1 || NVCEC_CTRL_ENABLE
|-
| 0x804C0302 || Out || 76 || NVCEC_CTRL_GET_PADDR
|-
| 0x40040303 || In || 4 || NVCEC_CTRL_SET_LADDR
|-
| 0xC04C0304 || Inout || 76 || NVCEC_CTRL_WRITE
|-
| 0xC04C0305 || Inout || 76 || NVCEC_CTRL_READ
|-
| 0x804C0306 || Out || 76 || NVCEC_CTRL_GET_CONNECTION_STATUS
|-
| 0x804C0307 || Out || 76 || NVCEC_CTRL_GET_WRITE_STATUS
|}


  struct {
== /dev/nvhdcp_up-ctrl ==
    __out u64 id;
{| class="wikitable" border="1"
  };
! Value || Direction || Size || Description
|-
| 0xC4880401 || Inout || 1160 || NVHDCP_READ_STATUS
|-
| 0xC4880402 || Inout || 1160 || NVHDCP_READ_M
|-
| 0x40010403 || In || 1 || NVHDCP_ENABLE
|-
| 0xC0080404 || Inout || 8 || NVHDCP_CTRL_STATE_TRANSIT_EVENT_DATA
|-
| 0xC0010405 || Inout || 1 || NVHDCP_CTRL_STATE_CB
|}


=== NVSCHED_CTRL_ADD_RUNLIST ===
== /dev/nvdcutil-disp0, /dev/nvdcutil-disp1 ==
Creates a new runlist and returns it's ID.
{| class="wikitable" border="1"
 
! Value || Direction || Size || Description
  struct {
|-
    __out u64 runlist_id;
| 0x40010501 || In || 1 || NVDCUTIL_ENABLE_CRC
  };
|-
 
| 0x40010502 || In || 1 || [[#NVDCUTIL_VIRTUAL_EDID_ENABLE]]
=== NVSCHED_CTRL_UPDATE_RUNLIST ===
|-
Updates the runlist parameters in the scheduler.
| 0x42040503 || In || 516 || [[#NVDCUTIL_VIRTUAL_EDID_SET_DATA]]
|-
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
|-
| 0x40010505 || In || 1 || NVDCUTIL_BEGIN_TELEMETRY_TEST
|-
| 0x400C0506 || In || 12 || NVDCUTIL_DSI_PACKET_TEST_SHORT_WRITE
|-
| 0x40F80507 || In || 248 || NVDCUTIL_DSI_PACKET_TEST_LONG_WRITE
|-
| 0xC0F40508 || Inout || 244 || NVDCUTIL_DSI_PACKET_TEST_READ
|-
| 0x40010509 || In || 1 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_EN
|-
| 0xC020050A || Inout || 32 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_SETTINGS
|-
| 0x8070050B || Out || 112 || [11.0.0+] NVDCUTIL_DP_CONF_READ
|}
 
=== NVDCUTIL_VIRTUAL_EDID_ENABLE ===


   struct {
   struct {
     __in u64 runlist_id;
     __in u8 enable;
    __in u64 priority;
    __in u64 timeslice;
   };
   };


=== NVSCHED_CTRL_LINK_RUNLIST ===
=== NVDCUTIL_VIRTUAL_EDID_SET_DATA ===
Links a runlist to a given application in the scheduler.


   struct {
   struct {
     __in u64 runlist_id;
     __in u8 edid[512];
     __in u64 application_id;
     __in u32 edid_size;
   };
   };


=== NVSCHED_CTRL_UNLINK_RUNLIST ===
== /dev/nvsched-ctrl ==
Unlinks a runlist from a given application in the scheduler.
This is a customized scheduler device.


  struct {
The way this device is exposed and configured is exclusive to the Switch, since other sources don't have an actual interface for the scheduler.
    __in u64 runlist_id;
    __in u64 application_id;
  };


=== NVSCHED_CTRL_REMOVE_RUNLIST ===
{| class="wikitable" border="1"
Removes the runlist from the scheduler.
! Value || Direction || Size || Description
 
|-
  struct {
| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE]]
    __in u64 runlist_id;
|-
  };
| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE]]
 
|-
=== NVSCHED_CTRL_HAS_OVERRUN_EVENT ===
| 0x40180603 || In || 24 || [[#NVSCHED_CTRL_ADD_APPLICATION]]
Returns a boolean to tell if the scheduler has an overrun event or not.
|-
 
| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION]]
  struct {
|-
    __out u8 has_overrun;
| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION]]
  };
|-
 
| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID]]
=== NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT ===
|-
Returns the overrun event's data from the scheduler.
| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST]]
 
|-
  struct {
| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST]]
    __out u64 runlist_id;
|-
    __out u64 debt;
| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST]]
    __out u64 unk0;          // 3.0.0+ only
|-
    __out u64 unk1;          // 3.0.0+ only
| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST]]
  };
|-
 
| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST]]
=== NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE ===
|-
Installs a fence swap event?
| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]]
|-
| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]
|-
| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]
|-
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]
|-
| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT
|-
| 0x40100611 || In || 16 || NVSCHED_CTRL_SET_RUNLIST_MAX_DEBT
|-
| 0x40010612 || In || 1 || NVSCHED_CTRL_OVERRUN_EVENTS_ENABLE
|}


  struct {
=== NVSCHED_CTRL_ENABLE ===
    __in u32 fence_id;
Enables the scheduler.
    __in u32 fence_value;
    __in u32 swap_interval;
  };


=== NVSCHED_CTRL_DETACH_APPLICATION ===
=== NVSCHED_CTRL_DISABLE ===
Places the given application in detached state.
Disables the scheduler.


   struct {
=== NVSCHED_CTRL_ADD_APPLICATION ===
Adds a new application to the scheduler.
 
   struct {
     __in u64 application_id;
     __in u64 application_id;
    __in u64 priority;
    __in u64 timeslice;
   };
   };


== /dev/nverpt-ctrl ==
=== NVSCHED_CTRL_UPDATE_APPLICATION ===
Added in firmware version 3.0.0.
Updates the application parameters in the scheduler.


{| class="wikitable" border="1"
  struct {
! Value || Direction || Size || Description
    __in u64 application_id;
|-
    __in u64 priority;
| 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA]]
    __in u64 timeslice;
|-
  };
| 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]]
|}


=== NVERPT_TELEMETRY_SUBMIT_DATA ===
=== NVSCHED_CTRL_REMOVE_APPLICATION ===
Sends test data for creating a new [[Error_Report_services|Error Report]].
Removes the application from the scheduler.


   struct {
   struct {
     __in u64 TestU64;
     __in u64 application_id;
    __in u32 TestU32;
   };
    __in u8  padding0[4];
    __in s64 TestI64;
    __in s32 TestI32;
    __in u8  TestString[32];
    __in u8  TestU8Array[8];
    __in u32 TestU8Array_size;
    __in u32 TestU32Array[8];
    __in u32 TestU32Array_size;
    __in u64 TestU64Array[8];
    __in u32 TestU64Array_size;
    __in s32 TestI32Array[8];
    __in u32 TestI32Array_size;
    __in s64 TestI64Array[8];
    __in u32 TestI64Array_size;
    __in u16 TestU16;
    __in u8  TestU8;
    __in s16 TestI16;
    __in s8  TestI8;
    __in u8  padding1[5];
   };


=== NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA ===
=== NVSCHED_CTRL_GET_ID ===
Sends display data for creating a new [[Error_Report_services|Error Report]].
Returns the ID of the last scheduled object.


   struct {
   struct {
     __in u32 CodecType;
     __out u64 id;
    __in u32 DecodeBuffers;
   };
    __in u32 FrameWidth;
    __in u32 FrameHeight;
    __in u8  ColorPrimaries;
    __in u8  TransferCharacteristics;
    __in u8  MatrixCoefficients;
    __in u8  padding;
    __in u32 DisplayWidth;
    __in u32 DisplayHeight;
    __in u32 DARWidth;
    __in u32 DARHeight;
    __in u32 ColorFormat;
    __in u32 ColorSpace[8];
    __in u32 ColorSpace_size;
    __in u32 SurfaceLayout[8];
    __in u32 SurfaceLayout_size;
    __in u8  ErrorString[64];      // must be "Error detected = 0x1000000"
    __in u32 VideoDecState;
    __in u8  VideoLog[3712];
    __in u32 VideoLog_size;
   };


== /dev/nvhost-as-gpu ==
=== NVSCHED_CTRL_ADD_RUNLIST ===
Each fd opened to this device creates an address space. An address space is then later bound with a channel.
Creates a new runlist and returns it's ID.


Once a nvgpu channel has been bound to an address space it cannot be unbound. There is no support for allowing an nvgpu channel to change from one address space to another (or from one to none).
  struct {
                                                                                                                             
    __out u64 runlist_id;
{| class="wikitable" border="1"
  };
! Value || Direction || Size || Description
|-
| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL]]
|-
| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE]]
|-
| 0xC0104103 || Inout || 16 || [[#NVGPU_AS_IOCTL_FREE_SPACE]]
|-
| 0xC0184104 || Inout || 24 || [[#NVGPU_AS_IOCTL_MAP_BUFFER]]
|-
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
|-
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
|-
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]
|-
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS]]
|-
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
|}


=== NVGPU_AS_IOCTL_BIND_CHANNEL ===
=== NVSCHED_CTRL_UPDATE_RUNLIST ===
Identical to Linux driver.
Updates the runlist parameters in the scheduler.


   struct {
   struct {
     __in u32 channel_fd;
     __in u64 runlist_id;
    __in u64 priority;
    __in u64 timeslice;
   };
   };


=== NVGPU_AS_IOCTL_ALLOC_SPACE ===
=== NVSCHED_CTRL_LINK_RUNLIST ===
Reserves pages in the device address space.
Links a runlist to a given application in the scheduler.


   struct {
   struct {
     __in u32 pages;
     __in u64 runlist_id;
    __in u32 page_size;
     __in u64 application_id;
     __in u32 flags;
    u32      padding;
    union {
      __out u64 offset;
      __in  u64 align;
    };
   };
   };


=== NVGPU_AS_IOCTL_FREE_SPACE ===
=== NVSCHED_CTRL_UNLINK_RUNLIST ===
Frees pages from the device address space.
Unlinks a runlist from a given application in the scheduler.


   struct {
   struct {
     __in u64 offset;
     __in u64 runlist_id;
     __in u32 pages;
     __in u64 application_id;
    __in u32 page_size;
   };
   };


=== NVGPU_AS_IOCTL_MAP_BUFFER ===
=== NVSCHED_CTRL_REMOVE_RUNLIST ===
Maps a memory region in the device address space.
Removes the runlist from the scheduler.


Unaligned size will cause a [[#Panic]].
  struct {
    __in u64 runlist_id;
  };


On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
=== NVSCHED_CTRL_HAS_OVERRUN_EVENT ===
Returns a boolean to tell if the scheduler has an overrun event or not.


   struct {
   struct {
     __in    u32 flags;        // bit0: fixed_offset, bit2: cacheable
     __out u8 has_overrun;
    u32        reserved0;
    __in    u32 mem_id;      // nvmap handle
    u32        reserved1;
    union {
      __out u64 offset;
      __in  u64 align;
    };
   };
   };


=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
=== NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT ===
Maps a memory region in the device address space with extra params.
Returns the overrun event's data from the scheduler.


Unaligned size will cause a [[#Panic]].
  struct {
    __out u64 runlist_id;
    __out u64 debt;
    __out u64 unk0;          // 3.0.0+ only
    __out u64 unk1;          // 3.0.0+ only
  };


On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
=== NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE ===
Installs a fence swap event?


   struct {
   struct {
     __in     u32 flags;         // bit0: fixed_offset, bit2: cacheable
     __in u32 fence_id;
     __inout  u32 kind;           // -1 is default
     __in u32 fence_value;
     __in     u32 mem_id;        // nvmap handle
     __in u32 swap_interval;
    u32           reserved;
    __in      u64 buffer_offset;
    __in      u64 mapping_size;
    union {
      __out  u64 offset;
      __in    u64 align;
    };
   };
   };


=== NVGPU_AS_IOCTL_UNMAP_BUFFER ===
=== NVSCHED_CTRL_DETACH_APPLICATION ===
Unmaps a memory region from the device address space.
Places the given application in detached state.


struct {
  struct {
     __in u64 offset;
     __in u64 application_id;
   };
   };


=== NVGPU_AS_IOCTL_ALLOC_AS ===
== /dev/nverpt-ctrl ==
Nintendo's custom implementation for allocating an address space.
Added in firmware version 3.0.0.


  struct {
{| class="wikitable" border="1"
    __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
! Value || Direction || Size || Description
    __in s32 as_fd;          // ignored; passes 0
|-
    __in u64 reserved;        // ignored; passes 0
| 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA]]
  };
|-
| 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]]
|}


=== NVGPU_AS_IOCTL_GET_VA_REGIONS ===
=== NVERPT_TELEMETRY_SUBMIT_DATA ===
Nintendo's custom implementation to get rid of pointer in struct.
Sends test data for creating a new [[Error_Report_services|Error Report]].


Uses [[#Ioctl3|Ioctl3]].
  struct {
 
    __in u64 TestU64;
  struct va_region {
    __in u32 TestU32;
     u64 offset;
    __in u8  padding0[4];
     u32 page_size;
    __in s64 TestI64;
     u32 reserved;
    __in s32 TestI32;
     u64 pages;
    __in u8  TestString[32];
    __in u8  TestU8Array[8];
    __in u32 TestU8Array_size;
    __in u32 TestU32Array[8];
    __in u32 TestU32Array_size;
     __in u64 TestU64Array[8];
     __in u32 TestU64Array_size;
     __in s32 TestI32Array[8];
    __in u32 TestI32Array_size;
     __in s64 TestI64Array[8];
    __in u32 TestI64Array_size;
    __in u16 TestU16;
    __in u8  TestU8;
    __in s16 TestI16;
    __in s8  TestI8;
    __in u8  padding1[5];
   };
   };
 
 
=== NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA ===
Sends display data for creating a new [[Error_Report_services|Error Report]].
 
   struct {
   struct {
     u64          buf_addr;   // (contained output user ptr on linux, ignored)
     __in u32 CodecType;
     __inout u32   buf_size;   // forced to 2*sizeof(struct va_region)
    __in u32 DecodeBuffers;
     u32           reserved;
    __in u32 FrameWidth;
     __out struct va_region regions[2];
    __in u32 FrameHeight;
    __in u8  ColorPrimaries;
    __in u8  TransferCharacteristics;
    __in u8  MatrixCoefficients;
    __in u8  padding;
    __in u32 DisplayWidth;
    __in u32 DisplayHeight;
    __in u32 DARWidth;
    __in u32 DARHeight;
    __in u32 ColorFormat;
    __in u32 ColorSpace[8];
    __in u32 ColorSpace_size;
    __in u32 SurfaceLayout[8];
     __in u32 SurfaceLayout_size;
    __in u8  ErrorString[64];      // must be "Error detected = 0x1000000"
     __in u32 VideoDecState;
     __in u8 VideoLog[3712];
    __in u32 VideoLog_size;
   };
   };


=== NVGPU_AS_IOCTL_ALLOC_AS_EX ===
== /dev/nvhost-as-gpu ==
Nintendo's custom implementation for allocating an address space with extra params.
Each fd opened to this device creates an address space. An address space is then later bound with a channel.


  struct {
Once a nvgpu channel has been bound to an address space it cannot be unbound. There is no support for allowing an nvgpu channel to change from one address space to another (or from one to none).
    __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
                                                                                                                             
    __in s32 as_fd;          // ignored; passes 0
{| class="wikitable" border="1"
    __in u32 flags;          // passes 0
! Value || Direction || Size || Description
    __in u32 reserved;        // ignored; passes 0
|-
    __in u64 va_range_start;
| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL]]
    __in u64 va_range_end;
|-
    __in u64 va_range_split;
| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE]]
  };
|-
 
| 0xC0104103 || Inout || 16 || [[#NVGPU_AS_IOCTL_FREE_SPACE]]
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX2 ===
|-
Maps a memory region in the device address space with extra params.
| 0xC0184104 || Inout || 24 || [[#NVGPU_AS_IOCTL_MAP_BUFFER]]
 
|-
Unaligned size will cause a [[#Panic]].
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
|-
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
|-
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]
|-
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS]]
|-
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
|}


On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
=== NVGPU_AS_IOCTL_BIND_CHANNEL ===
Identical to Linux driver.


   struct {
   struct {
     __in     u32 flags;         // bit0: fixed_offset, bit2: cacheable
     __in u32 channel_fd;
    __inout   u32 kind;           // -1 is default
   };
     __in     u32 mem_id;         // nvmap handle
 
     u32           reserved0;
=== NVGPU_AS_IOCTL_ALLOC_SPACE ===
     __in     u64 buffer_offset;
Reserves pages in the device address space.
     __in     u64 mapping_size;
 
  struct {
     __in u32 pages;
     __in u32 page_size;
     __in u32 flags;
     u32     padding;
     union {
     union {
       __out   u64 offset;
       __out u64 offset;
       __in   u64 align;
       __in u64 align;
     };
     };
    __in      u64 vma_addr;
    __in      u32 pages;
    u32          reserved1;
   };
   };


=== NVGPU_AS_IOCTL_REMAP ===
=== NVGPU_AS_IOCTL_FREE_SPACE ===
Nintendo's custom implementation of address space remapping for sparse pages.
Frees pages from the device address space.


   struct remap_op {
   struct {
     __in u16 flags;                      // bit2: cacheable
     __in u64 offset;
    __in u16 kind;         
     __in u32 pages;
    __in u32 mem_handle;
     __in u32 page_size;
    __in u32 mem_offset_in_pages;
     __in u32 virt_offset_in_pages;       // (alloc_space_offset >> 0x10)
     __in u32 num_pages;                 // alloc_space_pages
   };
   };
struct {
    __in struct remap_op entries[];
};


== /dev/nvhost-dbg-gpu ==
=== NVGPU_AS_IOCTL_MAP_BUFFER ===
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.
Maps a memory region in the device address space.
 
Unaligned size will cause a [[#Panic]].
 
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


{| class="wikitable" border="1"
  struct {
! Value || Direction || Size || Description
    __in    u32 flags;        // bit0: fixed_offset, bit2: cacheable
|-
    u32        reserved0;
| 0x40084401 || In || 8 || NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL
    __in    u32 mem_id;      // nvmap handle
|-
    u32        reserved1;
| 0xC0??4402 || Inout || Variable || NVGPU_DBG_GPU_IOCTL_REG_OPS
    union {
|-
      __out u64 offset;
| 0x40084403 || In || 8 || NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL
      __in  u64 align;
|-
    };
| 0x40044404 || In || 4 || NVGPU_DBG_GPU_IOCTL_POWERGATE
  };
|-
 
| 0x40044405 || In || 4 || NVGPU_DBG_GPU_IOCTL_SMPC_CTXSW_MODE
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
|-
Maps a memory region in the device address space with extra params.
| 0x40044406 || In || 4 || NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_ALL_SMS
 
|-
Unaligned size will cause a [[#Panic]].
| 0xC0184407 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_PERFBUF_MAP
 
|-
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
| 0x40084408 || In || 8 || NVGPU_DBG_GPU_IOCTL_PERFBUF_UNMAP
 
|-
  struct {
| 0x40084409 || In || 8 || NVGPU_DBG_GPU_IOCTL_PC_SAMPLING
    __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
|-
    __inout  u32 kind;          // -1 is default
| 0x4008440A || In || 8 || NVGPU_DBG_GPU_IOCTL_TIMEOUT
    __in      u32 mem_id;        // nvmap handle
|-
    u32          reserved;
| 0x8008440B || Out || 8 || NVGPU_DBG_GPU_IOCTL_GET_TIMEOUT
    __in      u64 buffer_offset;
|-
    __in      u64 mapping_size;
| 0x8004440C || Out || 4 || NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT_SIZE
    union {
|-
      __out  u64 offset;
| 0x0000440D || None || 0 || [[#NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT]]
      __in    u64 align;
|-
    };
| 0xC018440E || Inout || 24 || NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
  };
|-
 
| 0xC018440F || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PDES
=== NVGPU_AS_IOCTL_UNMAP_BUFFER ===
|-
Unmaps a memory region from the device address space.
| 0xC0104410 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES]]
 
|-
struct {
| 0xC0184411 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PTES
    __in u64 offset;
|-
  };
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
|-
| 0xC0684413 || Inout || 104 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
|-
| 0xC0184414 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
|-
| 0xC0184415 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
|-
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
|-
| 0xC0104417 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_COMPTAGS
|-
| 0xC0104418 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_PA
|-
| 0xC0104419 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_PA
|-
| 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA
|-
| 0xC020441B || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA_EX
|-
| 0xC084441C || Inout || 132 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SETTINGS
|-
| 0xC018441D || Inout || 24 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SERIAL_NUMBER
|-
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
|}


=== NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT ===
=== NVGPU_AS_IOCTL_ALLOC_AS ===
Uses [[#Ioctl3|Ioctl3]].
Nintendo's custom implementation for allocating an address space.


=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES ===
  struct {
Uses [[#Ioctl3|Ioctl3]].
    __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
    __in s32 as_fd;          // ignored; passes 0
    __in u64 reserved;        // ignored; passes 0
  };


=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES ===
=== NVGPU_AS_IOCTL_GET_VA_REGIONS ===
Uses [[#Ioctl3|Ioctl3]].
Nintendo's custom implementation to get rid of pointer in struct.


=== NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS ===
Uses [[#Ioctl3|Ioctl3]].
Uses [[#Ioctl3|Ioctl3]].


=== NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS ===
  struct va_region {
Uses [[#Ioctl2|Ioctl2]].
    u64 offset;
 
    u32 page_size;
== /dev/nvhost-prof-gpu ==
    u32 reserved;
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.
    u64 pages;
 
  };
This device is identical to [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]].
 
  struct {
    u64          buf_addr;    // (contained output user ptr on linux, ignored)
    __inout u32  buf_size;    // forced to 2*sizeof(struct va_region)
    u32          reserved;
    __out struct  va_region regions[2];
  };
 
=== NVGPU_AS_IOCTL_ALLOC_AS_EX ===
Nintendo's custom implementation for allocating an address space with extra params.


== /dev/nvhost-ctrl-gpu ==
  struct {
This device is for global (context independent) operations on the gpu. 
    __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
                                                                                                                                             
    __in s32 as_fd;          // ignored; passes 0
{| class="wikitable" border="1"
    __in u32 flags;          // passes 0
! Value || Direction || Size || Description
    __in u32 reserved;        // ignored; passes 0
|-
    __in u64 va_range_start;
| 0x80044701 || Out || 4 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE]]
    __in u64 va_range_end;
|-
    __in u64 va_range_split;
| 0x80284702 || Out || 40 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_INFO]]
  };
|-
 
| 0x402C4703 || In || 44 || [[#NVGPU_GPU_IOCTL_ZBC_SET_TABLE]]
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX2 ===
|-
Maps a memory region in the device address space with extra params.
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
 
|-
Unaligned size will cause a [[#Panic]].
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
 
|-
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
 
|-
  struct {
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
    __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
|-
    __inout  u32 kind;          // -1 is default
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]
    __in      u32 mem_id;        // nvmap handle
|-
    u32          reserved0;
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
    __in      u64 buffer_offset;
|-
    __in      u64 mapping_size;
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
    union {
|-
      __out  u64 offset;
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
      __in    u64 align;
|-
    };
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
    __in      u64 vma_addr;
|-
    __in      u32 pages;
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
    u32          reserved1;
|-
  };
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
 
|-
=== NVGPU_AS_IOCTL_REMAP ===
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
Nintendo's custom implementation of address space remapping for sparse pages.
|-
 
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
  struct remap_op {
|-
    __in u16 flags;                      // bit2: cacheable
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
    __in u16 kind;         
    __in u32 mem_handle;
    __in u32 mem_offset_in_pages;
    __in u32 virt_offset_in_pages;      // (alloc_space_offset >> 0x10)
    __in u32 num_pages;                  // alloc_space_pages
  };
struct {
    __in struct remap_op entries[];
};
 
== /dev/nvhost-dbg-gpu ==
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.
 
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
|-
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
| 0x40084401 || In || 8 || NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL
|-
|-
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
| 0xC0??4402 || Inout || Variable || NVGPU_DBG_GPU_IOCTL_REG_OPS
|-
|-
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
| 0x40084403 || In || 8 || NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL
|-
|-
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
| 0x40044404 || In || 4 || NVGPU_DBG_GPU_IOCTL_POWERGATE
|-
|-
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
| 0x40044405 || In || 4 || NVGPU_DBG_GPU_IOCTL_SMPC_CTXSW_MODE
|-
| 0x40044406 || In || 4 || NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_ALL_SMS
|-
| 0xC0184407 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_PERFBUF_MAP
|-
| 0x40084408 || In || 8 || NVGPU_DBG_GPU_IOCTL_PERFBUF_UNMAP
|-
| 0x40084409 || In || 8 || NVGPU_DBG_GPU_IOCTL_PC_SAMPLING
|-
| 0x4008440A || In || 8 || NVGPU_DBG_GPU_IOCTL_TIMEOUT
|-
| 0x8008440B || Out || 8 || NVGPU_DBG_GPU_IOCTL_GET_TIMEOUT
|-
|-
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
| 0x8004440C || Out || 4 || NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT_SIZE
|-
|-
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
| 0x0000440D || None || 0 || [[#NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT]]
|}
|-
 
| 0xC018440E || Inout || 24 || NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
=== NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE ===
|-
Returns the GPU's ZCULL context size. Identical to Linux driver.
| 0xC018440F || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PDES
 
|-
struct {
| 0xC0104410 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES]]
    __out u32 size;
|-
  };
| 0xC0184411 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PTES
 
|-
=== NVGPU_GPU_IOCTL_ZCULL_GET_INFO ===
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
Returns GPU's ZCULL information. Identical to Linux driver.
|-
 
| 0xC0684413 || Inout || 104 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
struct {
|-
    __out u32 width_align_pixels;
| 0xC0184414 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
    __out u32 height_align_pixels;
|-
    __out u32 pixel_squares_by_aliquots;
| 0xC0184415 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
    __out u32 aliquot_total;
|-
    __out u32 region_byte_multiplier;
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
    __out u32 region_header_size;
|-
    __out u32 subregion_header_size;
| 0xC0104417 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_COMPTAGS
    __out u32 subregion_width_align_pixels;
|-
    __out u32 subregion_height_align_pixels;
| 0xC0104418 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_PA
    __out u32 subregion_count;
|-
  };
| 0xC0104419 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_PA
 
|-
=== NVGPU_GPU_IOCTL_ZBC_SET_TABLE ===
| 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA
Sets the active ZBC table. Identical to Linux driver.
|-
| 0xC020441B || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA_EX
|-
| 0xC084441C || Inout || 132 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SETTINGS
|-
| 0xC018441D || Inout || 24 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SERIAL_NUMBER
|-
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
|}
 
=== NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT ===
Uses [[#Ioctl3|Ioctl3]].


struct {
=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES ===
    __in u32 color_ds[4];
Uses [[#Ioctl3|Ioctl3]].
    __in u32 color_l2[4];
    __in u32 depth;
    __in u32 format;
    __in u32 type;        // 1=color, 2=depth
  };


=== NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE ===
=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES ===
Queries the active ZBC table. Identical to Linux driver.
Uses [[#Ioctl3|Ioctl3]].


struct {
=== NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS ===
    __out u32 color_ds[4];
Uses [[#Ioctl3|Ioctl3]].
    __out u32 color_l2[4];
    __out u32 depth;
    __out u32 ref_cnt;
    __out u32 format;
    __out u32 type;
    __inout u32 index_size;
  };


=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
=== NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS ===
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.
Uses [[#Ioctl2|Ioctl2]].


[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
== /dev/nvhost-prof-gpu ==
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.
 
This device is identical to [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]].


  struct gpu_characteristics {
== /dev/nvhost-ctrl-gpu ==
    u32 arch;                      // 0x120 (NVGPU_GPU_ARCH_GM200)
This device is for global (context independent) operations on the gpu. 
    u32 impl;                      // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
                                                                                                                                             
    u32 rev;                        // 0xA1 (Revision A1)
{| class="wikitable" border="1"
    u32 num_gpc;                    // 0x1
! Value || Direction || Size || Description
    u64 l2_cache_size;              // 0x40000
|-
    u64 on_board_video_memory_size; // 0x0 (not used)
| 0x80044701 || Out || 4 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE]]
    u32 num_tpc_per_gpc;            // 0x2
|-
    u32 bus_type;                  // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
| 0x80284702 || Out || 40 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_INFO]]
    u32 big_page_size;              // 0x20000
|-
    u32 compression_page_size;      // 0x20000
| 0x402C4703 || In || 44 || [[#NVGPU_GPU_IOCTL_ZBC_SET_TABLE]]
    u32 pde_coverage_bit_count;    // 0x1B
|-
    u32 available_big_page_sizes;  // 0x30000
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
    u32 gpc_mask;                  // 0x1
|-
    u32 sm_arch_sm_version;        // 0x503 (Maxwell Generation 5.0.3)
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
    u32 sm_arch_spa_version;        // 0x503 (Maxwell Generation 5.0.3)
|-
    u32 sm_arch_warp_count;        // 0x80
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
    u32 gpu_va_bit_count;          // 0x28
|-
    u32 reserved;                  // NULL
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
    u64 flags;                      // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
|-
    u32 twod_class;                // 0x902D (FERMI_TWOD_A)
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]
    u32 threed_class;              // 0xB197 (MAXWELL_B)
|-
    u32 compute_class;              // 0xB1C0 (MAXWELL_COMPUTE_B)
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
    u32 gpfifo_class;              // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
|-
    u32 inline_to_memory_class;    // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
    u32 dma_copy_class;            // 0xB0B5 (MAXWELL_DMA_COPY_A)
|-
    u32 max_fbps_count;            // 0x1
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
    u32 fbp_en_mask;                // 0x0 (disabled)
|-
    u32 max_ltc_per_fbp;            // 0x2
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
    u32 max_lts_per_ltc;            // 0x1
|-
    u32 max_tex_per_tpc;            // 0x0 (not supported)
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
    u32 max_gpc_count;              // 0x1
|-
    u32 rop_l2_en_mask_0;          // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
    u32 rop_l2_en_mask_1;          // 0x0
|-
    u64 chipname;                  // 0x6230326D67 ("gm20b")
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
    u64 gr_compbit_store_base_hw;  // 0x0 (not supported)
|-
  };
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
|-
  struct {
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
    __inout u64 gpu_characteristics_buf_size;  // must not be NULL, but gets overwritten with 0xA0=max_size
|-
    __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
    __out struct gpu_characteristics gc;
|-
  };
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
|-
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
|-
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
|-
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
|-
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
|-
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|}


=== NVGPU_GPU_IOCTL_GET_TPC_MASKS ===
=== NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE ===
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer.
Returns the GPU's ZCULL context size. Identical to Linux driver.


[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
struct {
 
     __out u32 size;
  struct {
     __in u32 mask_buf_size;      // ignored, but must not be NULL
    __in u32 reserved[3];
    __out u64 mask_buf;           // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
   };
   };


=== NVGPU_GPU_IOCTL_FLUSH_L2 ===
=== NVGPU_GPU_IOCTL_ZCULL_GET_INFO ===
Flushes the GPU L2 cache.
Returns GPU's ZCULL information. Identical to Linux driver.


  struct {
struct {
     __in u32 flush;         // l2_flush | l2_invalidate << 1 | fb_flush << 2
     __out u32 width_align_pixels;
     __in u32 reserved;
     __out u32 height_align_pixels;
    __out u32 pixel_squares_by_aliquots;
    __out u32 aliquot_total;
    __out u32 region_byte_multiplier;
    __out u32 region_header_size;
    __out u32 subregion_header_size;
    __out u32 subregion_width_align_pixels;
    __out u32 subregion_height_align_pixels;
    __out u32 subregion_count;
   };
   };


=== NVGPU_GPU_IOCTL_INVAL_ICACHE ===
=== NVGPU_GPU_IOCTL_ZBC_SET_TABLE ===
Invalidates the GPU instruction cache. Identical to Linux driver.
Sets the active ZBC table. Identical to Linux driver.


  struct {
struct {
     __in s32 channel_fd;
     __in u32 color_ds[4];
     __in u32 reserved;
    __in u32 color_l2[4];
    __in u32 depth;
    __in u32 format;
     __in u32 type;         // 1=color, 2=depth
   };
   };


=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE ===
=== NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE ===
Sets the GPU MMU debug mode. Identical to Linux driver.
Queries the active ZBC table. Identical to Linux driver.


  struct {
struct {
     __in u32 state;
     __out u32 color_ds[4];
     __in u32 reserved;
     __out u32 color_l2[4];
    __out u32 depth;
    __out u32 ref_cnt;
    __out u32 format;
    __out u32 type;
    __inout u32 index_size;
   };
   };


=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE ===
=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
Sets the GPU SM debug mode. Identical to Linux driver.
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.


  struct {
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
    __in s32 channel_fd;
    __in u32 enable;
    __in u64 sms;
  };


=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
  struct gpu_characteristics {
Waits until all valid warps on the GPU SM are paused and returns their current state.
    u32 arch;                      // 0x120 (NVGPU_GPU_ARCH_GM200)
 
    u32 impl;                      // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
  struct {
    u32 rev;                        // 0xA1 (Revision A1)
     __in u64 pwarpstate;
    u32 num_gpc;                    // 0x1
   };
    u64 l2_cache_size;              // 0x40000
 
     u64 on_board_video_memory_size; // 0x0 (not used)
[6.1.0+] This command was modified to return inline data instead of using a pointer.
    u32 num_tpc_per_gpc;            // 0x2
 
    u32 bus_type;                  // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
  struct {
    u32 big_page_size;              // 0x20000
     __out u64 sm0_valid_warps;
    u32 compression_page_size;      // 0x20000
     __out u64 sm0_trapped_warps;
    u32 pde_coverage_bit_count;     // 0x1B
     __out u64 sm0_paused_warps;
    u32 available_big_page_sizes;   // 0x30000
     __out u64 sm1_valid_warps;
    u32 gpc_mask;                   // 0x1
     __out u64 sm1_trapped_warps;
    u32 sm_arch_sm_version;        // 0x503 (Maxwell Generation 5.0.3)
     __out u64 sm1_paused_warps;
    u32 sm_arch_spa_version;        // 0x503 (Maxwell Generation 5.0.3)
    u32 sm_arch_warp_count;        // 0x80
    u32 gpu_va_bit_count;          // 0x28
    u32 reserved;                  // NULL
     u64 flags;                      // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
    u32 twod_class;                // 0x902D (FERMI_TWOD_A)
    u32 threed_class;              // 0xB197 (MAXWELL_B)
    u32 compute_class;              // 0xB1C0 (MAXWELL_COMPUTE_B)
    u32 gpfifo_class;              // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
    u32 inline_to_memory_class;    // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
    u32 dma_copy_class;            // 0xB0B5 (MAXWELL_DMA_COPY_A)
    u32 max_fbps_count;            // 0x1
    u32 fbp_en_mask;                // 0x0 (disabled)
    u32 max_ltc_per_fbp;            // 0x2
    u32 max_lts_per_ltc;            // 0x1
    u32 max_tex_per_tpc;           // 0x0 (not supported)
     u32 max_gpc_count;             // 0x1
     u32 rop_l2_en_mask_0;           // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
     u32 rop_l2_en_mask_1;           // 0x0
     u64 chipname;                   // 0x6230326D67 ("gm20b")
     u64 gr_compbit_store_base_hw;   // 0x0 (not supported)
   };
   };
 
=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
  struct {
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.
    __inout u64 gpu_characteristics_buf_size;  // must not be NULL, but gets overwritten with 0xA0=max_size
    __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
    __out struct gpu_characteristics gc;
  };
 
=== NVGPU_GPU_IOCTL_GET_TPC_MASKS ===
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer.
 
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].


   struct {
   struct {
     __out u64 tpc_exception_en_sm_mask;
    __in u32 mask_buf_size;      // ignored, but must not be NULL
    __in u32 reserved[3];
     __out u64 mask_buf;           // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
   };
   };


=== NVGPU_GPU_IOCTL_NUM_VSMS ===
=== NVGPU_GPU_IOCTL_FLUSH_L2 ===
Returns the number of GPU SM units present. Identical to Linux driver.
Flushes the GPU L2 cache.


   struct {
   struct {
     __out u32 num_vsms;
     __in u32 flush;         // l2_flush | l2_invalidate << 1 | fb_flush << 2
     __out u32 reserved;
     __in u32 reserved;
   };
   };


=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
=== NVGPU_GPU_IOCTL_INVAL_ICACHE ===
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.
Invalidates the GPU instruction cache. Identical to Linux driver.


   struct {
   struct {
     __out u8 sm0_gpc_index;
     __in s32 channel_fd;
     __out u8 sm0_tpc_index;
     __in u32 reserved;
    __out u8 sm1_gpc_index;
    __out u8 sm1_tpc_index;
   };
   };


=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE ===
Returns the mask value for a ZBC slot.
Sets the GPU MMU debug mode. Identical to Linux driver.


   struct {
   struct {
     __out u32 slot;       // always 0x07
     __in u32 state;
     __out u32 mask;
     __in u32 reserved;
   };
   };


=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE ===
Returns the GPU load value from the PMU.
Sets the GPU SM debug mode. Identical to Linux driver.


   struct {
   struct {
     __out u32 pmu_gpu_load;
     __in s32 channel_fd;
    __in u32 enable;
    __in u64 sms;
   };
   };


=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
Sets the clock gate control value.
Waits until all valid warps on the GPU SM are paused and returns their current state.


   struct {
   struct {
     __in u32 cg_mask;
     __in u64 pwarpstate;
    __in u32 cg_value;
   };
   };


=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
[6.1.0+] This command was modified to return inline data instead of using a pointer.
Returns the clock gate control value.


   struct {
   struct {
     __in u32 cg_mask;
     __out u64 sm0_valid_warps;
     __out u32 cg_value;
    __out u64 sm0_trapped_warps;
    __out u64 sm0_paused_warps;
    __out u64 sm1_valid_warps;
    __out u64 sm1_trapped_warps;
     __out u64 sm1_paused_warps;
   };
   };


=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
Sets the power gate control value.
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.


   struct {
   struct {
     __in u32 pg_mask;
     __out u64 tpc_exception_en_sm_mask;
    __in u32 pg_value;
   };
   };


=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
=== NVGPU_GPU_IOCTL_NUM_VSMS ===
Returns the power gate control value.
Returns the number of GPU SM units present. Identical to Linux driver.


   struct {
   struct {
     __in u32 pg_mask;
     __out u32 num_vsms;
     __out u32 pg_value;
     __out u32 reserved;
   };
   };


=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
Returns the GPU PMU ELPG residency gating values.
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.


   struct {
   struct {
     __out u64 pg_ingating_time_us;
     __out u8 sm0_gpc_index;
     __out u64 pg_ungating_time_us;
     __out u8 sm0_tpc_index;
     __out u64 pg_gating_cnt;
     __out u8 sm1_gpc_index;
    __out u8 sm1_tpc_index;
   };
   };


=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
Returns user specific data from the error channel, if one exists.
Returns the mask value for a ZBC slot.


   struct {
   struct {
     __out u64 data;
     __out u32 slot;      // always 0x07
    __out u32 mask;
   };
   };


=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.
Returns the GPU load value from the PMU.


   struct {
   struct {
     __out u64 gpu_timestamp;      // raw GPU counter (PTIMER) value
     __out u32 pmu_gpu_load;
    __out u64 reserved;
   };
   };


=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.
Sets the clock gate control value.


struct time_correlation_sample {
  struct {
  u64 cpu_timestamp;                                 // from CPU's CNTPCT_EL0 register
    __in u32 cg_mask;
  u64 gpu_timestamp;                                 // from GPU's PTIMER registers
    __in u32 cg_value;
};
  };
 
struct {
=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
  __out struct time_correlation_sample samples[16];  // timestamp pairs
Returns the clock gate control value.
  __in u32    count;                                // number of pairs to read
  __in u32    source_id;                            // cpu clock source id (must be 1)
};


= Channels =
  struct {
Channels are a concept for NVIDIA hardware blocks that share a common interface.
    __in u32 cg_mask;
    __out u32 cg_value;
  };


{| class="wikitable" border="1"
=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
! Path || Name
Sets the power gate control value.
|-
 
| /dev/nvhost-gpu || GPU
  struct {
|-
    __in u32 pg_mask;
| /dev/nvhost-msenc || Video Encoder
    __in u32 pg_value;
|-
  };
| /dev/nvhost-nvdec || Video Decoder
 
|-
=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
| /dev/nvhost-nvjpg || JPEG Decoder
Returns the power gate control value.
|-
| /dev/nvhost-vic || Video Image Compositor
|-
| /dev/nvhost-display || Display
|}


== Ioctls ==
  struct {
{| class="wikitable" border="1"
    __in u32 pg_mask;
! Value || Size || Description
    __out u32 pg_value;
|-
  };
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
 
|-
=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
Returns the GPU PMU ELPG residency gating values.
|-
 
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
  struct {
|-
    __out u64 pg_ingating_time_us;
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
    __out u64 pg_ungating_time_us;
|-
    __out u64 pg_gating_cnt;
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
  };
|-
 
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
|-
Returns user specific data from the error channel, if one exists.
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
 
|-
  struct {
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
    __out u64 data;
|-
  };
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
 
|-
=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.
|-
 
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
  struct {
|-
    __out u64 gpu_timestamp;      // raw GPU counter (PTIMER) value
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
    __out u64 reserved;
|-
  };
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
 
|- style="border-top: double"
=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.
|-
 
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
struct time_correlation_sample {
|-
  u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
  u64 gpu_timestamp;                                  // from GPU's PTIMER registers
|-
};
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
struct {
  __out struct time_correlation_sample samples[16];  // timestamp pairs
  __in u32    count;                                // number of pairs to read
  __in u32    source_id;                            // cpu clock source id (must be 1)
};
 
= Channels =
Channels are a concept for NVIDIA hardware blocks that share a common interface.
 
{| class="wikitable" border="1"
! Path || Name
|-
|-
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
| /dev/nvhost-gpu || GPU
|-
|-
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
| /dev/nvhost-msenc || Video Encoder
|-
|-
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
| /dev/nvhost-nvdec || Video Decoder
|-
|-
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
| /dev/nvhost-nvjpg || JPEG Decoder
|-
|-
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
| /dev/nvhost-vic || Video Image Compositor
|-
|-
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
| /dev/nvhost-display || Display
|-
|-
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
| /dev/nvhost-tsec || TSEC
|}
 
== Ioctls ==
{| class="wikitable" border="1"
! Value || Size || Description
|-
|-
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
|-
|-
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
|-
|-
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
|-
|-
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
|-
|-
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
|-
|-
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
|-
|-
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
|-
|-
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
|-
|-
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
|-
|-
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
|-
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
|-
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
|-
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
|- style="border-top: double"
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
|-
|-
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
|-
|-
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
|-
|-
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
|-
|-
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
|- style="border-top: double"
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
|-
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
|}
|-
 
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
|-
Submits data to the channel.
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
 
|-
  struct cmdbuf {
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
    u32 mem;
|-
    u32 offset;
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
    u32 words;
|-
  };
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
 
|-
  struct reloc {
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
    u32 cmdbuf_mem;
|-
    u32 cmdbuf_offset;
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
    u32 target;
|-
    u32 target_offset;
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
  };
|-
 
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
  struct reloc_shift {
|-
    u32 shift;
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
  };
|-
 
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
  struct syncpt_incr {
|-
    u32 syncpt_id;
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
    u32 syncpt_incrs;
|-
    u32 reserved[3];
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
  };
|-
 
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
  struct {
|-
    __in    u32 num_cmdbufs;
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
    __in    u32 num_relocs;
|-
    __in    u32 num_syncpt_incrs;
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
    __in    u32 num_fences;
|-
    __in    struct cmdbuf cmdbufs[];              // depends on num_cmdbufs
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
    __in    struct reloc relocs[];                // depends on num_relocs
|-
    __in    struct reloc_shift reloc_shifts[];    // depends on num_relocs
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
    __in    struct syncpt_incr syncpt_incrs[];    // depends on num_syncpt_incrs
|-
    __out  u32 fence_thresholds[];                // depends on num_fences
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
  };
|- style="border-top: double"
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|}


=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
Returns the current syncpoint value for a given module. Identical to Linux driver.
Submits data to the channel.


   struct {
   struct cmdbuf {
     __in    u32 module_id;
     u32 mem;
     __out  u32 syncpt_value;
     u32 offset;
    u32 words;
   };
   };
 
 
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
   struct reloc {
Returns the current waitbase value for a given module. Always returns 0.
     u32 cmdbuf_mem;
 
    u32 cmdbuf_offset;
   struct {
    u32 target;
     __in    u32 module_id;
     u32 target_offset;
     __out  u32 waitbase_value;
   };
   };
 
 
=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
  struct reloc_shift {
Stubbed. Does a debug print and returns 0.
    u32 shift;
 
  };
=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
 
Sets the submit timeout value for the channel. Identical to Linux driver.
  struct syncpt_incr {
 
    u32 syncpt_id;
   struct {
    u32 syncpt_incrs;
     __in    u32 timeout;
    u32 reserved[3];
  };
 
   struct {
     __in    u32 num_cmdbufs;
    __in    u32 num_relocs;
    __in    u32 num_syncpt_incrs;
    __in    u32 num_fences;
    __in    struct cmdbuf cmdbufs[];              // depends on num_cmdbufs
    __in    struct reloc relocs[];                // depends on num_relocs
    __in    struct reloc_shift reloc_shifts[];    // depends on num_relocs
    __in    struct syncpt_incr syncpt_incrs[];    // depends on num_syncpt_incrs
    __out  u32 fence_thresholds[];               // depends on num_fences
   };
   };


=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
Sets the clock rate value for a given module. Identical to Linux driver.
Returns the current syncpoint value for a given module. Identical to Linux driver.


   struct {
   struct {
    __in    u32 clk_rate;
     __in    u32 module_id;
     __in    u32 module_id;
    __out  u32 syncpt_value;
   };
   };


=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.
Returns the current waitbase value for a given module. Always returns 0.
 
  struct {
    __in    u32 module_id;
    __out  u32 waitbase_value;
  };
 
=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
Stubbed. Does a debug print and returns 0.
 
=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
Sets the submit timeout value for the channel. Identical to Linux driver.
 
  struct {
    __in    u32 timeout;
  };
 
=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
Sets the clock rate value for a given module. Identical to Linux driver.
 
  struct {
    __in    u32 clk_rate;
    __in    u32 module_id;
  };
 
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.


   struct handle {
   struct handle {
Line 1,970: Line 2,231:


   struct {
   struct {
     __out u32 error_info[32];   // first word is an error code (0=no_error, 1=mmu_error, 2=gr_error, 3=pbdma_error, 4=timeout)
     __out u32 type;     // Error type (0=no_error, 1=mmu_error, 2=gr_error, 3=pbdma_error, 4=timeout)
   };
    __out u32 info[31]; // Infor depends on the error type
   };  


=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
==== GR Error Code Format ====
Returns the current error notification caught by the error notifier. Exclusive to the Switch.
When <code>type == 2</code> (GR Error), the returned data is formatted as follows:
  struct {
    __out u32 type;      // 2=gr_error
    __out u32 intr_value; // Interrupt bits
    __out u32 addr;      // Register address (in bytes)
    __out u32 data_hi;    // Data high 32 bits
    __out u32 data_lo;    // Data low 32 bits
    __out u32 class_num;  // GPU class number (e.g., 0xb197 for MAXWELL_B)
  };


  struct {
{| class="wikitable"
    __out u64 timestamp;    // fetched straight from armGetSystemTick
|+ GR Error Interrupt Bits
    __out u32 info32;      // error code
|-
    __out u16 info16;      // additional error info
! Bit(s)
    __out u16 status;      // always 0xFFFF
! Description
  };
|-
 
| 0
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX ===
| GR_INTR_NOTIFY
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.
|-
 
| 1
struct fence {
| GR_INTR_SEMAPHORE
    u32 id;
|-
    u32 value;
| 2
};
| unknown
|-
struct {
| 3
  __in    u32 num_entries;
| unknown
  __in    u32 num_jobs;
|-
  __in    u32 flags;                      // bit0: vpr_enabled
| 4
  __out  struct fence fence_out;          // returned new fence object for others to wait on
| GR_INTR_ILLEGAL_METHOD
  __in    u32 reserved[3];                // ignored
|-
};
| 5
| GR_INTR_ILLEGAL_CLASS
|-
| 6
| GR_INTR_ILLEGAL_NOTIFY
|-
| 7
| unknown
|-
| 8
| GR_INTR_FIRMWARE_METHOD
|-
| 9–18
| unknown
|-
| 19
| GR_INTR_FECS_ERROR
|-
| 20
| GR_INTR_CLASS_ERROR
|-
| 21
| GR_INTR_EXCEPTION
|-
| 22–31
| unknown
|}


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY ===
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]].
Returns the current error notification caught by the error notifier. Exclusive to the Switch.


=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2 ===
  struct {
    __out u64 timestamp;    // fetched straight from armGetSystemTick
    __out u32 info32;      // error code
    __out u16 info16;      // additional error info
    __out u16 status;      // always 0xFFFF
  };
 
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX ===
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.
 
struct fence {
    u32 id;
    u32 value;
};
struct {
  __in    u32 num_entries;
  __in    u32 num_jobs;
  __in    u32 flags;                      // bit0: vpr_enabled
  __out  struct fence fence_out;          // returned new fence object for others to wait on
  __in    u32 reserved[3];                // ignored
};
 
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]].
 
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2 ===
Same as [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]].
Same as [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]].


Line 2,228: Line 2,550:
! Offset
! Offset
! Size
! Size
! Description
! Description
|-
|-
| 0x0
| 0x0
| 0x4
| 0x4
| FreeSize
| FreeSize
|-
|-
| 0x4
| 0x4
| 0x4
| 0x4
| AllocatableSize
| AllocatableSize
|-
|-
| 0x8
| 0x8
| 0x4
| 0x4
| MinimumFreeSize
| MinimumFreeSize
|-
|-
| 0xC
| 0xC
| 0x4
| 0x4
| MinimumAllocatableSize
| MinimumAllocatableSize
|-
|-
| 0x10
| 0x10
| 0x10
| 0x10
| Reserved
| Reserved
|}
|}
 
= Notes =
In some cases, a panic may occur. NV forces a crash by doing:
(void *)0 = 0xCAFE;
End result is that the system hangs with a white-screen.
 
When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done.


= Notes =
GPU rendering (GPFIFO) is only used by applets/Applications. All sysmodules doing any gfx-display uses software rendering. During system-boot, GPU GPFIFO is not used until the applets are launched.
In some cases, a panic may occur. NV forces a crash by doing:
(void *)0 = 0xCAFE;
End result is that the system hangs with a white-screen.
 
When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done.


[[Category:Services]]
[[Category:Services]]
Retrieved from "https://switchbrew.org/wiki/NV_services"