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NV services: Difference between revisions

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Line 16: Line 16:
! Cmd || Name
! Cmd || Name
|-
|-
| 0 || [[#Open]]
| 0 || [[#Open|Open]]
|-
|-
| 1 || [[#Ioctl]]
| 1 || [[#Ioctl|Ioctl]]
|-
|-
| 2 || [[#Close]]
| 2 || [[#Close|Close]]
|-
|-
| 3 || [[#Initialize]]
| 3 || [[#Initialize|Initialize]]
|-
|-
| 4 || [[#QueryEvent]]
| 4 || [[#QueryEvent|QueryEvent]]
|-
|-
| 5 || [[#MapSharedMem]]
| 5 || [[#MapSharedMem|MapSharedMem]]
|-
|-
| 6 || [[#GetStatus]]
| 6 || [[#GetStatus|GetStatus]]
|-
|-
| 7 || [[#SetAruidWithoutCheck]]
| 7 || [[#SetAruidWithoutCheck|SetAruidWithoutCheck]]
|-
|-
| 8 || [[#SetAruid]]
| 8 || [[#SetAruid|SetAruid]]
|-
|-
| 9 || [[#DumpStatus]]
| 9 || [[#DumpStatus|DumpStatus]]
|-
|-
| 10 || [3.0.0+] [[#InitializeDevtools]]
| 10 || [3.0.0+] [[#InitializeDevtools|InitializeDevtools]]
|-
|-
| 11 || [3.0.0+] [[#Ioctl2]]
| 11 || [3.0.0+] [[#Ioctl2|Ioctl2]]
|-
|-
| 12 || [3.0.0+] [[#Ioctl3]]
| 12 || [3.0.0+] [[#Ioctl3|Ioctl3]]
|-
|-
| 13 || [3.0.0+] [[#SetGraphicsFirmwareMemoryMarginEnabled]]
| 13 || [3.0.0+] [[#SetGraphicsFirmwareMemoryMarginEnabled|SetGraphicsFirmwareMemoryMarginEnabled]]
|}
|}


Line 64: Line 64:
Takes two input u32s '''Fd''' and '''EvtId'''. Returns an output u32 '''Err''' and an output Event handle.
Takes two input u32s '''Fd''' and '''EvtId'''. Returns an output u32 '''Err''' and an output Event handle.


QueryEvent is only supported on (and implemented differently on):
QueryEvent is only supported by:
* /dev/nvhost-gpu
* '''/dev/nvcec-ctrl'''
** EvtId=1: SmException_BptIntReport
** EvtId=0
** EvtId=2: SmException_BptPauseReport
** EvtId=1
** EvtId=2
** EvtId=3
** EvtId=4
** EvtId=5
** EvtId=6
** EvtId=7
** EvtId=8
** EvtId=9
 
* '''/dev/nvhdcp_up-ctrl'''
** EvtId=0: DphdcpStateEvent
 
* '''/dev/nvdisp-ctrl'''
** EvtId=0: HpdInEvent
** EvtId=1: HpdOutEvent
** EvtId=2: VblankHead0Event
 
* '''/dev/nvhost-gpu'''
** EvtId=1: BptIntEvent
** EvtId=2: BptPauseEvent
** EvtId=3: ErrorNotifierEvent
** EvtId=3: ErrorNotifierEvent
* /dev/nvhost-ctrl: Used to get events for syncpts.
 
** EvtId=(event_slot | ((syncpt_id & 0xFFF) << 16) | (is_valid << 28)): New format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]/[[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]].
* '''/dev/nvhost-ctrl'''
** EvtId=(event_slot | (syncpt_id << 4)): Old format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]].
** EvtId=(EventSlot | ((SyncptId & 0xFFF) << 16) | (IsValid << 28)): New format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]/[[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]].
* /dev/nvhost-ctrl-gpu
** EvtId=(EventSlot | (SyncptId << 4)): Old format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]].
** EvtId=1: Returns error_event_handle.
 
** EvtId=2: Returns unknown event.
* '''/dev/nvhost-ctrl-gpu'''
* /dev/nvhost-dbg-gpu
** EvtId=1: ErrorEvent
** Ignores EvtId.
** EvtId=2: SemaphoreEvent
 
* '''/dev/nvhost-dbg-gpu'''
** EvtId=Any: DbgEvents
 
* '''/dev/nvsched-ctrl'''
** EvtId=0: ApplicationAddedEvent
** EvtId=1: ApplicationUpdatedEvent
** EvtId=2: ApplicationMaxDebtUpdatedEvent
** EvtId=3: ApplicationRemovedEvent
** EvtId=4: ApplicationDetachedEvent
** EvtId=5: RunlistAddedEvent
** EvtId=6: RunlistUpdatedEvent
** EvtId=7: RunlistMaxDebtUpdatedEvent
** EvtId=8: RunlistLinkedEvent
** EvtId=9: RunlistUnlinkedEvent
** EvtId=10: RunlistRemovedEvent
** EvtId=11: ConductorSwapintervalUpdatedEvent
** EvtId=12: ChannelAcquiredEvent
** EvtId=13: ChannelReleasedEvent


== MapSharedMem ==
== MapSharedMem ==
Line 107: Line 146:


== SetGraphicsFirmwareMemoryMarginEnabled ==
== SetGraphicsFirmwareMemoryMarginEnabled ==
Unofficial name.
Takes an input u64. No output.
Takes an input u64. No output.


Line 140: Line 181:
! Cmd || Name
! Cmd || Name
|-
|-
| 0 || [[#DebugFSOpen]]
| 0 || [[#DebugFSOpen|DebugFSOpen]]
|-
|-
| 1 || [[#DebugFSClose]]
| 1 || [[#DebugFSClose|DebugFSClose]]
|-
|-
| 2 || [[#GetDebugFSKeys]]
| 2 || [[#GetDebugFSKeys|GetDebugFSKeys]]
|-
|-
| 3 || [[#GetDebugFSValue]]
| 3 || [[#GetDebugFSValue|GetDebugFSValue]]
|-
|-
| 4 || [[#SetDebugFSValue]]
| 4 || [[#SetDebugFSValue|SetDebugFSValue]]
|}
|}


Line 257: Line 298:


This service has no commands.
This service has no commands.
= (S2) INvDrv2User =
This is "nn::nvdrv::INvDrv2User".
{| class="wikitable" border="1"
|-
! Cmd || Name
|-
| 0 || Open
|-
| 1 || Ioctl
|-
| 2 || Close
|-
| 4 || QueryEvent
|-
| 9 || DumpStatus
|-
| 10 || InitializeDevtools
|-
| 11 || Ioctl2
|-
| 12 || Ioctl3
|-
| 13 || [[#SetConfiguration|SetConfiguration]]
|}
== SetConfiguration ==
Unofficial name.
Takes an input u64 '''Configuration'''. No output.
Bit 0 in '''Configuration''' represents the old '''GraphicsFirmwareMemoryMarginEnabled''' option.


= Ioctls =
= Ioctls =
Line 270: Line 344:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0xC0080014 || Inout || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_READ]]
| 0xC0080014 || Inout || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_READ|NVHOST_IOCTL_CTRL_SYNCPT_READ]]
|-
|-
| 0x40040015 || In || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_INCR]]
| 0x40040015 || In || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_INCR|NVHOST_IOCTL_CTRL_SYNCPT_INCR]]
|-
|-
| 0xC00C0016 || Inout || 12 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT]]
| 0xC00C0016 || Inout || 12 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT]]
|-
|-
| 0x40080017 || In || 8 || [[#NVHOST_IOCTL_CTRL_MODULE_MUTEX]]
| 0x40080017 || In || 8 || [[#NVHOST_IOCTL_CTRL_MODULE_MUTEX|NVHOST_IOCTL_CTRL_MODULE_MUTEX]]
|-
|-
| 0xC0180018 || Inout || 24 || [[#NVHOST_IOCTL_CTRL_MODULE_REGRDWR]]
| 0xC0180018 || Inout || 24 || [[#NVHOST_IOCTL_CTRL_MODULE_REGRDWR|NVHOST_IOCTL_CTRL_MODULE_REGRDWR]]
|-
|-
| 0xC0100019 || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]]
| 0xC0100019 || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]]
|-
|-
| 0xC008001A || Inout || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_READ_MAX]]
| 0xC008001A || Inout || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_READ_MAX|NVHOST_IOCTL_CTRL_SYNCPT_READ_MAX]]
|-
|-
| 0xC183001B || Inout || 387 || [[#NVHOST_IOCTL_CTRL_GET_CONFIG]]
| 0xC183001B || Inout || 387 || [[#NVHOST_IOCTL_CTRL_GET_CONFIG|NVHOST_IOCTL_CTRL_GET_CONFIG]]
|-
|-
| 0xC004001C || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT]]
| 0xC004001C || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT|NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT]]
|-
|-
| 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]
| 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]
|-
|-
| 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]]
| 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]]
|-
|-
| 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT]]
| 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT]]
|-
|-
| 0xC0040020 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT]]
| 0xC0040020 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT]]
|-
|-
| 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH]]
| 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH|NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH]]
|-
|-
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT|NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]
|}
|-
| 0xC0080027 || Inout || 8 || [S2] NVHOST_IOCTL_CTRL_ALLOC_SYNCPT
|-
| 0x40040028 || In || 4 || [S2] NVHOST_IOCTL_CTRL_FREE_SYNCPT
|-
| 0xC010002A || Inout || 16 || [S2] NVHOST_IOCTL_CTRL_GET_CHARACTERISTICS
|-
| 0xC008002B || Inout || 8 || [S2] NVHOST_IOCTL_CTRL_CHECK_MODULE_SUPPORT
|}


=== NVHOST_IOCTL_CTRL_SYNCPT_READ ===
=== NVHOST_IOCTL_CTRL_SYNCPT_READ ===
Line 421: Line 503:


=== NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT ===
=== NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT ===
Unofficial name.
Returns the syncpt shift value.
Returns the syncpt shift value.


Line 431: Line 515:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0xC0080101 || Inout || 8 || [[#NVMAP_IOC_CREATE]]
| 0xC0080101 || Inout || 8 || [[#NVMAP_IOC_CREATE|NVMAP_IOC_CREATE]]
|-
|-
| 0x00000102 || - || 0 || [[#NVMAP_IOC_CLAIM]]
| 0x00000102 || - || 0 || [[#NVMAP_IOC_CLAIM|NVMAP_IOC_CLAIM]]
|-
|-
| 0xC0080103 || Inout || 8 || [[#NVMAP_IOC_FROM_ID]]
| 0xC0080103 || Inout || 8 || [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]]
|-
|-
| 0xC0200104 || Inout || 32 || [[#NVMAP_IOC_ALLOC]]
| 0xC0200104 || Inout || 32 || [[#NVMAP_IOC_ALLOC|NVMAP_IOC_ALLOC]]
|-
|-
| 0xC0180105 || Inout || 24 || [[#NVMAP_IOC_FREE]]
| 0xC0180105 || Inout || 24 || [[#NVMAP_IOC_FREE|NVMAP_IOC_FREE]]
|-
|-
| 0xC0280106 || Inout || 40 || [[#NVMAP_IOC_MMAP]]
| 0xC0280106 || Inout || 40 || [[#NVMAP_IOC_MMAP|NVMAP_IOC_MMAP]]
|-
|-
| 0xC0280107 || Inout || 40 || [[#NVMAP_IOC_WRITE]]
| 0xC0280107 || Inout || 40 || [[#NVMAP_IOC_WRITE|NVMAP_IOC_WRITE]]
|-
|-
| 0xC0280108 || Inout || 40 || [[#NVMAP_IOC_READ]]
| 0xC0280108 || Inout || 40 || [[#NVMAP_IOC_READ|NVMAP_IOC_READ]]
|-
|-
| 0xC00C0109 || Inout || 12 || [[#NVMAP_IOC_PARAM]]
| 0xC00C0109 || Inout || 12 || [[#NVMAP_IOC_PARAM|NVMAP_IOC_PARAM]]
|-
|-
| 0xC010010A || Inout || 16 || [[#NVMAP_IOC_PIN_MULT]]
| 0xC010010A || Inout || 16 || [[#NVMAP_IOC_PIN_MULT|NVMAP_IOC_PIN_MULT]]
|-
|-
| 0xC010010B || Inout || 16 || [[#NVMAP_IOC_UNPIN_MULT]]
| 0xC010010B || Inout || 16 || [[#NVMAP_IOC_UNPIN_MULT|NVMAP_IOC_UNPIN_MULT]]
|-
|-
| 0xC008010C || Inout || 8 || [[#NVMAP_IOC_CACHE]]
| 0xC008010C || Inout || 8 || [[#NVMAP_IOC_CACHE|NVMAP_IOC_CACHE]]
|-
|-
| 0xC004010D || Inout || 4 || [[#NVMAP_IOC_GET_IVC_ID]]
| 0xC004010D || Inout || 4 || [[#NVMAP_IOC_GET_IVC_ID|NVMAP_IOC_GET_IVC_ID]]
|-
|-
| 0xC008010E || Inout || 8 || [[#NVMAP_IOC_GET_ID]]
| 0xC008010E || Inout || 8 || [[#NVMAP_IOC_GET_ID|NVMAP_IOC_GET_ID]]
|-
|-
| 0xC004010F || Inout || 4 || [[#NVMAP_IOC_FROM_IVC_ID]]
| 0xC004010F || Inout || 4 || [[#NVMAP_IOC_FROM_IVC_ID|NVMAP_IOC_FROM_IVC_ID]]
|-
|-
| 0x40040110 || In || 4 || [[#NVMAP_IOC_SET_ALLOCATION_TAG_LABEL]]
| 0x40040110 || In || 4 || [[#NVMAP_IOC_SET_ALLOCATION_TAG_LABEL|NVMAP_IOC_SET_ALLOCATION_TAG_LABEL]]
|-
|-
| 0x00000111 || - || 0 || [[#NVMAP_IOC_RESERVE]]
| 0x00000111 || - || 0 || [[#NVMAP_IOC_RESERVE|NVMAP_IOC_RESERVE]]
|-
|-
| 0x40100112 || In || 16 || [[#NVMAP_IOC_EXPORT_FOR_ARUID]]
| 0x40100112 || In || 16 || [[#NVMAP_IOC_EXPORT_FOR_ARUID|NVMAP_IOC_EXPORT_FOR_ARUID]]
|-
|-
| 0x40100113 || In || 16 || [[#NVMAP_IOC_IS_OWNED_BY_ARUID]]
| 0x40100113 || In || 16 || [[#NVMAP_IOC_IS_OWNED_BY_ARUID|NVMAP_IOC_IS_OWNED_BY_ARUID]]
|-
|-
| 0x40100114 || In || 16 || [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]]
| 0x40100114 || In || 16 || [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID|NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]]
|}
|}


Line 500: Line 584:
     __inout u32 align;
     __inout u32 align;
     __in u8  kind;
     __in u8  kind;
     u8       pad[7];
     __in u8 pad[7];
     __in u64 addr;
     __in u64 addr;
   };
   };
Line 509: Line 593:
   struct {
   struct {
     __in  u32 handle;
     __in  u32 handle;
     u32       pad;
     __in  u32 pad;
     __out u64 address;  // 0 if the handle wasn't yet freed
     __out u64 address;  // 0 if the handle wasn't yet freed
     __out u32 size;
     __out u32 size;
Line 568: Line 652:
     __in  u64 aruid;
     __in  u64 aruid;
     __in  u32 handle;
     __in  u32 handle;
     u8       pad[4];
     __in  u8 pad[4];
   };
   };


Line 577: Line 661:
     __in  u64 aruid;
     __in  u64 aruid;
     __in  u32 handle;
     __in  u32 handle;
     u8       pad[4];
     __in  u8 pad[4];
   };
   };


Line 586: Line 670:
     __in  u64 aruid;
     __in  u64 aruid;
     __in  u32 handle;
     __in  u32 handle;
     u8       pad[4];
     __in  u8 pad[4];
   };
   };


Line 593: Line 677:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0x80040212 || Out || 4 || NVDISP_CTRL_NUM_OUTPUTS
| 0x80040212 || Out || 4 || [[#NVDISP_CTRL_NUM_OUTPUTS|NVDISP_CTRL_NUM_OUTPUTS]]
|-
|-
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES
|-
|-
| 0xC1100214 || Inout || 272 || NVDISP_CTRL_QUERY_EDID
| 0xC2100214</br>([1.0.0-11.0.1] 0xC1100214) || Inout || 528</br>([1.0.0-11.0.1] 272) || NVDISP_CTRL_QUERY_EDID
|-
|-
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
|-
|-
| ([1.0.0-3.0.0] 0xC0040217) || ([1.0.0-3.0.0] Inout) || ([1.0.0-3.0.0] 4) || ([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_OUT_EVENT)
| 0xC0040217 || Inout || 4 || [1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_OUT_EVENT
|-
|-
| 0xC0100218 || Inout || 16 || NVDISP_CTRL_GET_VBLANK_HEAD0_EVENT
| 0xC0100218 || Inout || 16 || NVDISP_CTRL_GET_VBLANK_HEAD0_EVENT
Line 609: Line 693:
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND
|-
|-
| 0x80010224 || Out || 1 || [11.0.0+] NVDISP_CTRL_IS_DISPLAY_OLED
| 0x80010224 || Out || 1 || [11.0.0+] [[#NVDISP_CTRL_IS_DISPLAY_OLED|NVDISP_CTRL_IS_DISPLAY_OLED]]
|}
|}
=== NVDISP_CTRL_NUM_OUTPUTS ===
Returns the number of display outputs available.
  struct {
    __out u32 num_outputs;
  };
=== NVDISP_CTRL_IS_DISPLAY_OLED ===
Unofficial name.
This sets a boolean value based on the values of the system configuration.
Returns true if "nvservices!internal_display_vddpn_control" is set to false and "nvservices!external_display_full_dp_lanes" is set to true.
  struct {
    __out u8 is_display_oled;
  };


== /dev/nvdisp-disp0, /dev/nvdisp-disp1 ==
== /dev/nvdisp-disp0, /dev/nvdisp-disp1 ==
Line 622: Line 724:
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
|-
|-
| 0x80380204 || Out || 56 || NVDISP_GET_MODE
| 0x80380204 || Out || 56 || [[#NVDISP_GET_MODE|NVDISP_GET_MODE]]
|-
|-
| 0x40380205 || Out || 56 || NVDISP_SET_MODE
| 0x40380205 || In || 56 || [[#NVDISP_SET_MODE|NVDISP_SET_MODE]]
|-
|-
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
Line 634: Line 736:
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
|-
|-
| 0xC038020A || Inout || 56 || NVDISP_VALIDATE_MODE
| 0xC038020A || Inout || 56 || [[#NVDISP_VALIDATE_MODE|NVDISP_VALIDATE_MODE]]
|-
|-
| 0x4018020B || In || 24 || NVDISP_SET_CSC
| 0x4018020B || In || 24 || NVDISP_SET_CSC
Line 646: Line 748:
| 0xC004020F || Inout || 4 || NVDISP_DPMS
| 0xC004020F || Inout || 4 || NVDISP_DPMS
|-
|-
| 0x80600210 || Out || 96 || NVDISP_GET_AVI_INFOFRAME
| 0x80600210 || Out || 96 || [[#NVDISP_GET_AVI_INFOFRAME|NVDISP_GET_AVI_INFOFRAME]]
|-
|-
| 0x40600211 || In || 96 || NVDISP_SET_AVI_INFOFRAME
| 0x40600211 || In || 96 || [[#NVDISP_SET_AVI_INFOFRAME|NVDISP_SET_AVI_INFOFRAME]]
|-
|-
| 0xEBFC0215 || Inout || 11260 || NVDISP_GET_MODE_DB
| 0xEBFC0215 || Inout || 11260 || [[#NVDISP_GET_MODE_DB|NVDISP_GET_MODE_DB]]
|-
|-
| 0xC003021A || Inout || 3 || NVDISP_PANEL_GET_VENDOR_ID
| 0xC003021A || Inout || 3 || [[#NVDISP_PANEL_GET_VENDOR_ID|NVDISP_PANEL_GET_VENDOR_ID]]
|-
|-
| 0x803C021B || Out || 60 || NVDISP_GET_MODE2
| 0x803C021B || Out || 60 || [[#NVDISP_GET_MODE2|NVDISP_GET_MODE2]]
|-
|-
| 0x403C021C || In || 60 || NVDISP_SET_MODE2
| 0x403C021C || In || 60 || [[#NVDISP_SET_MODE2|NVDISP_SET_MODE2]]
|-
|-
| 0xC03C021D || Inout || 60 || NVDISP_VALIDATE_MODE2
| 0xC03C021D || Inout || 60 || [[#NVDISP_VALIDATE_MODE2|NVDISP_VALIDATE_MODE2]]
|-
|-
| 0xEF20021E || Inout || 12064 || NVDISP_GET_MODE_DB2
| 0xEF20021E || Inout || 12064 || [[#NVDISP_GET_MODE_DB2|NVDISP_GET_MODE_DB2]]
|-
|-
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
|-
|-
| 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE]]
| 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE|NVDISP_GET_BACKLIGHT_RANGE]]
|-
|-
| 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MAX]]
| 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MAX|NVDISP_SET_BACKLIGHT_RANGE_MAX]]
|-
|-
| 0x40040223 || In || 4 || [11.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MIN]]
| 0x40040223 || In || 4 || [11.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MIN|NVDISP_SET_BACKLIGHT_RANGE_MIN]]
|-
|-
| 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG]]
| 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG|NVDISP_SEND_PANEL_MSG]]
|-
|-
| 0xC01C0226 || Inout || 28 || [11.0.0+] [[#NVDISP_GET_PANEL_DATA]]
| 0xC01C0226 || Inout || 28 || [11.0.0+] [[#NVDISP_GET_PANEL_DATA|NVDISP_GET_PANEL_DATA]]
|}
|}


=== NVDISP_GET_BACKLIGHT_RANGE ===
=== NVDISP_GET_MODE ===
Returns the minimum and maximum values for the intensity of the display's backlight.
Almost identical to Linux driver.


   struct {
   struct {
     __out u32 min;
     __out u32 hActive;
     __out u32 max;
     __out u32 vActive;
    __out u32 hSyncWidth;
    __out u32 vSyncWidth;
    __out u32 hFrontPorch;
    __out u32 vFrontPorch;
    __out u32 hBackPorch;
    __out u32 vBackPorch;
    __out u32 hRefToSync;
    __out u32 vRefToSync;
    __out u32 pclkKHz;
    __out u32 bitsPerPixel;      // Always 0
    __out u32 vmode;            // Always 0
    __out u32 sync;
   };
   };


=== NVDISP_SET_BACKLIGHT_RANGE_MAX ===
=== NVDISP_SET_MODE ===
Sets the maximum value for the intensity of the display's backlight.
Almost identical to Linux driver.


   struct {
   struct {
     __in u32 max;
     __in u32 hActive;
    __in u32 vActive;
    __in u32 hSyncWidth;
    __in u32 vSyncWidth;
    __in u32 hFrontPorch;
    __in u32 vFrontPorch;
    __in u32 hBackPorch;
    __in u32 vBackPorch;
    __in u32 hRefToSync;
    __in u32 vRefToSync;
    __in u32 pclkKHz;
    __in u32 bitsPerPixel;
    __in u32 vmode;
    __in u32 sync;
   };
   };


=== NVDISP_SET_BACKLIGHT_RANGE_MIN ===
=== NVDISP_VALIDATE_MODE ===
Sets the minimum value for the intensity of the display's backlight.
Almost identical to Linux driver.


   struct {
   struct {
     __in u32 min;
     __inout u32 hActive;
    __inout u32 vActive;
    __inout u32 hSyncWidth;
    __inout u32 vSyncWidth;
    __inout u32 hFrontPorch;
    __inout u32 vFrontPorch;
    __inout u32 hBackPorch;
    __inout u32 vBackPorch;
    __inout u32 hRefToSync;
    __inout u32 vRefToSync;
    __inout u32 pclkKHz;
    __inout u32 bitsPerPixel;
    __inout u32 vmode;
    __inout u32 sync;
   };
   };


=== NVDISP_SEND_PANEL_MSG ===
=== NVDISP_GET_AVI_INFOFRAME ===
Sends raw data to the display panel over DPAUX.
Unpacked standard AVI infoframe struct (HDMI v1.4b/2.0)


   struct {
   struct {
     __in u32 cmd;         // DPAUX AUXCTL command (1=unk, 2=I2CWR, 4=MOTWR, 7=AUXWR)
     __out u32 csum;
     __in u32 addr;         // DPAUX AUXADDR
    __out u32 scan;
     __in u32 size;         // message size
    __out u32 bar_valid;
     __in u32 msg[4];       // raw AUXDATA message
    __out u32 act_fmt_valid;
    __out u32 rgb_ycc;
    __out u32 act_format;
    __out u32 aspect_ratio;
    __out u32 colorimetry;
    __out u32 scaling;
    __out u32 rgb_quant;
    __out u32 ext_colorimetry;
    __out u32 it_content;
    __out u32 video_format;
    __out u32 pix_rep;
    __out u32 it_content_type;
    __out u32 ycc_quant;
    __out u32 top_bar_end_line_lsb;
    __out u32 top_bar_end_line_msb;
    __out u32 bot_bar_start_line_lsb;
    __out u32 bot_bar_start_line_msb;
    __out u32 left_bar_end_pixel_lsb;
    __out u32 left_bar_end_pixel_msb;
    __out u32 right_bar_start_pixel_lsb;
    __out u32 right_bar_start_pixel_msb;
  };
 
=== NVDISP_SET_AVI_INFOFRAME ===
Unpacked standard AVI infoframe struct (HDMI v1.4b/2.0)
 
  struct {
    __in u32 csum;
    __in u32 scan;
    __in u32 bar_valid;
    __in u32 act_fmt_valid;
    __in u32 rgb_ycc;
    __in u32 act_format;
    __in u32 aspect_ratio;
    __in u32 colorimetry;
    __in u32 scaling;
    __in u32 rgb_quant;
    __in u32 ext_colorimetry;
    __in u32 it_content;
    __in u32 video_format;
    __in u32 pix_rep;
    __in u32 it_content_type;
    __in u32 ycc_quant;
     __in u32 top_bar_end_line_lsb;
    __in u32 top_bar_end_line_msb;
    __in u32 bot_bar_start_line_lsb;
    __in u32 bot_bar_start_line_msb;
    __in u32 left_bar_end_pixel_lsb;
    __in u32 left_bar_end_pixel_msb;
     __in u32 right_bar_start_pixel_lsb;
     __in u32 right_bar_start_pixel_msb;
   };
   };


=== NVDISP_GET_PANEL_DATA ===
=== NVDISP_GET_MODE_DB ===
Receives raw data from the display panel over DPAUX.
Almost identical to Linux driver.


  struct mode {
    u32 hActive;
    u32 vActive;
    u32 hSyncWidth;
    u32 vSyncWidth;
    u32 hFrontPorch;
    u32 vFrontPorch;
    u32 hBackPorch;
    u32 vBackPorch;
    u32 hRefToSync;
    u32 vRefToSync;
    u32 pclkKHz;
    u32 bitsPerPixel;
    u32 vmode;
    u32 sync;
  };
   struct {
   struct {
     __in u32 cmd;          // DPAUX AUXCTL command (3=I2CRD, 5=MOTRD, 6=AUXRD)
     __out struct mode modes[201];
    __in u32 addr;         // DPAUX AUXADDR
     __out u32 num_modes;
    __in u32 size;        // message size
     __out u32 msg[4];     // raw AUXDATA message
   };
   };


== /dev/nvcec-ctrl ==
=== NVDISP_PANEL_GET_VENDOR_ID ===
{| class="wikitable" border="1"
Returns display panel's informations.
! Value || Direction || Size || Description
|-
| 0x40010301 || In || 1 || NVCEC_CTRL_ENABLE
|-
| 0x804C0302 || Out || 76 || NVCEC_CTRL_GET_PADDR
|-
| 0x40040303 || In || 4 || NVCEC_CTRL_SET_LADDR
|-
| 0xC04C0304 || Inout || 76 || NVCEC_CTRL_WRITE
|-
| 0xC04C0305 || Inout || 76 || NVCEC_CTRL_READ
|-
| 0x804C0306 || Out || 76 || NVCEC_CTRL_GET_CONNECTION_STATUS
|-
| 0x804C0307 || Out || 76 || NVCEC_CTRL_GET_WRITE_STATUS
|}


== /dev/nvhdcp_up-ctrl ==
  struct {
{| class="wikitable" border="1"
    __out u8 vendor; //0x10 - JDI, 0x20 - InnoLux, 0x30 - AUO, 0x40 - Sharp, 0x50 - Samsung
! Value || Direction || Size || Description
    __out u8 model;
|-
    __out u8 board; //0xF - 6.2", 0x10 - 5.5", 0x20 - 7.0". JDI panels have nonstandard values
| 0xC4880401 || Inout || 1160 || NVHDCP_READ_STATUS
  };
|-
 
| 0xC4880402 || Inout || 1160 || NVHDCP_READ_M
=== NVDISP_GET_MODE2 ===
|-
 
| 0x40010403 || In || 1 || NVHDCP_ENABLE
  struct {
|-
    __out u32 unk0;              //Always 0
| 0xC0080404 || Inout || 8 || NVHDCP_CTRL_STATE_TRANSIT_EVENT_DATA
    __out u32 hActive;
|-
    __out u32 vActive;
| 0xC0010405 || Inout || 1 || NVHDCP_CTRL_STATE_CB
    __out u32 hSyncWidth;
|}
    __out u32 vSyncWidth;
    __out u32 hFrontPorch;
    __out u32 vFrontPorch;
    __out u32 hBackPorch;
    __out u32 vBackPorch;
    __out u32 pclkKHz;
    __out u32 bitsPerPixel;      // Always 0
    __out u32 vmode;            // Always 0
    __out u32 sync;
    __out u32 unk1;
    __out u32 reserved;
  };
 
=== NVDISP_SET_MODE2 ===


== /dev/nvdcutil-disp0, /dev/nvdcutil-disp1 ==
  struct {
{| class="wikitable" border="1"
    __in u32 unk0;
! Value || Direction || Size || Description
    __in u32 hActive;
|-
    __in u32 vActive;
| 0x40010501 || In || 1 || NVDCUTIL_ENABLE_CRC
    __in u32 hSyncWidth;
|-
    __in u32 vSyncWidth;
| 0x40010502 || In || 1 || NVDCUTIL_VIRTUAL_EDID_ENABLE
    __in u32 hFrontPorch;
|-
    __in u32 vFrontPorch;
| 0x42040503 || In || 1056 || NVDCUTIL_VIRTUAL_EDID_SET_DATA
    __in u32 hBackPorch;
|-
    __in u32 vBackPorch;
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
    __in u32 pclkKHz;
|-
    __in u32 bitsPerPixel;
| 0x40010505 || In || 1 || NVDCUTIL_BEGIN_TELEMETRY_TEST
    __in u32 vmode;
|-
    __in u32 sync;
| 0x400C0506 || In || 12 || NVDCUTIL_DSI_PACKET_TEST_SHORT_WRITE
    __in u32 unk1;
|-
    __in u32 reserved;
| 0x40F80507 || In || 248 || NVDCUTIL_DSI_PACKET_TEST_LONG_WRITE
  };
|-
 
| 0xC0F40508 || Inout || 244 || NVDCUTIL_DSI_PACKET_TEST_READ
=== NVDISP_VALIDATE_MODE2 ===
|-
| 0x40010509 || In || 1 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_EN
|-
| 0xC020050A || Inout || 32 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_SETTINGS
|-
| 0x8070050B || Out || 112 || [11.0.0+] NVDCUTIL_DP_CONF_READ
|}


== /dev/nvsched-ctrl ==
  struct {
This is a customized scheduler device.
    __inout u32 unk0;
    __inout u32 hActive;
    __inout u32 vActive;
    __inout u32 hSyncWidth;
    __inout u32 vSyncWidth;
    __inout u32 hFrontPorch;
    __inout u32 vFrontPorch;
    __inout u32 hBackPorch;
    __inout u32 vBackPorch;
    __inout u32 pclkKHz;
    __inout u32 bitsPerPixel;
    __inout u32 vmode;
    __inout u32 sync;
    __inout u32 unk1;
    __inout u32 reserved;
  };


The way this device is exposed and configured is exclusive to the Switch, since other sources don't have an actual interface for the scheduler.
=== NVDISP_GET_MODE_DB2 ===


{| class="wikitable" border="1"
  struct mode2 {
! Value || Direction || Size || Description
    u32 unk0;
|-
    u32 hActive;
| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE]]
    u32 vActive;
|-
    u32 hSyncWidth;
| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE]]
    u32 vSyncWidth;
|-
    u32 hFrontPorch;
| 0x40180603 || In || 24 || [[#NVSCHED_CTRL_ADD_APPLICATION]]
    u32 vFrontPorch;
|-
    u32 hBackPorch;
| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION]]
    u32 vBackPorch;
|-
    u32 pclkKHz;
| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION]]
    u32 bitsPerPixel;
|-
    u32 vmode;
| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID]]
    u32 sync;
|-
    u32 unk1;
| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST]]
    u32 reserved;
|-
  };
| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST]]
|-
  struct {
| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST]]
    __out struct mode2 modes[201];
|-
    __out u32 num_modes;
| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST]]
  };
|-
| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST]]
|-
| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]]
|-
| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]
|-
| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]
|-
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]
|-
| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT
|-
| 0x40100611 || In || 16 || NVSCHED_CTRL_SET_RUNLIST_MAX_DEBT
|-
| 0x40010612 || In || 1 || NVSCHED_CTRL_OVERRUN_EVENTS_ENABLE
|}


=== NVSCHED_CTRL_ENABLE ===
=== NVDISP_GET_BACKLIGHT_RANGE ===
Enables the scheduler.
Unofficial name.


=== NVSCHED_CTRL_DISABLE ===
Returns the minimum and maximum values for the intensity of the display's backlight.
Disables the scheduler.


=== NVSCHED_CTRL_ADD_APPLICATION ===
  struct {
Adds a new application to the scheduler.
    __out u32 min;
    __out u32 max;
  };


  struct {
=== NVDISP_SET_BACKLIGHT_RANGE_MAX ===
    __in u64 application_id;
Unofficial name.
    __in u64 priority;
    __in u64 timeslice;
  };


=== NVSCHED_CTRL_UPDATE_APPLICATION ===
Sets the maximum value for the intensity of the display's backlight.
Updates the application parameters in the scheduler.


   struct {
   struct {
     __in u64 application_id;
     __in u32 max;
    __in u64 priority;
    __in u64 timeslice;
   };
   };


=== NVSCHED_CTRL_REMOVE_APPLICATION ===
=== NVDISP_SET_BACKLIGHT_RANGE_MIN ===
Removes the application from the scheduler.
Unofficial name.
 
Sets the minimum value for the intensity of the display's backlight.


   struct {
   struct {
     __in u64 application_id;
     __in u32 min;
   };
   };


=== NVSCHED_CTRL_GET_ID ===
=== NVDISP_SEND_PANEL_MSG ===
Returns the ID of the last scheduled object.
Unofficial name.


  struct {
Sends raw data to the display panel over DPAUX.
    __out u64 id;
  };
 
=== NVSCHED_CTRL_ADD_RUNLIST ===
Creates a new runlist and returns it's ID.


   struct {
   struct {
     __out u64 runlist_id;
     __in u32 cmd;         // DPAUX AUXCTL command (1=unk, 2=I2CWR, 4=MOTWR, 7=AUXWR)
    __in u32 addr;        // DPAUX AUXADDR
    __in u32 size;        // message size
    __in u32 msg[4];      // raw AUXDATA message
   };
   };


=== NVSCHED_CTRL_UPDATE_RUNLIST ===
=== NVDISP_GET_PANEL_DATA ===
Updates the runlist parameters in the scheduler.
Unofficial name.


  struct {
Receives raw data from the display panel over DPAUX.
    __in u64 runlist_id;
    __in u64 priority;
    __in u64 timeslice;
  };
 
=== NVSCHED_CTRL_LINK_RUNLIST ===
Links a runlist to a given application in the scheduler.


   struct {
   struct {
     __in u64 runlist_id;
     __in u32 cmd;         // DPAUX AUXCTL command (3=I2CRD, 5=MOTRD, 6=AUXRD)
     __in u64 application_id;
     __in u32 addr;         // DPAUX AUXADDR
    __in u32 size;        // message size
    __out u32 msg[4];      // raw AUXDATA message
   };
   };


=== NVSCHED_CTRL_UNLINK_RUNLIST ===
== /dev/nvcec-ctrl ==
Unlinks a runlist from a given application in the scheduler.
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0x40010301 || In || 1 || NVCEC_CTRL_ENABLE
|-
| 0x804C0302 || Out || 76 || NVCEC_CTRL_GET_PADDR
|-
| 0x40040303 || In || 4 || NVCEC_CTRL_SET_LADDR
|-
| 0xC04C0304 || Inout || 76 || NVCEC_CTRL_WRITE
|-
| 0xC04C0305 || Inout || 76 || NVCEC_CTRL_READ
|-
| 0x804C0306 || Out || 76 || NVCEC_CTRL_GET_CONNECTION_STATUS
|-
| 0x804C0307 || Out || 76 || NVCEC_CTRL_GET_WRITE_STATUS
|}


  struct {
== /dev/nvhdcp_up-ctrl ==
    __in u64 runlist_id;
{| class="wikitable" border="1"
    __in u64 application_id;
! Value || Direction || Size || Description
  };
|-
 
| 0xC4880401 || Inout || 1160 || NVHDCP_READ_STATUS
=== NVSCHED_CTRL_REMOVE_RUNLIST ===
|-
Removes the runlist from the scheduler.
| 0xC4880402 || Inout || 1160 || NVHDCP_READ_M
|-
| 0x40010403 || In || 1 || NVHDCP_ENABLE
|-
| 0xC0080404 || Inout || 8 || NVHDCP_CTRL_STATE_TRANSIT_EVENT_DATA
|-
| 0xC0010405 || Inout || 1 || NVHDCP_CTRL_STATE_CB
|}


  struct {
== /dev/nvdcutil-disp0, /dev/nvdcutil-disp1 ==
    __in u64 runlist_id;
{| class="wikitable" border="1"
  };
! Value || Direction || Size || Description
 
|-
=== NVSCHED_CTRL_HAS_OVERRUN_EVENT ===
| 0x40010501 || In || 1 || NVDCUTIL_ENABLE_CRC
Returns a boolean to tell if the scheduler has an overrun event or not.
|-
 
| 0x40010502 || In || 1 || [[#NVDCUTIL_VIRTUAL_EDID_ENABLE|NVDCUTIL_VIRTUAL_EDID_ENABLE]]
  struct {
|-
    __out u8 has_overrun;
| 0x42040503 || In || 516 || [[#NVDCUTIL_VIRTUAL_EDID_SET_DATA|NVDCUTIL_VIRTUAL_EDID_SET_DATA]]
  };
|-
 
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
=== NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT ===
|-
Returns the overrun event's data from the scheduler.
| 0x40010505 || In || 1 || NVDCUTIL_BEGIN_TELEMETRY_TEST
|-
| 0x400C0506 || In || 12 || NVDCUTIL_DSI_PACKET_TEST_SHORT_WRITE
|-
| 0x40F80507 || In || 248 || NVDCUTIL_DSI_PACKET_TEST_LONG_WRITE
|-
| 0xC0F40508 || Inout || 244 || NVDCUTIL_DSI_PACKET_TEST_READ
|-
| 0x40010509 || In || 1 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_EN
|-
| 0xC020050A || Inout || 32 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_SETTINGS
|-
| 0x8070050B || Out || 112 || [11.0.0+] NVDCUTIL_DP_CONF_READ
|}
 
=== NVDCUTIL_VIRTUAL_EDID_ENABLE ===
Enables virtual EDID.


   struct {
   struct {
     __out u64 runlist_id;
     __in u8 enable;
    __out u64 debt;
    __out u64 unk0;          // 3.0.0+ only
    __out u64 unk1;          // 3.0.0+ only
   };
   };


=== NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE ===
=== NVDCUTIL_VIRTUAL_EDID_SET_DATA ===
Installs a fence swap event?
Sets virtual EDID data.


   struct {
   struct {
     __in u32 fence_id;
     __in u8 edid[512];
    __in u32 fence_value;
     __in u32 edid_size;
     __in u32 swap_interval;
   };
   };


=== NVSCHED_CTRL_DETACH_APPLICATION ===
== /dev/nvsched-ctrl ==
Places the given application in detached state.
This is a customized scheduler device.


  struct {
The way this device is exposed and configured is exclusive to the Switch, since other sources don't have an actual interface for the scheduler.
    __in u64 application_id;
  };
 
== /dev/nverpt-ctrl ==
Added in firmware version 3.0.0.


{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA]]
| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE|NVSCHED_CTRL_ENABLE]]
|-
| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE|NVSCHED_CTRL_DISABLE]]
|-
| 0x40180603 || In || 24 || [[#NVSCHED_CTRL_ADD_APPLICATION|NVSCHED_CTRL_ADD_APPLICATION]]
|-
| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION|NVSCHED_CTRL_UPDATE_APPLICATION]]
|-
| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION|NVSCHED_CTRL_REMOVE_APPLICATION]]
|-
| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID|NVSCHED_CTRL_GET_ID]]
|-
| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST|NVSCHED_CTRL_ADD_RUNLIST]]
|-
| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST|NVSCHED_CTRL_UPDATE_RUNLIST]]
|-
| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST|NVSCHED_CTRL_LINK_RUNLIST]]
|-
| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST|NVSCHED_CTRL_UNLINK_RUNLIST]]
|-
| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST|NVSCHED_CTRL_REMOVE_RUNLIST]]
|-
|-
| 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]]
| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT|NVSCHED_CTRL_HAS_OVERRUN_EVENT]]
|-
| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT|NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]
|-
| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE|NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]
|-
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION|NVSCHED_CTRL_DETACH_APPLICATION]]
|-
| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT
|-
| 0x40100611 || In || 16 || NVSCHED_CTRL_SET_RUNLIST_MAX_DEBT
|-
| 0x40010612 || In || 1 || NVSCHED_CTRL_OVERRUN_EVENTS_ENABLE
|}
|}


=== NVERPT_TELEMETRY_SUBMIT_DATA ===
=== NVSCHED_CTRL_ENABLE ===
Sends test data for creating a new [[Error_Report_services|Error Report]].
Enables the scheduler.


  struct {
=== NVSCHED_CTRL_DISABLE ===
    __in u64 TestU64;
Disables the scheduler.
    __in u32 TestU32;
    __in u8  padding0[4];
    __in s64 TestI64;
    __in s32 TestI32;
    __in u8  TestString[32];
    __in u8  TestU8Array[8];
    __in u32 TestU8Array_size;
    __in u32 TestU32Array[8];
    __in u32 TestU32Array_size;
    __in u64 TestU64Array[8];
    __in u32 TestU64Array_size;
    __in s32 TestI32Array[8];
    __in u32 TestI32Array_size;
    __in s64 TestI64Array[8];
    __in u32 TestI64Array_size;
    __in u16 TestU16;
    __in u8  TestU8;
    __in s16 TestI16;
    __in s8  TestI8;
    __in u8  padding1[5];
  };


=== NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA ===
=== NVSCHED_CTRL_ADD_APPLICATION ===
Sends display data for creating a new [[Error_Report_services|Error Report]].
Adds a new application to the scheduler.


   struct {
   struct {
     __in u32 CodecType;
     __in u64 application_id;
     __in u32 DecodeBuffers;
     __in u64 priority;
     __in u32 FrameWidth;
     __in u64 timeslice;
    __in u32 FrameHeight;
    __in u8  ColorPrimaries;
    __in u8  TransferCharacteristics;
    __in u8  MatrixCoefficients;
    __in u8  padding;
    __in u32 DisplayWidth;
    __in u32 DisplayHeight;
    __in u32 DARWidth;
    __in u32 DARHeight;
    __in u32 ColorFormat;
    __in u32 ColorSpace[8];
    __in u32 ColorSpace_size;
    __in u32 SurfaceLayout[8];
    __in u32 SurfaceLayout_size;
    __in u8  ErrorString[64];      // must be "Error detected = 0x1000000"
    __in u32 VideoDecState;
    __in u8  VideoLog[3712];
    __in u32 VideoLog_size;
   };
   };


== /dev/nvhost-as-gpu ==
=== NVSCHED_CTRL_UPDATE_APPLICATION ===
Each fd opened to this device creates an address space. An address space is then later bound with a channel.
Updates the application parameters in the scheduler.


Once a nvgpu channel has been bound to an address space it cannot be unbound. There is no support for allowing an nvgpu channel to change from one address space to another (or from one to none).
  struct {
                                                                                                                             
    __in u64 application_id;
{| class="wikitable" border="1"
    __in u64 priority;
! Value || Direction || Size || Description
    __in u64 timeslice;
|-
  };
| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL]]
|-
| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE]]
|-
| 0xC0104103 || Inout || 16 || [[#NVGPU_AS_IOCTL_FREE_SPACE]]
|-
| 0xC0184104 || Inout || 24 || [[#NVGPU_AS_IOCTL_MAP_BUFFER]]
|-
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
|-
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
|-
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]
|-
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS]]
|-
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
|}


=== NVGPU_AS_IOCTL_BIND_CHANNEL ===
=== NVSCHED_CTRL_REMOVE_APPLICATION ===
Identical to Linux driver.
Removes the application from the scheduler.


   struct {
   struct {
     __in u32 channel_fd;
     __in u64 application_id;
   };
   };


=== NVGPU_AS_IOCTL_ALLOC_SPACE ===
=== NVSCHED_CTRL_GET_ID ===
Reserves pages in the device address space.
Returns the ID of the last scheduled object.


   struct {
   struct {
     __in u32 pages;
     __out u64 id;
    __in u32 page_size;
    __in u32 flags;
    u32      padding;
    union {
      __out u64 offset;
      __in  u64 align;
    };
   };
   };


=== NVGPU_AS_IOCTL_FREE_SPACE ===
=== NVSCHED_CTRL_ADD_RUNLIST ===
Frees pages from the device address space.
Creates a new runlist and returns it's ID.


   struct {
   struct {
     __in u64 offset;
     __out u64 runlist_id;
    __in u32 pages;
    __in u32 page_size;
   };
   };


=== NVGPU_AS_IOCTL_MAP_BUFFER ===
=== NVSCHED_CTRL_UPDATE_RUNLIST ===
Maps a memory region in the device address space.
Updates the runlist parameters in the scheduler.


Unaligned size will cause a [[#Panic]].
  struct {
    __in u64 runlist_id;
    __in u64 priority;
    __in u64 timeslice;
  };


On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
=== NVSCHED_CTRL_LINK_RUNLIST ===
Links a runlist to a given application in the scheduler.


   struct {
   struct {
     __in   u32 flags;        // bit0: fixed_offset, bit2: cacheable
     __in u64 runlist_id;
    u32        reserved0;
     __in u64 application_id;
    __in    u32 mem_id;      // nvmap handle
    u32        reserved1;
     union {
      __out u64 offset;
      __in u64 align;
    };
   };
   };


=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
=== NVSCHED_CTRL_UNLINK_RUNLIST ===
Maps a memory region in the device address space with extra params.
Unlinks a runlist from a given application in the scheduler.


Unaligned size will cause a [[#Panic]].
  struct {
    __in u64 runlist_id;
    __in u64 application_id;
  };


On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
=== NVSCHED_CTRL_REMOVE_RUNLIST ===
Removes the runlist from the scheduler.


   struct {
   struct {
     __in     u32 flags;          // bit0: fixed_offset, bit2: cacheable
     __in u64 runlist_id;
    __inout  u32 kind;          // -1 is default
    __in      u32 mem_id;        // nvmap handle
    u32          reserved;
    __in      u64 buffer_offset;
    __in      u64 mapping_size;
    union {
      __out  u64 offset;
      __in    u64 align;
    };
   };
   };


=== NVGPU_AS_IOCTL_UNMAP_BUFFER ===
=== NVSCHED_CTRL_HAS_OVERRUN_EVENT ===
Unmaps a memory region from the device address space.
Returns a boolean to tell if the scheduler has an overrun event or not.


struct {
  struct {
     __in u64 offset;
     __out u8 has_overrun;
   };
   };


=== NVGPU_AS_IOCTL_ALLOC_AS ===
=== NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT ===
Nintendo's custom implementation for allocating an address space.
Returns the overrun event's data from the scheduler.


   struct {
   struct {
     __in u32 big_page_size;   // depends on GPU's available_big_page_sizes; 0=default
     __out u64 runlist_id;
     __in s32 as_fd;          // ignored; passes 0
    __out u64 debt;
     __in u64 reserved;       // ignored; passes 0
     __out u64 unk0;          // 3.0.0+ only
     __out u64 unk1;           // 3.0.0+ only
   };
   };


=== NVGPU_AS_IOCTL_GET_VA_REGIONS ===
=== NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE ===
Nintendo's custom implementation to get rid of pointer in struct.
Installs a fence swap event?
 
Uses [[#Ioctl3|Ioctl3]].


  struct va_region {
    u64 offset;
    u32 page_size;
    u32 reserved;
    u64 pages;
  };
 
   struct {
   struct {
     u64          buf_addr;   // (contained output user ptr on linux, ignored)
     __in u32 fence_id;
     __inout u32   buf_size;   // forced to 2*sizeof(struct va_region)
     __in u32 fence_value;
     u32           reserved;
     __in u32 swap_interval;
    __out struct  va_region regions[2];
   };
   };


=== NVGPU_AS_IOCTL_ALLOC_AS_EX ===
=== NVSCHED_CTRL_DETACH_APPLICATION ===
Nintendo's custom implementation for allocating an address space with extra params.
Places the given application in detached state.


   struct {
   struct {
    __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
     __in u64 application_id;
    __in s32 as_fd;          // ignored; passes 0
    __in u32 flags;          // passes 0
    __in u32 reserved;        // ignored; passes 0
     __in u64 va_range_start;
    __in u64 va_range_end;
    __in u64 va_range_split;
   };
   };


=== NVGPU_AS_IOCTL_MAP_BUFFER_EX2 ===
== /dev/nverpt-ctrl ==
Maps a memory region in the device address space with extra params.
Added in firmware version 3.0.0.
 
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA|NVERPT_TELEMETRY_SUBMIT_DATA]]
|-
| 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA|NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]]
|}


Unaligned size will cause a [[#Panic]].
=== NVERPT_TELEMETRY_SUBMIT_DATA ===
Unofficial name.


On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
Sends test data for creating a new [[Error_Report_services|Error Report]].


   struct {
   struct {
     __in     u32 flags;         // bit0: fixed_offset, bit2: cacheable
     __in u64 TestU64;
     __inout  u32 kind;           // -1 is default
    __in u32 TestU32;
     __in     u32 mem_id;         // nvmap handle
    __in u8  padding0[4];
     u32           reserved0;
    __in s64 TestI64;
     __in     u64 buffer_offset;
    __in s32 TestI32;
     __in     u64 mapping_size;
     __in u8  TestString[32];
     union {
    __in u8  TestU8Array[8];
      __out  u64 offset;
    __in u32 TestU8Array_size;
      __in   u64 align;
     __in u32 TestU32Array[8];
     };
     __in u32 TestU32Array_size;
     __in     u64 vma_addr;
     __in u64 TestU64Array[8];
     __in     u32 pages;
     __in u32 TestU64Array_size;
     u32          reserved1;
     __in s32 TestI32Array[8];
    __in u32 TestI32Array_size;
    __in s64 TestI64Array[8];
    __in u32 TestI64Array_size;
    __in u16 TestU16;
     __in u8  TestU8;
     __in s16 TestI16;
     __in s8  TestI8;
     __in u8  padding1[5];
   };
   };


=== NVGPU_AS_IOCTL_REMAP ===
=== NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA ===
Nintendo's custom implementation of address space remapping for sparse pages.
Unofficial name.


  struct remap_op {
Sends display data for creating a new [[Error_Report_services|Error Report]].
    __in u16 flags;                      // bit2: cacheable
    __in u16 kind;         
    __in u32 mem_handle;
    __in u32 mem_offset_in_pages;
    __in u32 virt_offset_in_pages;      // (alloc_space_offset >> 0x10)
    __in u32 num_pages;                  // alloc_space_pages
  };
struct {
    __in struct remap_op entries[];
};


== /dev/nvhost-dbg-gpu ==
  struct {
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.
    __in u32 CodecType;
    __in u32 DecodeBuffers;
    __in u32 FrameWidth;
    __in u32 FrameHeight;
    __in u8  ColorPrimaries;
    __in u8  TransferCharacteristics;
    __in u8  MatrixCoefficients;
    __in u8  padding;
    __in u32 DisplayWidth;
    __in u32 DisplayHeight;
    __in u32 DARWidth;
    __in u32 DARHeight;
    __in u32 ColorFormat;
    __in u32 ColorSpace[8];
    __in u32 ColorSpace_size;
    __in u32 SurfaceLayout[8];
    __in u32 SurfaceLayout_size;
    __in u8  ErrorString[64];      // must be "Error detected = 0x1000000"
    __in u32 VideoDecState;
    __in u8  VideoLog[3712];
    __in u32 VideoLog_size;
  };
 
== /dev/nvhost-as-gpu ==
Each fd opened to this device creates an address space. An address space is then later bound with a channel.


Once a nvgpu channel has been bound to an address space it cannot be unbound. There is no support for allowing an nvgpu channel to change from one address space to another (or from one to none).
                                                                                                                             
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0x40084401 || In || 8 || NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL
| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL|NVGPU_AS_IOCTL_BIND_CHANNEL]]
|-
|-
| 0xC0??4402 || Inout || Variable || NVGPU_DBG_GPU_IOCTL_REG_OPS
| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE|NVGPU_AS_IOCTL_ALLOC_SPACE]]
|-
|-
| 0x40084403 || In || 8 || NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL
| 0xC0104103 || Inout || 16 || [[#NVGPU_AS_IOCTL_FREE_SPACE|NVGPU_AS_IOCTL_FREE_SPACE]]
|-
|-
| 0x40044404 || In || 4 || NVGPU_DBG_GPU_IOCTL_POWERGATE
| 0xC0184104 || Inout || 24 || [[#NVGPU_AS_IOCTL_MAP_BUFFER|NVGPU_AS_IOCTL_MAP_BUFFER]]
|-
|-
| 0x40044405 || In || 4 || NVGPU_DBG_GPU_IOCTL_SMPC_CTXSW_MODE
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER|NVGPU_AS_IOCTL_UNMAP_BUFFER]]
|-
|-
| 0x40044406 || In || 4 || NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_ALL_SMS
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX|NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
|-
|-
| 0xC0184407 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_PERFBUF_MAP
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS|NVGPU_AS_IOCTL_ALLOC_AS]]
|-
|-
| 0x40084408 || In || 8 || NVGPU_DBG_GPU_IOCTL_PERFBUF_UNMAP
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS|NVGPU_AS_IOCTL_GET_VA_REGIONS]]
|-
|-
| 0x40084409 || In || 8 || NVGPU_DBG_GPU_IOCTL_PC_SAMPLING
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX|NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
|-
| 0x4008440A || In || 8 || NVGPU_DBG_GPU_IOCTL_TIMEOUT
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2|NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
|-
|-
| 0x8008440B || Out || 8 || NVGPU_DBG_GPU_IOCTL_GET_TIMEOUT
| 0x8010410B || Out || 16 || [S2] [[#NVGPU_AS_IOCTL_GET_SYNC_RO_MAP|NVGPU_AS_IOCTL_GET_SYNC_RO_MAP]]
|-
|-
| 0x8004440C || Out || 4 || NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT_SIZE
| 0xC020410C || Inout || 32 || [S2] [[#NVGPU_AS_IOCTL_MAPPING_MODIFY|NVGPU_AS_IOCTL_MAPPING_MODIFY]]
|-
|-
| 0x0000440D || None || 0 || [[#NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT]]
| 0xC???410D || Inout || Variable || [S2] [[#NVGPU_AS_IOCTL_REMAP_2|NVGPU_AS_IOCTL_REMAP]]
|-
|-
| 0xC018440E || Inout || 24 || NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP|NVGPU_AS_IOCTL_REMAP]]
|-
|}
| 0xC018440F || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PDES
 
|-
=== NVGPU_AS_IOCTL_BIND_CHANNEL ===
| 0xC0104410 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES]]
Identical to Linux driver.
|-
 
| 0xC0184411 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PTES
  struct {
|-
    __in u32 channel_fd;
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
  };
|-
 
| 0xC0684413 || Inout || 104 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
=== NVGPU_AS_IOCTL_ALLOC_SPACE ===
|-
Reserves pages in the device address space.
| 0xC0184414 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
|-
| 0xC0184415 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
|-
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
|-
| 0xC0104417 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_COMPTAGS
|-
| 0xC0104418 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_PA
|-
| 0xC0104419 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_PA
|-
| 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA
|-
| 0xC020441B || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA_EX
|-
| 0xC084441C || Inout || 132 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SETTINGS
|-
| 0xC018441D || Inout || 24 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SERIAL_NUMBER
|-
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
|}


=== NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT ===
  struct {
Uses [[#Ioctl3|Ioctl3]].
    __in u32 pages;
    __in u32 page_size;
    __in u32 flags;
    __in u32 padding;
    union {
      __out u64 offset;
      __in  u64 align;
    };
  };


=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES ===
=== NVGPU_AS_IOCTL_FREE_SPACE ===
Uses [[#Ioctl3|Ioctl3]].
Frees pages from the device address space.


=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES ===
  struct {
Uses [[#Ioctl3|Ioctl3]].
    __in u64 offset;
    __in u32 pages;
    __in u32 page_size;
  };


=== NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS ===
=== NVGPU_AS_IOCTL_MAP_BUFFER ===
Uses [[#Ioctl3|Ioctl3]].
Maps a memory region in the device address space.


=== NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS ===
Unaligned size will cause a [[#Panic]].
Uses [[#Ioctl2|Ioctl2]].


== /dev/nvhost-prof-gpu ==
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.


This device is identical to [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]].
  struct {
    __in    u32 flags;        // bit0: fixed_offset, bit2: cacheable
    __inout u32 reserved0;
    __in    u32 mem_id;      // nvmap handle
    __inout u32 reserved1;
    union {
      __out u64 offset;
      __in  u64 align;
    };
  };


== /dev/nvhost-ctrl-gpu ==
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
This device is for global (context independent) operations on the gpu. 
Maps a memory region in the device address space with extra params.
                                                                                                                                             
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0x80044701 || Out || 4 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE]]
|-
| 0x80284702 || Out || 40 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_INFO]]
|-
| 0x402C4703 || In || 44 || [[#NVGPU_GPU_IOCTL_ZBC_SET_TABLE]]
|-
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
|-
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
|-
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
|-
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
|-
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]
|-
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
|-
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
|-
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
|-
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
|-
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
|-
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
|-
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
|-
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
|-
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
|-
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
|-
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
|-
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
|-
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
|-
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
|-
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
|-
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|}


=== NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE ===
Unaligned size will cause a [[#Panic]].
Returns the GPU's ZCULL context size. Identical to Linux driver.
 
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


struct {
  struct {
     __out u32 size;
     __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
    __inout  u32 kind;          // -1 is default
    __in      u32 mem_id;        // nvmap handle
    __inout  u32 reserved;
    __in      u64 buffer_offset;
    __in      u64 mapping_size;
    union {
      __out   u64 offset;
      __in    u64 align;
    };
   };
   };


=== NVGPU_GPU_IOCTL_ZCULL_GET_INFO ===
=== NVGPU_AS_IOCTL_UNMAP_BUFFER ===
Returns GPU's ZCULL information. Identical to Linux driver.
Unmaps a memory region from the device address space.
 
  struct {
    __in u64 offset;
  };


struct {
=== NVGPU_AS_IOCTL_ALLOC_AS ===
    __out u32 width_align_pixels;
Nintendo's custom implementation for allocating an address space.
    __out u32 height_align_pixels;
 
    __out u32 pixel_squares_by_aliquots;
  struct {
    __out u32 aliquot_total;
     __in u32 big_page_size;   // depends on GPU's available_big_page_sizes; 0=default
     __out u32 region_byte_multiplier;
     __in s32 as_fd;           // ignored; passes 0
    __out u32 region_header_size;
     __in u64 reserved;       // ignored; passes 0
     __out u32 subregion_header_size;
    __out u32 subregion_width_align_pixels;
     __out u32 subregion_height_align_pixels;
    __out u32 subregion_count;
   };
   };


=== NVGPU_GPU_IOCTL_ZBC_SET_TABLE ===
=== NVGPU_AS_IOCTL_GET_VA_REGIONS ===
Sets the active ZBC table. Identical to Linux driver.
Nintendo's custom implementation to get rid of pointer in struct.
 
Uses [[#Ioctl3|Ioctl3]].


struct {
  struct va_region {
     __in u32 color_ds[4];
     u64 offset;
     __in u32 color_l2[4];
     u32 page_size;
     __in u32 depth;
     u32 reserved;
     __in u32 format;
     u64 pages;
     __in u32 type;         // 1=color, 2=depth
  };
 
  struct {
     __inout u64  buf_addr;    // (contained output user ptr on linux, ignored)
    __inout u32   buf_size;   // forced to 2*sizeof(struct va_region)
    __inout u32  reserved;
    __out struct  va_region regions[2];
   };
   };


=== NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE ===
=== NVGPU_AS_IOCTL_ALLOC_AS_EX ===
Queries the active ZBC table. Identical to Linux driver.
Nintendo's custom implementation for allocating an address space with extra params.


struct {
  struct {
     __out u32 color_ds[4];
     __in u32 big_page_size;   // depends on GPU's available_big_page_sizes; 0=default
     __out u32 color_l2[4];
     __in s32 as_fd;          // ignored; passes 0
     __out u32 depth;
     __in u32 flags;           // passes 0
     __out u32 ref_cnt;
     __in u32 reserved;       // ignored; passes 0
     __out u32 format;
     __in u64 va_range_start;
     __out u32 type;
     __in u64 va_range_end;
     __inout u32 index_size;
     __in u64 va_range_split;
   };
   };


=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX2 ===
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.
Maps a memory region in the device address space with extra params.
 
Unaligned size will cause a [[#Panic]].


[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


  struct gpu_characteristics {
    u32 arch;                      // 0x120 (NVGPU_GPU_ARCH_GM200)
    u32 impl;                      // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
    u32 rev;                        // 0xA1 (Revision A1)
    u32 num_gpc;                    // 0x1
    u64 l2_cache_size;              // 0x40000
    u64 on_board_video_memory_size; // 0x0 (not used)
    u32 num_tpc_per_gpc;            // 0x2
    u32 bus_type;                  // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
    u32 big_page_size;              // 0x20000
    u32 compression_page_size;      // 0x20000
    u32 pde_coverage_bit_count;    // 0x1B
    u32 available_big_page_sizes;  // 0x30000
    u32 gpc_mask;                  // 0x1
    u32 sm_arch_sm_version;        // 0x503 (Maxwell Generation 5.0.3)
    u32 sm_arch_spa_version;        // 0x503 (Maxwell Generation 5.0.3)
    u32 sm_arch_warp_count;        // 0x80
    u32 gpu_va_bit_count;          // 0x28
    u32 reserved;                  // NULL
    u64 flags;                      // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
    u32 twod_class;                // 0x902D (FERMI_TWOD_A)
    u32 threed_class;              // 0xB197 (MAXWELL_B)
    u32 compute_class;              // 0xB1C0 (MAXWELL_COMPUTE_B)
    u32 gpfifo_class;              // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
    u32 inline_to_memory_class;    // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
    u32 dma_copy_class;            // 0xB0B5 (MAXWELL_DMA_COPY_A)
    u32 max_fbps_count;            // 0x1
    u32 fbp_en_mask;                // 0x0 (disabled)
    u32 max_ltc_per_fbp;            // 0x2
    u32 max_lts_per_ltc;            // 0x1
    u32 max_tex_per_tpc;            // 0x0 (not supported)
    u32 max_gpc_count;              // 0x1
    u32 rop_l2_en_mask_0;          // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
    u32 rop_l2_en_mask_1;          // 0x0
    u64 chipname;                  // 0x6230326D67 ("gm20b")
    u64 gr_compbit_store_base_hw;  // 0x0 (not supported)
  };
   struct {
   struct {
     __inout u64 gpu_characteristics_buf_size;   // must not be NULL, but gets overwritten with 0xA0=max_size
    __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
     __in   u64 gpu_characteristics_buf_addr;   // ignored, but must not be NULL
     __inout   u32 kind;           // -1 is default
     __out struct gpu_characteristics gc;
     __in     u32 mem_id;         // nvmap handle
    __inout  u32 reserved0;
    __in      u64 buffer_offset;
    __in      u64 mapping_size;
     union {
      __out   u64 offset;
      __in    u64 align;
    };
    __in      u64 vma_addr;
    __in      u32 pages;
    __inout  u32 reserved1;
   };
   };


=== NVGPU_GPU_IOCTL_GET_TPC_MASKS ===
=== NVGPU_AS_IOCTL_GET_SYNC_RO_MAP ===
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer.
Returns the GPU virtual address to the read-only syncpoint-semaphore shim.
 
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].


   struct {
   struct {
     __in u32 mask_buf_size;       // ignored, but must not be NULL
     __out    u64 base_gpuva;
     __in u32 reserved[3];
     __out    u32 sync_size;
     __out u64 mask_buf;           // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
     __out     u32 num_syncpoints;
   };
   };


=== NVGPU_GPU_IOCTL_FLUSH_L2 ===
=== NVGPU_AS_IOCTL_MAPPING_MODIFY ===
Flushes the GPU L2 cache.
Changes the kind of an existing mapped buffer region.


   struct {
   struct {
     __in u32 flush;         // l2_flush | l2_invalidate << 1 | fb_flush << 2
     __in     s16 compr_kind;
     __in u32 reserved;
     __in     s16 incompr_kind;
    __in      u64 buffer_offset;
    __in      u64 buffer_size;
    __in      u64 map_address;
   };
   };


=== NVGPU_GPU_IOCTL_INVAL_ICACHE ===
=== NVGPU_AS_IOCTL_REMAP ===
Invalidates the GPU instruction cache. Identical to Linux driver.
Nintendo's custom implementation of address space remapping for sparse pages.


   struct {
   struct remap_op {
     __in s32 channel_fd;
     u16 flags;                     // bit2: cacheable
     __in u32 reserved;
    u16 kind;         
    u32 mem_handle;
    u32 mem_offset_in_pages;
    u32 virt_offset_in_pages;      // (alloc_space_offset >> 0x10)
     u32 num_pages;                 // alloc_space_pages
   };
   };
 
=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE ===
Sets the GPU MMU debug mode. Identical to Linux driver.
 
   struct {
   struct {
     __in u32 state;
     __in struct remap_op entries[];
    __in u32 reserved;
   };
   };


=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE ===
=== NVGPU_AS_IOCTL_REMAP ===
Sets the GPU SM debug mode. Identical to Linux driver.
Switch 2 variation of [[#NVGPU_AS_IOCTL_REMAP|NVGPU_AS_IOCTL_REMAP]].


   struct {
   struct remap_op {
     __in s32 channel_fd;
     u32 flags;
     __in u32 enable;
    s16 compr_kind; 
     __in u64 sms;
    s16 incompr_kind;      
     u32 mem_handle;
    u32 reserved;
    u64 mem_offset_in_pages;
    u64 virt_offset_in_pages;
     u64 num_pages;
   };
   };
 
=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
Waits until all valid warps on the GPU SM are paused and returns their current state.
 
   struct {
   struct {
     __in u64 pwarpstate;
     __in struct remap_op entries[];
   };
   };


[6.1.0+] This command was modified to return inline data instead of using a pointer.
== /dev/nvhost-dbg-gpu ==
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.


  struct {
{| class="wikitable" border="1"
    __out u64 sm0_valid_warps;
! Value || Direction || Size || Description
    __out u64 sm0_trapped_warps;
|-
    __out u64 sm0_paused_warps;
| 0x40084401 || In || 8 || NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL
    __out u64 sm1_valid_warps;
|-
    __out u64 sm1_trapped_warps;
| 0xC0??4402 || Inout || Variable || NVGPU_DBG_GPU_IOCTL_REG_OPS
    __out u64 sm1_paused_warps;
|-
  };
| 0x40084403 || In || 8 || NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL
 
|-
=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
| 0x40044404 || In || 4 || NVGPU_DBG_GPU_IOCTL_POWERGATE
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.
|-
 
| 0x40044405 || In || 4 || NVGPU_DBG_GPU_IOCTL_SMPC_CTXSW_MODE
  struct {
|-
    __out u64 tpc_exception_en_sm_mask;
| 0x40044406 || In || 4 || NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_ALL_SMS
  };
|-
 
| 0xC0184407 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_PERFBUF_MAP
=== NVGPU_GPU_IOCTL_NUM_VSMS ===
|-
Returns the number of GPU SM units present. Identical to Linux driver.
| 0x40084408 || In || 8 || NVGPU_DBG_GPU_IOCTL_PERFBUF_UNMAP
 
|-
  struct {
| 0x40084409 || In || 8 || NVGPU_DBG_GPU_IOCTL_PC_SAMPLING
    __out u32 num_vsms;
|-
    __out u32 reserved;
| 0x4008440A || In || 8 || NVGPU_DBG_GPU_IOCTL_TIMEOUT
  };
|-
 
| 0x8008440B || Out || 8 || NVGPU_DBG_GPU_IOCTL_GET_TIMEOUT
=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
|-
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.
| 0x8004440C || Out || 4 || NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT_SIZE
 
|-
  struct {
| 0x0000440D || None || 0 || [[#NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT|NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT]]
    __out u8 sm0_gpc_index;
|-
    __out u8 sm0_tpc_index;
| 0xC018440E || Inout || 24 || NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
    __out u8 sm1_gpc_index;
|-
    __out u8 sm1_tpc_index;
| 0xC018440F || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PDES
  };
|-
 
| 0xC0104410 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES|NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES]]
=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
|-
Returns the mask value for a ZBC slot.
| 0xC0184411 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PTES
 
|-
  struct {
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES|NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
    __out u32 slot;      // always 0x07
|-
    __out u32 mask;
| 0xC0684413</br>[S2] 0xC0304413 || Inout || 104</br>48 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
  };
|-
 
| 0xC0184414</br>[S2] 0xC0084414 || Inout || 24</br>8 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS|NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
|-
Returns the GPU load value from the PMU.
| 0xC0184415</br>[S2] 0xC0084415 || Inout || 24</br>8 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS|NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
 
|-
  struct {
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
    __out u32 pmu_gpu_load;
|-
  };
| 0xC0104417 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_COMPTAGS
|-
| 0xC0104418 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_PA
|-
| 0xC0104419 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_PA
|-
| 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA
|-
| 0xC020441B || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA_EX
|-
| 0xC084441C || Inout || 132 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SETTINGS
|-
| 0xC018441D || Inout || 24 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SERIAL_NUMBER
|-
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
|-
| 0x4008441F || In || 8 || [S2]
|-
| 0x00004420 || None || 0 || [S2]
|-
| 0xC0184421 || Inout || 24 || [S2]
|-
| 0x40084422 || In || 8 || [S2] NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE
|-
| 0xC0084423 || Inout || 8 || [S2] NVGPU_DBG_GPU_IOCTL_HWPM_CTXSW_MODE
|-
| 0x40084424 || In || 8 || [S2] NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK
|-
| 0xC0104425 || Inout || 16 || [S2] NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_CONTEXTS
|-
| 0xC0184426 || Inout || 24 || [S2] NVGPU_DBG_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE
|-
| 0x40084427 || In || 8 || [S2] NVGPU_DBG_GPU_IOCTL_CLEAR_SINGLE_SM_ERROR_STATE
|-
| 0x40044428 || In || 4 || [S2] NVGPU_DBG_GPU_IOCTL_SET_SCHED_EXIT_WAIT_FOR_ERRBAR
|-
| 0xC0184429 || Inout || 24 || [S2]
|-
| 0x4010442A || In || 16 || [S2]
|-
| 0x4010442B || In || 16 || [S2]
|}


=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
=== NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT ===
Sets the clock gate control value.
Uses [[#Ioctl3|Ioctl3]].


  struct {
=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES ===
    __in u32 cg_mask;
Uses [[#Ioctl3|Ioctl3]].
    __in u32 cg_value;
  };


=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES ===
Returns the clock gate control value.
Uses [[#Ioctl3|Ioctl3]].


  struct {
=== NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS ===
    __in u32 cg_mask;
Uses [[#Ioctl3|Ioctl3]].
    __out u32 cg_value;
  };


=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
=== NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS ===
Sets the power gate control value.
Uses [[#Ioctl2|Ioctl2]].


  struct {
== /dev/nvhost-prof-gpu ==
    __in u32 pg_mask;
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.
    __in u32 pg_value;
  };


=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
This device is identical to [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]].
Returns the power gate control value.


  struct {
== /dev/nvhost-ctrl-gpu ==
    __in u32 pg_mask;
This device is for global (context independent) operations on the gpu. 
    __out u32 pg_value;
                                                                                                                                             
  };
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0x80044701 || Out || 4 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE|NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE]]
|-
| 0x80284702 || Out || 40 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_INFO|NVGPU_GPU_IOCTL_ZCULL_GET_INFO]]
|-
| 0x402C4703 || In || 44 || [[#NVGPU_GPU_IOCTL_ZBC_SET_TABLE|NVGPU_GPU_IOCTL_ZBC_SET_TABLE]]
|-
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE|NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
|-
| 0xC0B04705</br>[S2] 0xC0E04705 || Inout || 176</br>[S2] 224|| [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS|NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
|-
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS|NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
|-
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2|NVGPU_GPU_IOCTL_FLUSH_L2]]
|-
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE|NVGPU_GPU_IOCTL_INVAL_ICACHE]]
|-
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE|NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
|-
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE|NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
|-
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710)</br>[S2] 0xC0084710 || Inout || 48</br>([1.0.0-6.1.0] 8)</br>[S2] 8 || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE|NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
|-
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS|NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
|-
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS|NVGPU_GPU_IOCTL_NUM_VSMS]]
|-
| 0xC0044713</br>[S2] 0xC0084713 || Inout || 4</br>[S2] 8 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING|NVGPU_GPU_IOCTL_VSMS_MAPPING]]
|-
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK|NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
|-
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD|NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
|-
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS|NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
|-
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS|NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
|-
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS|NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
|-
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS|NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
|-
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING|NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
|-
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA|NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
|-
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME|NVGPU_GPU_IOCTL_GET_GPU_TIME]]
|-
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO|NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|-
| 0xC010471E || Inout || 16 || [S2] [[#NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS|NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS]]
|-
| 0xC010471F || Inout || 16 || [S2] [[#NVGPU_GPU_IOCTL_GET_ENGINE_INFO|NVGPU_GPU_IOCTL_GET_ENGINE_INFO]]
|}


=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
=== NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE ===
Returns the GPU PMU ELPG residency gating values.
Returns the GPU's ZCULL context size. Identical to Linux driver.


   struct {
   struct {
     __out u64 pg_ingating_time_us;
     __out u32 size;
    __out u64 pg_ungating_time_us;
    __out u64 pg_gating_cnt;
   };
   };


=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
=== NVGPU_GPU_IOCTL_ZCULL_GET_INFO ===
Returns user specific data from the error channel, if one exists.
Returns GPU's ZCULL information. Identical to Linux driver.


   struct {
   struct {
     __out u64 data;
     __out u32 width_align_pixels;
    __out u32 height_align_pixels;
    __out u32 pixel_squares_by_aliquots;
    __out u32 aliquot_total;
    __out u32 region_byte_multiplier;
    __out u32 region_header_size;
    __out u32 subregion_header_size;
    __out u32 subregion_width_align_pixels;
    __out u32 subregion_height_align_pixels;
    __out u32 subregion_count;
   };
   };


=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
=== NVGPU_GPU_IOCTL_ZBC_SET_TABLE ===
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.
Sets the active ZBC table. Identical to Linux driver.


   struct {
   struct {
     __out u64 gpu_timestamp;     // raw GPU counter (PTIMER) value
     __in u32 color_ds[4];
     __out u64 reserved;
    __in u32 color_l2[4];
    __in u32 depth;
    __in u32 format;
    __in u32 type;         // 1=color, 2=depth
  };
 
=== NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE ===
Queries the active ZBC table. Identical to Linux driver.
 
  struct {
     __out u32 color_ds[4];
    __out u32 color_l2[4];
    __out u32 depth;
    __out u32 ref_cnt;
    __out u32 format;
    __out u32 type;
    __inout u32 index_size;
   };
   };


=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.
 
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].


struct time_correlation_sample {
  struct gpu_characteristics {
  u64 cpu_timestamp;                                 // from CPU's CNTPCT_EL0 register
    u32 arch;                        // 0x120 (NVGPU_GPU_ARCH_GM200)
  u64 gpu_timestamp;                                 // from GPU's PTIMER registers
    u32 impl;                        // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
};
    u32 rev;                          // 0xA1 (Revision A1)
    u32 num_gpc;                      // 0x1
    u64 l2_cache_size;                // 0x40000
    u64 on_board_video_memory_size;  // 0x0 (not used)
    u32 num_tpc_per_gpc;              // 0x2
    u32 bus_type;                    // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
    u32 big_page_size;                // 0x20000
    u32 compression_page_size;        // 0x20000
    u32 pde_coverage_bit_count;      // 0x1B
    u32 available_big_page_sizes;    // 0x30000
    u32 gpc_mask;                    // 0x1
    u32 sm_arch_sm_version;          // 0x503 (Maxwell Generation 5.0.3)
    u32 sm_arch_spa_version;          // 0x503 (Maxwell Generation 5.0.3)
    u32 sm_arch_warp_count;          // 0x80
    u32 gpu_va_bit_count;            // 0x28
    u32 reserved;                    // 0x0
    u64 flags;                        // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
    u32 twod_class;                  // 0x902D (FERMI_TWOD_A)
    u32 threed_class;                // 0xB197 (MAXWELL_B)
    u32 compute_class;                // 0xB1C0 (MAXWELL_COMPUTE_B)
    u32 gpfifo_class;                // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
    u32 inline_to_memory_class;      // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
    u32 dma_copy_class;              // 0xB0B5 (MAXWELL_DMA_COPY_A)
    u32 max_fbps_count;              // 0x1
    u32 fbp_en_mask;                  // 0x0 (disabled)
    u32 max_ltc_per_fbp;              // 0x2
    u32 max_lts_per_ltc;              // 0x1
    u32 max_tex_per_tpc;              // 0x0 (not supported)
    u32 max_gpc_count;                // 0x1
    u32 rop_l2_en_mask_0;            // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
    u32 rop_l2_en_mask_1;            // 0x0
    u64 chipname;                     // 0x6230326D67 ("gm20b")
    u64 gr_compbit_store_base_hw;     // 0x0 (not supported)
  };
   
   
struct {
  struct {
  __out struct time_correlation_sample samples[16];  // timestamp pairs
    __inout u64 gpu_characteristics_buf_size;  // must not be NULL, but gets overwritten with 0xA0=max_size
   __in u32    count;                                 // number of pairs to read
    __in   u64 gpu_characteristics_buf_addr;   // ignored, but must not be NULL
  __in u32     source_id;                             // cpu clock source id (must be 1)
     __out struct gpu_characteristics gc;
};
  };


= Channels =
[S2] Uses [[#Ioctl3|Ioctl3]].
Channels are a concept for NVIDIA hardware blocks that share a common interface.


{| class="wikitable" border="1"
  struct gpu_characteristics {
! Path || Name
    u32 arch;                        // 0x170
|-
    u32 impl;                        // 0xE
| /dev/nvhost-gpu || GPU
    u32 rev;                          // 0xA1 (Revision A1)
|-
    u32 num_gpc;                      // 0x1
| /dev/nvhost-msenc || Video Encoder
    u64 l2_cache_size;                // 0x100000
|-
    u64 on_board_video_memory_size;  // 0x0 (not used)
| /dev/nvhost-nvdec || Video Decoder
    u32 num_tpc_per_gpc;              // 0x6
|-
    u32 bus_type;                    // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
| /dev/nvhost-nvjpg || JPEG Decoder
    u32 big_page_size;                // 0x0
|-
    u32 compression_page_size;        // 0x10000
| /dev/nvhost-vic || Video Image Compositor
    u32 pde_coverage_bit_count;      // 0x15
|-
    u32 available_big_page_sizes;    // 0x0
| /dev/nvhost-display || Display
    u32 gpc_mask;                    // 0x1
|}
    u32 sm_arch_sm_version;          // 0x808
    u32 sm_arch_spa_version;          // 0x806
    u32 sm_arch_warp_count;          // 0x60
    u32 gpu_va_bit_count;            // 0x28
    u32 reserved;                    // 0x0
    u64 flags;                        // 0x935FAF1EDC0155
    u32 twod_class;                  // 0x902D (FERMI_TWOD_A)
    u32 threed_class;                // 0xC797 (AMPERE_B)
    u32 compute_class;                // 0xC7C0 (AMPERE_COMPUTE_B)
    u32 gpfifo_class;                // 0xC76F (AMPERE_CHANNEL_GPFIFO_B)
    u32 inline_to_memory_class;      // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
    u32 dma_copy_class;              // 0xC7B5 (AMPERE_DMA_COPY_B)
    s16 gpu_ioctl_nr_last;            // 0x1F
    s16 tsg_ioctl_nr_last;            // 0xF
    s16 dbg_gpu_ioctl_nr_last;        // 0x2B
    s16 ioctl_channel_nr_last;        // 0x21
    s16 as_ioctl_nr_last;            // 0xD
    s16 unk0_ioctl_nr_last;          // 0xFFFF
    s16 unk1_ioctl_nr_last;          // 0xFFFF
    s16 unk2_ioctl_nr_last;          // 0xFFFF
    u32 max_fbps_count;              // 0x0
    u32 fbp_en_mask;                  // 0x1
    u32 emc_en_mask;                  // 0x1
    u32 max_ltc_per_fbp;              // 0x1
    u32 max_lts_per_ltc;              // 0x4
    u32 max_tex_per_tpc;              // 0x0
    u32 max_gpc_count;                // 0x1
    u32 rop_l2_en_mask_DEPRECATED_0;  // 0x0
    u32 rop_l2_en_mask_DEPRECATED_1;  // 0x0
    u64 chipname;                    // 0x6761313066 ("ga10f")
    u32 unk0;                        // 0x0
    u32 unk1;                        // 0x2
    u32 unk2;                        // 0x40
    u32 unk3;                        // 0x3
    u32 unk4;                        // 0x7
    u32 unk5;                        // 0x1
    u32 unk6;                        // 0x1
    u32 unk7;                        // 0x0
    u32 unk8;                        // 0x0
  };
 
  struct in_buf {
    __in u64 gpu_characteristics_buf_size;  // must not be NULL, but gets overwritten with 0xD0=max_size
    __in u8 reserved[0xD8];
  };
 
  struct out_buf {
    __out u8 reserved[0xE0];
  };
 
  struct out_buf2 {
    __out struct gpu_characteristics gc;
  };
 
=== NVGPU_GPU_IOCTL_GET_TPC_MASKS ===
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer.


== Ioctls ==
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
{| class="wikitable" border="1"
 
! Value || Size || Description
  struct {
|-
    __in u32 mask_buf_size;      // ignored, but must not be NULL
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
    __inout u32 reserved[3];
|-
    __out u64 mask_buf;          // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
  };
|-
 
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
=== NVGPU_GPU_IOCTL_FLUSH_L2 ===
|-
Flushes the GPU L2 cache.
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
 
|-
  struct {
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
    __in u32 flush;          // l2_flush | l2_invalidate << 1 | fb_flush << 2
|-
    __in u32 reserved;
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
  };
|-
 
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
=== NVGPU_GPU_IOCTL_INVAL_ICACHE ===
|-
Invalidates the GPU instruction cache. Identical to Linux driver.
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
|-
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
|-
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
|-
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
|-
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
|-
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
|- style="border-top: double"
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
|-
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
|-
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
|-
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
|-
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
|-
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
|-
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
|-
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
|-
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
|-
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
|-
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
|-
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
|-
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
|-
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
|-
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
|-
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
|-
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
|-
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
|-
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
|-
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
|-
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
|-
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
|-
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
|-
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
|-
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
|- style="border-top: double"
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|}


=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
  struct {
Submits data to the channel.
    __in s32 channel_fd;
    __in u32 reserved;
  };


   struct cmdbuf {
=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE ===
     u32 mem;
Sets the GPU MMU debug mode. Identical to Linux driver.
    u32 offset;
 
     u32 words;
   struct {
     __in u32 state;
     __in u32 reserved;
   };
   };
 
 
   struct reloc {
=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE ===
     u32 cmdbuf_mem;
Sets the GPU SM debug mode. Identical to Linux driver.
    u32 cmdbuf_offset;
 
     u32 target;
   struct {
     u32 target_offset;
     __in s32 channel_fd;
     __in u32 enable;
     __in u64 sms;
   };
   };
 
 
  struct reloc_shift {
=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
    u32 shift;
Waits until all valid warps on the GPU SM are paused and returns their current state.
  };
 
 
  struct syncpt_incr {
    u32 syncpt_id;
    u32 syncpt_incrs;
    u32 reserved[3];
  };
 
   struct {
   struct {
     __in   u32 num_cmdbufs;
     __in u64 pwarpstate;
    __in    u32 num_relocs;
    __in    u32 num_syncpt_incrs;
    __in    u32 num_fences;
    __in    struct cmdbuf cmdbufs[];              // depends on num_cmdbufs
    __in    struct reloc relocs[];                // depends on num_relocs
    __in    struct reloc_shift reloc_shifts[];    // depends on num_relocs
    __in    struct syncpt_incr syncpt_incrs[];    // depends on num_syncpt_incrs
    __out  u32 fence_thresholds[];                // depends on num_fences
   };
   };


=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
[6.1.0+] This command was modified to return inline data instead of using a pointer.
Returns the current syncpoint value for a given module. Identical to Linux driver.


   struct {
   struct {
     __in    u32 module_id;
     __out u64 sm0_valid_warps;
     __out   u32 syncpt_value;
    __out u64 sm0_trapped_warps;
    __out u64 sm0_paused_warps;
    __out u64 sm1_valid_warps;
    __out u64 sm1_trapped_warps;
     __out u64 sm1_paused_warps;
   };
   };


=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
Returns the current waitbase value for a given module. Always returns 0.
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.


   struct {
   struct {
    __in    u32 module_id;
     __out u64 tpc_exception_en_sm_mask;
     __out   u32 waitbase_value;
   };
   };


=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
=== NVGPU_GPU_IOCTL_NUM_VSMS ===
Stubbed. Does a debug print and returns 0.
Returns the number of GPU SM units present. Identical to Linux driver.
 
=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
Sets the submit timeout value for the channel. Identical to Linux driver.


   struct {
   struct {
     __in    u32 timeout;
     __out u32 num_vsms;
    __out u32 reserved;
   };
   };


=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
Sets the clock rate value for a given module. Identical to Linux driver.
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.


   struct {
   struct {
     __in    u32 clk_rate;
     __out u8 sm0_gpc_index;
     __in    u32 module_id;
     __out u8 sm0_tpc_index;
    __out u8 sm1_gpc_index;
    __out u8 sm1_tpc_index;
   };
   };


=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.
Returns the mask value for a ZBC slot.


   struct handle {
   struct {
     u32 handle_id_in;                 // nvmap handle to map
     __out u32 slot;       // always 0x07
     u32 phys_addr_out;               // returned device physical address mapped to the handle
     __out u32 mask;
   };
   };
 
=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
Returns the GPU load value from the PMU.
 
   struct {
   struct {
     __in    u32 num_handles;         // number of nvmap handles to map
     __out u32 pmu_gpu_load;
    __in    u32 reserved;            // ignored
    __in    u8  is_compr;            // memory to map is compressed
    __in    u8  padding[3];          // ignored
    __inout struct handle handles[];  // depends on num_handles
   };
   };


=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER ===
=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
Uses '''nvmap_unpin''' internally to unpin a given number of nvmap handles from their device physical address.
Sets the clock gate control value.


  struct handle {
    u32 handle_id_in;                // nvmap handle to unmap
    u32 reserved;                    // ignored
  };
   struct {
   struct {
     __in   u32 num_handles;         // number of nvmap handles to unmap
     __in u32 cg_mask;
     __in   u32 reserved;             // ignored
     __in u32 cg_value;
    __in    u8  is_compr;            // memory to unmap is compressed
    __in    u8  padding[3];          // ignored
    __inout struct handle handles[];  // depends on num_handles
   };
   };


=== NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX ===
=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
Sets the global timeout value for the channel. Identical to Linux driver.
Returns the clock gate control value.


   struct {
   struct {
     __in   u32 timeout;
     __in u32 cg_mask;
     __in    u32 flags;
     __out u32 cg_value;
   };
   };


=== NVHOST_IOCTL_CHANNEL_GET_CLK_RATE ===
=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
Returns the clock rate value for a given module. Identical to Linux driver.
Sets the power gate control value.


   struct {
   struct {
     __out  u32 clk_rate;
     __in u32 pg_mask;
     __in   u32 module_id;
     __in u32 pg_value;
   };
   };


=== NVHOST_IOCTL_CHANNEL_SUBMIT_EX ===
=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
Same as [[#NVHOST_IOCTL_CHANNEL_SUBMIT|NVHOST_IOCTL_CHANNEL_SUBMIT]].
Returns the power gate control value.
 
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]], but calls '''nvmap_unpin''' internally in case of error.
 
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]].
 
=== NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD ===
Binds a nvmap object to this channel. Identical to Linux driver.


   struct {
   struct {
     __in u32 nvmap_fd;
     __in u32 pg_mask;
    __out u32 pg_value;
   };
   };


=== NVGPU_IOCTL_CHANNEL_SET_TIMEOUT ===
=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
Sets the timeout value for the GPU channel. Identical to Linux driver.
Returns the GPU PMU ELPG residency gating values.


   struct {
   struct {
     __in u32 timeout;
     __out u64 pg_ingating_time_us;
    __out u64 pg_ungating_time_us;
    __out u64 pg_gating_cnt;
   };
   };


=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO ===
=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
Allocates gpfifo entries. Identical to Linux driver.
Returns user specific data from the error channel, if one exists.


   struct {
   struct {
     __in u32 num_entries;
     __out u64 data;
    __in u32 flags;
   };
   };


=== NVGPU_IOCTL_CHANNEL_WAIT ===
=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
Waits on channel. Identical to Linux driver.
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.


   struct {
   struct {
     __in u32 type;           // wait type (0=notifier, 1=semaphore)
     __out u64 gpu_timestamp;     // raw GPU counter (PTIMER) value
    __in u32 timeout;        // wait timeout value
     __out u64 reserved;
     __in u32 dmabuf_fd;      // nvmap handle
    __in u32 offset;          // nvmap memory offset
    __in u32 payload;        // payload data (semaphore only)
    __in u32 padding;         // ignored
   };
   };


=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS ===
=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
Maps memory for the cycle stats buffer. Identical to Linux driver.
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.


  struct time_correlation_sample {
    u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register
    u64 gpu_timestamp;                                  // from GPU's PTIMER registers
  };
   struct {
   struct {
     __in u32 dmabuf_fd;   // nvmap handle
    __out struct time_correlation_sample samples[16];  // timestamp pairs
    __in u32    count;                                // number of pairs to read
     __in u32     source_id;                             // cpu clock source id (must be 1)
   };
   };


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO ===
=== NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS ===
Submits a gpfifo object. Modified to take inline entry objects instead of a pointer.
Adjusts options of deterministic channels in channel batches.
 
Uses [[#Ioctl2|Ioctl2]].


   struct fence {
   struct deterministic_opts {
     u32 id;
     __inout u32 num_channels;
     u32 value;
     __in u32 flags;
    __in u64 channels;                          // ignored
  };
 
  struct in_buf {
    __in struct deterministic_opts opts;
   };
   };
    
    
   struct gpfifo_entry {
   struct in_buf2 {
     u32 entry0;                             // gpu_iova_lo
     __in u32 channels[num_channels];
    u32 entry1;                              // gpu_iova_hi | (allow_flush << 8) | (is_push_buf << 9) | (size << 10) | (sync << 31)
   };
   };
    
    
   struct {
   struct out_buf {
     __in    u64 gpfifo;                      // (ignored) pointer to gpfifo fence structs
     __out struct deterministic_opts opts;
    __in    u32 num_entries;                // number of fence objects being submitted
    union {
      __out u32 detailed_error;
      __in  u32 flags;
    };
    __inout struct fence fence_out;          // returned new fence object for others to wait on
    __in    struct gpfifo_entry entries[];   // depends on num_entries
   };
   };


=== NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX ===
=== NVGPU_GPU_IOCTL_GET_ENGINE_INFO ===
Allocates a graphics context object. Modified to ignore object's ID.
Returns information on graphics engines.


You can only have one object context allocated at a time. You must have bound an address space before using this.
Uses [[#Ioctl3|Ioctl3]].


   struct {
   struct engine_info {
     __in  u32 class_num;   // 0x902D=2d, 0xB197=3d, 0xB1C0=compute, 0xA140=kepler, 0xB0B5=DMA, 0xB06F=channel_gpfifo
     __inout u32 engine_info_buf_size;
     __in u32 flags;       // bit0: LOCKBOOST_ZERO
     __in u32 reserved;
     __out u64 obj_id;       // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
     __in u64 engine_info_buf_addr;                   // ignored
  };
 
  struct engine_info_item {
    __out u32 engine_id;
    __out u32 engine_instance;
    __out s32 runlist_id;
    __out u32 reserved;
   };
   };
 
 
=== NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX ===
   struct in_buf {
Frees a graphics context object. Not supported.
     __in struct engine_info info;
 
   struct {
     __in u64 obj_id;       // ignored
   };
   };
 
 
=== NVGPU_IOCTL_CHANNEL_ZCULL_BIND ===
  struct out_buf {
Binds a ZCULL context to the channel. Identical to Linux driver.
     __out struct engine_info info;  
 
struct {
     __in u64 gpu_va;
    __in u32 mode;        // 0=global, 1=no_ctxsw, 2=separate_buffer, 3=part_of_regular_buf
    __in u32 reserved;
   };
   };
 
 
=== NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER ===
   struct out_buf2 {
Initializes the error notifier for this channel. Unlike for the Linux kernel, the Switch driver cannot write to an arbitrary userspace buffer. Thus new ioctls have been introduced to fetch the error information rather than using a shared memory buffer.
     __out struct engine_info_item items[engine_info_buf_size];
 
   struct {
     __in u64 offset;  // ignored
    __in u64 size;    // ignored
    __in u32 mem;      // must be non-zero to initialize, zero to de-initialize
    __in u32 reserved; // ignored
   };
   };


=== NVGPU_IOCTL_CHANNEL_SET_PRIORITY ===
== (S2) /dev/nvhost-prof-dev-gpu ==                                                                                                          
Changes channel's priority. Identical to Linux driver.
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0x40085001 || In || 8 || NVGPU_PROFILER_IOCTL_BIND_CONTEXT
|-
| 0x40105002 || In || 16 || NVGPU_PROFILER_IOCTL_RESERVE_PM_RESOURCE
|-
| 0x40085003 || In || 8 || NVGPU_PROFILER_IOCTL_RELEASE_PM_RESOURCE
|-
| 0xC0305004 || Inout || 48 || NVGPU_PROFILER_IOCTL_ALLOC_PMA_STREAM
|-
| 0x00005005 || None || 0 || NVGPU_PROFILER_IOCTL_FREE_PMA_STREAM
|-
| 0x00005006 || None || 0 || NVGPU_PROFILER_IOCTL_BIND_PM_RESOURCES
|-
| 0x00005007 || None || 0 || NVGPU_PROFILER_IOCTL_UNBIND_PM_RESOURCES
|-
| 0xC0285008 || Inout || 40 || NVGPU_PROFILER_IOCTL_PMA_STREAM_UPDATE_GET_PUT
|-
| 0xC0205009 || Inout || 32 || NVGPU_PROFILER_IOCTL_EXEC_REG_OPS
|-
| 0x0000500A || None || 0 || NVGPU_PROFILER_IOCTL_UNBIND_CONTEXT
|-
| 0x4010500B || In || 16 || NVGPU_PROFILER_IOCTL_VAB_RESERVE
|-
| 0x0000500C || None || 0 || NVGPU_PROFILER_IOCTL_VAB_RELEASE
|-
| 0x4010500D || In || 16 || NVGPU_PROFILER_IOCTL_VAB_FLUSH_STATE
|}


  struct {
== (S2) /dev/nvhost-tsg-gpu ==                                                                                    
    __in u32 priority;    // 0x32 is low, 0x64 is medium and 0x96 is high
{| class="wikitable" border="1"
  };
! Value || Direction || Size || Description
 
|-
=== NVGPU_IOCTL_CHANNEL_ENABLE ===
| 0xC0045401 || Inout || 4 || [[#NVGPU_TSG_IOCTL_BIND_CHANNEL|NVGPU_TSG_IOCTL_BIND_CHANNEL]]
Enables the current channel. Identical to Linux driver.
|-
 
| 0xC0045402 || Inout || 4 || [[#NVGPU_TSG_IOCTL_UNBIND_CHANNEL|NVGPU_TSG_IOCTL_UNBIND_CHANNEL]]
=== NVGPU_IOCTL_CHANNEL_DISABLE ===
|-
Disables the current channel. Identical to Linux driver.
| 0x00005403 || None || 0 || [[#NVGPU_TSG_IOCTL_ENABLE|NVGPU_TSG_IOCTL_ENABLE]]
 
|-
=== NVGPU_IOCTL_CHANNEL_PREEMPT ===
| 0x00005404 || None || 0 || [[#NVGPU_TSG_IOCTL_DISABLE|NVGPU_TSG_IOCTL_DISABLE]]
Clears the FIFO pipe for this channel. Identical to Linux driver.
|-
| 0x00005405 || None || 0 || [[#NVGPU_TSG_IOCTL_PREEMPT|NVGPU_TSG_IOCTL_PREEMPT]]
|-
| 0xC0085407 || Inout || 8 || [[#NVGPU_TSG_IOCTL_SET_RUNLIST_INTERLEAVE|NVGPU_TSG_IOCTL_SET_RUNLIST_INTERLEAVE]]
|-
| 0xC0045408 || Inout || 4 || [[#NVGPU_TSG_IOCTL_SET_TIMESLICE|NVGPU_TSG_IOCTL_SET_TIMESLICE]]
|-
| 0xC0105409 || Inout || 16 || [[#NVGPU_TSG_IOCTL_EVENT_ID_CTRL|NVGPU_TSG_IOCTL_EVENT_ID_CTRL]]
|-
| 0x8004540A || Out || 4 || [[#NVGPU_TSG_IOCTL_GET_TIMESLICE|NVGPU_TSG_IOCTL_GET_TIMESLICE]]
|-
| 0xC018540B || Inout || 24 || [[#NVGPU_TSG_IOCTL_BIND_CHANNEL_EX|NVGPU_TSG_IOCTL_BIND_CHANNEL_EX]]
|-
| 0xC018540C || Inout || 24 || [[#NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE|NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE]]
|-
| 0xC008540D || Inout || 8 || [[#NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION|NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION]]
|}


=== NVGPU_IOCTL_CHANNEL_FORCE_RESET ===
=== NVGPU_TSG_IOCTL_BIND_CHANNEL ===
Forces the channel to reset. Identical to Linux driver.
Binds a channel to the TSG.
 
=== NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL ===
Controls event notifications.


   struct {
   struct {
     __in u32 cmd;   // 0=disable, 1=enable, 2=clear
     __in s32 channel_fd;
    __in u32 id;    // same id's as for [[#QueryEvent]]
   };
   };


=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT ===
=== NVGPU_TSG_IOCTL_UNBIND_CHANNEL ===
Controls the cycle stats snapshot buffer. Identical to Linux driver.
Unbinds a channel from the TSG.


   struct {
   struct {
     __in   u32 cmd;         // command to handle (0=flush, 1=attach, 2=detach)
     __in s32 channel_fd;
    __in    u32 dmabuf_fd;  // nvmap handle
    __inout u32 extra;      // extra payload data/result
    __in    u32 padding;    // ignored
   };
   };


=== NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO ===
=== NVGPU_TSG_IOCTL_ENABLE ===
Returns information on the current error notification caught by the error notifier. Exclusive to the Switch.
Enables the TSG in runlist.
 
=== NVGPU_TSG_IOCTL_DISABLE ===
Disables the TSG in runlist.
 
=== NVGPU_TSG_IOCTL_PREEMPT ===
Preempts the TSG.
 
=== NVGPU_TSG_IOCTL_SET_RUNLIST_INTERLEAVE ===
Configures interleaving channels in a runlist.


   struct {
   struct {
     __out u32 error_info[32];   // first word is an error code (0=no_error, 1=gr_error, 2=gr_error, 3=invalid, 4=invalid)
     __in u32 level;
    __in u32 reserved;
   };
   };


=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
=== NVGPU_TSG_IOCTL_SET_TIMESLICE ===
Returns the current error notification caught by the error notifier. Exclusive to the Switch.
Sets how long a channel occupies an engine uninterrupted.


   struct {
   struct {
     __out u64 timestamp;    // fetched straight from armGetSystemTick
     __in u32 timeslice_us;
    __out u32 info32;      // error code
    __out u16 info16;      // additional error info
    __out u16 status;       // always 0xFFFF
   };
   };


=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX ===
=== NVGPU_TSG_IOCTL_EVENT_ID_CTRL ===
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.
Controls event notifications.


struct fence {
  struct {
     u32 id;
     __in u32 cmd;
     u32 value;
     __in u32 event_id;
};
    __out s32 event_fd;
    __in u32 padding;
struct {
   };
  __in   u32 num_entries;
  __in    u32 num_jobs;
  __in   u32 flags;
  __out   struct fence fence_out;          // returned new fence object for others to wait on
  __in    u32 reserved[3];                // ignored
};


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY ===
=== NVGPU_TSG_IOCTL_GET_TIMESLICE ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]].
Gets how long a channel occupies an engine uninterrupted.


=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2 ===
  struct {
Same as [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]].
    __out u32 timeslice_us;
  };


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2 ===
=== NVGPU_TSG_IOCTL_BIND_CHANNEL_EX ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]], but uses [[#Ioctl2|Ioctl2]].
Binds a channel to the TSG of the node receiving the command.


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY ===
  struct {
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]], but uses [[#Ioctl2|Ioctl2]].
    __in s32 channel_fd;
    __in u32 subcontext_id;
    __in u32 reserved[4];
  };


=== NVGPU_IOCTL_CHANNEL_SET_TIMESLICE ===
=== NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE ===
Changes channel's timeslice. Identical to Linux driver.
Reads the error state of a single SM.
 
Uses [[#Ioctl3|Ioctl3]].


   struct {
   struct single_sm_error_state {
     __in u32 timeslice;
     __in u32 sm_id;
    __inout u32 reserved;
    __inout u64 record_mem;
    __in u64 record_size;
  };
 
  struct in_buf {
    __in struct single_sm_error_state state;
  };
 
  struct out_buf {
    __out struct single_sm_error_state state;
   };
   };
 
 
=== NVGPU_IOCTL_CHANNEL_SET_USER_DATA ===
   struct out_buf2 {
Sets user specific data.
     __out u8 state[];
 
   struct {
     __in u64 data;
   };
   };


=== NVGPU_IOCTL_CHANNEL_GET_USER_DATA ===
=== NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION ===
Returns user specific data.
Configures L2 sector promotion.


   struct {
   struct {
     __out u64 data;
     __in u32 promotion_flag;
    __in u32 reserved;
   };
   };


= NvDrvPermission =
= Channels =
This is "nns::nvdrv::NvDrvPermission".
Channels are a concept for NVIDIA hardware blocks that share a common interface.


{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Bits
! Path || Name
!  Name
|-
!  Description
| /dev/nvhost-gpu || GPU
|-
|-
| 0
| /dev/nvhost-msenc || Video Encoder
| Gpu
|-
| Can access [[#Channels|/dev/nvhost-gpu]], [[#/dev/nvhost-ctrl-gpu|/dev/nvhost-ctrl-gpu]] and [[#/dev/nvhost-as-gpu|/dev/nvhost-as-gpu]].
| /dev/nvhost-nvdec || Video Decoder
|-
|-
| 1
| /dev/nvhost-nvjpg || JPEG Decoder
| GpuDebug
| Can access [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]] and [[#/dev/nvhost-prof-gpu|/dev/nvhost-prof-gpu]].
|-
|-
| 2
| /dev/nvhost-vic || Video Image Compositor
| GpuSchedule
| Can access [[#/dev/nvsched-ctrl|/dev/nvsched-ctrl]].
|-
|-
| 3
| /dev/nvhost-display || Display
| VIC
| Can access [[#Channels|/dev/nvhost-vic]].
|-
|-
| 4
| /dev/nvhost-tsec || TSEC
| VideoEncoder
|}
| Can access [[#Channels|/dev/nvhost-msenc]].
 
== Ioctls ==
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
|-
| 5
| 0xC0??0001 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT|NVHOST_IOCTL_CHANNEL_SUBMIT]]
| VideoDecoder
| Can access [[#Channels|/dev/nvhost-nvdec]].
|-
|-
| 6
| 0xC0080002 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT|NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
| TSEC
| Can access [[#Channels|/dev/nvhost-tsec]].
|-
|-
| 7
| 0xC0080003 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE|NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
| JPEG
|-
| Can access [[#Channels|/dev/nvhost-nvjpg]].
| 0xC0080004 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX|NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
|-
| 0x40040007 || In || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT|NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
|-
| 0x40080008 || In || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE|NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
|-
|-
| 8
| 0xC0??0009 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
| Display
| Can access [[#Channels|/dev/nvhost-display]], [[#/dev/nvcec-ctrl|/dev/nvcec-ctrl]], [[#/dev/nvhdcp_up-ctrl|/dev/nvhdcp_up-ctrl]], [[#/dev/nvdisp-ctrl|/dev/nvdisp-ctrl]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp0]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp1]], [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp0]] and [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp1]].
|-
|-
| 9
| 0xC0??000A || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
| ImportMemory
| Can duplicate [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
|-
| 10
| 0x00000013 || None || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX|NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
| NoCheckedAruid
| Can use [[#SetAruidWithoutCheck|SetAruidWithoutCheck]].
|-
|-
| 11
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE|NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
|
| Can use [[#SetGraphicsFirmwareMemoryMarginEnabled|SetGraphicsFirmwareMemoryMarginEnabled]].
|-
|-
| 12
| 0xC0??0024 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX|NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
|
| Can duplicate exported [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
|-
| 13
| 0xC0??0025 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX|NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
|
| Can use the GPU virtual address range 0xC0000 to 0x580000 instead of 0x0 to 0xC0000.
|-
|-
| 14
| 0xC0??0026 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX|NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
|
|- style="border-top: double"
| Can use [[#NVMAP_IOC_EXPORT_FOR_ARUID|NVMAP_IOC_EXPORT_FOR_ARUID]] and [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID|NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]].
| 0x40044801 || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD|NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
|-
|-
| 15
| 0x40044803 || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT|NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
|
| Can use the virtual address ranges 0x0 to 0x100000000 (GPU) and 0x0 to 0xE0000000 (non-GPU) instead of 0x100000000 to 0x11FA50000 (GPU) and 0xE0000000 to 0xFFFE0000 (non-GPU).
|}
 
= NvError =
This is "nns::nvdrv::NvError".
 
{| class="wikitable" border="1"
|-
|-
! Value || Name
| 0x40084805 || In || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
|-
|-
| 0x0 || Success
| 0x40184806 || In || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT|NVGPU_IOCTL_CHANNEL_WAIT]]
|-
|-
| 0x1 || NotImplemented
| 0xC0044807 || Inout || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS|NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
|-
|-
| 0x2 || NotSupported
| 0xC0??4808 || Inout || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
|-
|-
| 0x3 || NotInitialized
| 0xC0104809 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX|NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
|-
|-
| 0x4 || BadParameter
| 0x4008480A || In || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX|NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
|-
|-
| 0x5 || Timeout
| 0xC010480B || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND|NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
|-
|-
| 0x6 || InsufficientMemory
| 0xC018480C || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER|NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
|-
|-
| 0x7 || ReadOnlyAttribute
| 0x4004480D || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY|NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
|-
|-
| 0x8 || InvalidState
| 0x0000480E || None || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE|NVGPU_IOCTL_CHANNEL_ENABLE]]
|-
|-
| 0x9 || InvalidAddress
| 0x0000480F || None || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE|NVGPU_IOCTL_CHANNEL_DISABLE]]
|-
|-
| 0xA || InvalidSize
| 0x00004810 || None || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT|NVGPU_IOCTL_CHANNEL_PREEMPT]]
|-
|-
| 0xB || BadValue
| 0x00004811 || None ||  0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET|NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
|-
|-
| 0xD || AlreadyAllocated
| 0x40084812</br>[S2] 0x40104812 || In || 8</br>[S2] 16 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL|NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
|-
|-
| 0xE || Busy
| 0xC0104813 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT|NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
|-
|-
| 0xF || ResourceError
| 0x40084714 || In || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA|NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
|-
| 0x10 || CountMismatch
| 0x80084715 || Out || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA|NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|-
|-
| 0x11 || OverFlow
| 0x80804816 || Out || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO|NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
|-
|-
| 0x1000 || InsufficientTransferMemory
| 0xC0104817 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION|NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
|-
|-
| 0x10000 || InsufficientVideoMemory
| 0x40204818 || In || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
|-
|-
| 0x10001 || BadSurfaceColorScheme
| 0xC0??4819 || Inout || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
|-
|-
| 0x10002 || InvalidSurface
| 0xC020481A || Inout || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
|-
|-
| 0x10003 || SurfaceNotSupported
| 0xC018481B || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
|-
|-
| 0x20000 || DispInitFailed
| 0xC018481C || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
|-
|-
| 0x20001 || DispAlreadyAttached
| 0xC004481D || Inout || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE|NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
|-
|-
| 0x20002 || DispTooManyDisplays
| 0xC010481E || Inout || 16 || [S2] [[#NVGPU_IOCTL_CHANNEL_GET_USER_SYNCPOINT|NVGPU_IOCTL_CHANNEL_GET_USER_SYNCPOINT]]
|-
|-
| 0x20003 || DispNoDisplaysAttached
| 0xC008481F || Inout || 8 || [S2] [[#NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE|NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE]]
|-
|-
| 0x20004 || DispModeNotSupported
| 0x40044820 || In || 4 || [S2] [[#NVGPU_IOCTL_CHANNEL_OPEN|NVGPU_IOCTL_CHANNEL_OPEN]]
|-
|-
| 0x20005 || DispNotFound
| 0xC0504821 || Inout || 80 || [S2] [[#NVGPU_IOCTL_CHANNEL_SETUP_BIND|NVGPU_IOCTL_CHANNEL_SETUP_BIND]]
|-
|}
| 0x20006 || DispAttachDissallowed
 
|-
=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
| 0x20007 || DispTypeNotSupported
Submits data to the channel.
|-
 
| 0x20008 || DispAuthenticationFailed
  struct cmdbuf {
|-
    u32 mem;
| 0x20009 || DispNotAttached
    u32 offset;
|-
    u32 words;
| 0x2000A || DispSamePwrState
  };
|-
 
| 0x2000B || DispEdidFailure
  struct reloc {
|-
    u32 cmdbuf_mem;
| 0x2000C || DispDsiReadAckError
    u32 cmdbuf_offset;
|-
    u32 target;
| 0x2000D || DispDsiReadInvalidResp
    u32 target_offset;
|-
  };
| 0x30000 || FileWriteFailed
 
|-
  struct reloc_shift {
| 0x30001 || FileReadFailed
    u32 shift;
|-
  };
| 0x30002 || EndOfFile
 
|-
  struct syncpt_incr {
| 0x30003 || FileOperationFailed
    u32 syncpt_id;
|-
    u32 syncpt_incrs;
| 0x30004 || DirOperationFailed
    u32 reserved[3];
|-
  };
| 0x30005 || EndOfDirList
 
|-
  struct {
| 0x30006 || ConfigVarNotFound
    __in    u32 num_cmdbufs;
|-
    __in    u32 num_relocs;
| 0x30007 || InvalidConfigVar
    __in    u32 num_syncpt_incrs;
|-
    __in    u32 num_fences;
| 0x30008 || LibraryNotFound
    __in    struct cmdbuf cmdbufs[];              // depends on num_cmdbufs
|-
    __in    struct reloc relocs[];                // depends on num_relocs
| 0x30009 || SymbolNotFound
    __in    struct reloc_shift reloc_shifts[];    // depends on num_relocs
|-
    __in    struct syncpt_incr syncpt_incrs[];    // depends on num_syncpt_incrs
| 0x3000A || MemoryMapFailed
    __out  u32 fence_thresholds[];                // depends on num_fences
|-
  };
| 0x3000F || IoctlFailed                       
 
|-
=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
| 0x30010 || AccessDenied
Returns the current syncpoint value for a given module. Identical to Linux driver.
|-
 
| 0x30011 || DeviceNotFound
  struct {
|-
    __in    u32 module_id;
| 0x30012 || KernelDriverNotFound
    __out  u32 syncpt_value;
|-
  };
| 0x30013 || FileNotFound
 
|-
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
| 0x30014 || PathAlreadyExists
Returns the current waitbase value for a given module. Always returns 0.
|-
 
| 0xA000E || ModuleNotPresent
  struct {
|}
    __in    u32 module_id;
    __out  u32 waitbase_value;
  };
 
=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
Stubbed. Does a debug print and returns 0.
 
=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
Sets the submit timeout value for the channel. Identical to Linux driver.


= NvDrvStatus =
  struct {
This is "nns::nvdrv::NvDrvStatus".
    __in    u32 timeout;
  };
 
=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
Sets the clock rate value for a given module. Identical to Linux driver.
 
  struct {
    __in    u32 clk_rate;
    __in    u32 module_id;
  };
 
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.
 
  struct handle {
    u32 handle_id_in;                // nvmap handle to map
    u32 phys_addr_out;                // returned device physical address mapped to the handle
  };
 
  struct {
    __in    u32 num_handles;          // number of nvmap handles to map
    __in    u32 reserved;            // ignored
    __in    u8  is_compr;            // memory to map is compressed
    __in    u8  padding[3];          // ignored
    __inout struct handle handles[];  // depends on num_handles
  };
 
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER ===
Uses '''nvmap_unpin''' internally to unpin a given number of nvmap handles from their device physical address.
 
  struct handle {
    u32 handle_id_in;                // nvmap handle to unmap
    u32 reserved;                    // ignored
  };
 
  struct {
    __in    u32 num_handles;          // number of nvmap handles to unmap
    __in    u32 reserved;            // ignored
    __in    u8  is_compr;            // memory to unmap is compressed
    __in    u8  padding[3];          // ignored
    __inout struct handle handles[];  // depends on num_handles
  };
 
=== NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX ===
Sets the global timeout value for the channel. Identical to Linux driver.
 
  struct {
    __in    u32 timeout;
    __in    u32 flags;
  };
 
=== NVHOST_IOCTL_CHANNEL_GET_CLK_RATE ===
Returns the clock rate value for a given module. Identical to Linux driver.
 
  struct {
    __out  u32 clk_rate;
    __in    u32 module_id;
  };
 
=== NVHOST_IOCTL_CHANNEL_SUBMIT_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_SUBMIT|NVHOST_IOCTL_CHANNEL_SUBMIT]].
 
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]], but calls '''nvmap_unpin''' internally in case of error.
 
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]].
 
=== NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD ===
Binds a nvmap object to this channel. Identical to Linux driver.
 
  struct {
    __in u32 nvmap_fd;
  };
 
=== NVGPU_IOCTL_CHANNEL_SET_TIMEOUT ===
Sets the timeout value for the GPU channel. Identical to Linux driver.
 
  struct {
    __in u32 timeout;
  };
 
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO ===
Allocates gpfifo entries. Identical to Linux driver.
 
  struct {
    __in u32 num_entries;
    __in u32 flags;          // bit0: vpr_enabled
  };
 
=== NVGPU_IOCTL_CHANNEL_WAIT ===
Waits on channel. Identical to Linux driver.
 
  struct {
    __in u32 type;            // wait type (0=notifier, 1=semaphore)
    __in u32 timeout;        // wait timeout value
    __in u32 dmabuf_fd;      // nvmap handle
    __in u32 offset;          // nvmap memory offset
    __in u32 payload;        // payload data (semaphore only)
    __in u32 padding;        // ignored
  };
 
=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS ===
Maps memory for the cycle stats buffer. Identical to Linux driver.
 
  struct {
    __in u32 dmabuf_fd;  // nvmap handle
  };
 
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO ===
Submits a gpfifo object. Modified to take inline entry objects instead of a pointer.
 
  struct fence {
    u32 id;
    u32 value;
  };
 
  struct gpfifo_entry {
    u32 entry0;                              // gpu_iova_lo
    u32 entry1;                              // gpu_iova_hi | (allow_flush << 8) | (is_push_buf << 9) | (size << 10) | (sync << 31)
  };
 
  struct {
    __in    u64 gpfifo;                      // (ignored) pointer to gpfifo fence structs
    __in    u32 num_entries;                // number of fence objects being submitted
    union {
      __out u32 detailed_error;
      __in  u32 flags;                      // bit0: fence_wait, bit1: fence_get, bit2: hw_format, bit3: sync_fence, bit4: suppress_wfi, bit5: skip_buffer_refcounting
    };
    __inout struct fence fence_out;          // returned new fence object for others to wait on
    __in    struct gpfifo_entry entries[];  // depends on num_entries
  };
 
=== NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX ===
Allocates a graphics context object. Modified to ignore object's ID.
 
You can only have one object context allocated at a time. You must have bound an address space before using this.
 
  struct {
    __in  u32 class_num;    // 0x902D=2d, 0xB197=3d, 0xB1C0=compute, 0xA140=kepler, 0xB0B5=DMA, 0xB06F=channel_gpfifo
    __in  u32 flags;        // bit0: LOCKBOOST_ZERO
    __out u64 obj_id;      // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
  };
 
=== NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX ===
Frees a graphics context object. Not supported.
 
  struct {
    __in u64 obj_id;      // ignored
  };
 
=== NVGPU_IOCTL_CHANNEL_ZCULL_BIND ===
Binds a ZCULL context to the channel. Identical to Linux driver.
 
  struct {
    __in u64 gpu_va;
    __in u32 mode;        // 0=global, 1=no_ctxsw, 2=separate_buffer, 3=part_of_regular_buf
    __in u32 reserved;
  };
 
=== NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER ===
Initializes the error notifier for this channel. Unlike for the Linux kernel, the Switch driver cannot write to an arbitrary userspace buffer. Thus new ioctls have been introduced to fetch the error information rather than using a shared memory buffer.
 
  struct {
    __in u64 offset;  // ignored
    __in u64 size;    // ignored
    __in u32 mem;      // must be non-zero to initialize, zero to de-initialize
    __in u32 reserved; // ignored
  };
 
=== NVGPU_IOCTL_CHANNEL_SET_PRIORITY ===
Changes channel's priority. Identical to Linux driver.
 
  struct {
    __in u32 priority;    // 0x32 is low, 0x64 is medium and 0x96 is high
  };
 
=== NVGPU_IOCTL_CHANNEL_ENABLE ===
Enables the current channel. Identical to Linux driver.
 
=== NVGPU_IOCTL_CHANNEL_DISABLE ===
Disables the current channel. Identical to Linux driver.
 
=== NVGPU_IOCTL_CHANNEL_PREEMPT ===
Clears the FIFO pipe for this channel. Identical to Linux driver.
 
=== NVGPU_IOCTL_CHANNEL_FORCE_RESET ===
Forces the channel to reset. Identical to Linux driver.
 
=== NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL ===
Controls event notifications.
 
  struct {
    __in u32 cmd;    // 0=disable, 1=enable, 2=clear
    __in u32 id;    // same id's as for [[#QueryEvent]]
  };
 
=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT ===
Controls the cycle stats snapshot buffer. Identical to Linux driver.
 
  struct {
    __in    u32 cmd;        // command to handle (0=flush, 1=attach, 2=detach)
    __in    u32 dmabuf_fd;  // nvmap handle
    __inout u32 extra;      // extra payload data/result
    __in    u32 padding;    // ignored
  };
 
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO ===
Returns information on the current error notification caught by the error notifier. Exclusive to the Switch.
 
  struct {
    __out u32 type;    // Error type (0=no_error, 1=mmu_error, 2=gr_error, 3=pbdma_error, 4=timeout)
    __out u32 info[31]; // Infor depends on the error type
  };
 
==== GR Error Code Format ====
When <code>type == 2</code> (GR Error), the returned data is formatted as follows:
  struct {
    __out u32 type;      // 2=gr_error
    __out u32 intr_value; // Interrupt bits
    __out u32 addr;      // Register address (in bytes)
    __out u32 data_hi;    // Data high 32 bits
    __out u32 data_lo;    // Data low 32 bits
    __out u32 class_num;  // GPU class number (e.g., 0xb197 for MAXWELL_B)
  };
 
GR Error Interrupt Bits:
{| class="wikitable"
! Bits
! Description
|-
| 0
| GR_INTR_NOTIFY
|-
| 1
| GR_INTR_SEMAPHORE
|-
| 2
|
|-
| 3
|
|-
| 4
| GR_INTR_ILLEGAL_METHOD
|-
| 5
| GR_INTR_ILLEGAL_CLASS
|-
| 6
| GR_INTR_ILLEGAL_NOTIFY
|-
| 7
|
|-
| 8
| GR_INTR_FIRMWARE_METHOD
|-
| 9–18
|
|-
| 19
| GR_INTR_FECS_ERROR
|-
| 20
| GR_INTR_CLASS_ERROR
|-
| 21
| GR_INTR_EXCEPTION
|-
| 22–31
|
|}
 
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
Returns the current error notification caught by the error notifier. Exclusive to the Switch.
 
  struct {
    __out u64 timestamp;    // fetched straight from armGetSystemTick
    __out u32 info32;      // error code
    __out u16 info16;      // additional error info
    __out u16 status;      // always 0xFFFF
  };
 
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX ===
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.
 
  struct fence {
    u32 id;
    u32 value;
  };
  struct {
    __in    u32 num_entries;
    __in    u32 num_jobs;
    __in    u32 flags;                      // bit0: vpr_enabled
    __out  struct fence fence_out;          // returned new fence object for others to wait on
    __in    u32 reserved[3];                // ignored
  };
 
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]].
 
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2 ===
Same as [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]].
 
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2 ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]], but uses [[#Ioctl2|Ioctl2]].
 
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]], but uses [[#Ioctl2|Ioctl2]].
 
=== NVGPU_IOCTL_CHANNEL_SET_TIMESLICE ===
Changes channel's timeslice. Identical to Linux driver.
 
  struct {
    __in u32 timeslice;
  };
 
=== NVGPU_IOCTL_CHANNEL_SET_USER_DATA ===
Sets user specific data.
 
  struct {
    __in u64 data;
  };
 
=== NVGPU_IOCTL_CHANNEL_GET_USER_DATA ===
Returns user specific data.
 
  struct {
    __out u64 data;
  };
 
=== NVGPU_IOCTL_CHANNEL_GET_USER_SYNCPOINT ===
Returns information on the user syncpoint.
 
  struct {
    __out u64 gpu_va;
    __out u64 syncpoint_id;
    __out u64 syncpoint_max;
  };
 
=== NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE ===
Sets the channel preemption modes.
 
  struct {
    __in u32 graphics_preempt_mode;
    __in u32 compute_preempt_mode;
  };
 
=== NVGPU_IOCTL_CHANNEL_OPEN ===
Opens the channel for a given runlist.
 
  struct {
    __in s32 runlist_id;
  };
 
=== NVGPU_IOCTL_CHANNEL_SETUP_BIND ===
Allocates or assigns the control buffers for the channel.
 
  struct {
    __in u32 num_gpfifo_entries;
    __in u32 num_inflight_jobs;
    __in u32 flags;
    __in s32 userd_dmabuf_fd;
    __in s32 gpfifo_dmabuf_fd;
    __out u32 work_submit_token;
    __in u64 userd_dmabuf_offset;
    __in u64 gpfifo_dmabuf_offset;
    __out u64 gpfifo_gpu_va;
    __out u64 userd_gpu_va;
    __out u64 usermode_mmio_gpu_va;
    __out u32 hw_channel_id;
    __in u32 reserved[3];
  };
 
= NvDrvPermission =
This is "nns::nvdrv::NvDrvPermission".


{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
!  Bits
! Offset
!  Name
! Size
!  Description
! Description
|-
|-
| 0
| 0x0
| Gpu
| 0x4
| Can access [[#Channels|/dev/nvhost-gpu]], [[#/dev/nvhost-ctrl-gpu|/dev/nvhost-ctrl-gpu]] and [[#/dev/nvhost-as-gpu|/dev/nvhost-as-gpu]].
| FreeSize
|-
|-
| 1
| 0x4
| GpuDebug
| 0x4
| Can access [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]] and [[#/dev/nvhost-prof-gpu|/dev/nvhost-prof-gpu]].
| AllocatableSize
|-
|-
| 2
| 0x8
| GpuSchedule
| 0x4
| Can access [[#/dev/nvsched-ctrl|/dev/nvsched-ctrl]].
| MinimumFreeSize
|-
|-
| 3
| 0xC
| VIC
| 0x4
| Can access [[#Channels|/dev/nvhost-vic]].
| MinimumAllocatableSize
|-
|-
| 4
| 0x10
| VideoEncoder
| 0x10
| Can access [[#Channels|/dev/nvhost-msenc]].
| Reserved
|-
|}
| 5
| VideoDecoder
| Can access [[#Channels|/dev/nvhost-nvdec]].
|-
| 6
| TSEC
| Can access [[#Channels|/dev/nvhost-tsec]].
|-
| 7
| JPEG
| Can access [[#Channels|/dev/nvhost-nvjpg]].
|-
| 8
| Display
| Can access [[#Channels|/dev/nvhost-display]], [[#/dev/nvcec-ctrl|/dev/nvcec-ctrl]], [[#/dev/nvhdcp_up-ctrl|/dev/nvhdcp_up-ctrl]], [[#/dev/nvdisp-ctrl|/dev/nvdisp-ctrl]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp0]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp1]], [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp0]] and [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp1]].
|-
| 9
| ImportMemory
| Can duplicate [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
| 10
| NoCheckedAruid
| Can use [[#SetAruidWithoutCheck|SetAruidWithoutCheck]].
|-
| 11
|
| Can use [[#SetGraphicsFirmwareMemoryMarginEnabled|SetGraphicsFirmwareMemoryMarginEnabled]].
|-
| 12
|
| Can duplicate exported [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
| 13
|
| Can use the GPU virtual address range 0xC0000 to 0x580000 instead of 0x0 to 0xC0000.
|-
| 14
|
| Can use [[#NVMAP_IOC_EXPORT_FOR_ARUID|NVMAP_IOC_EXPORT_FOR_ARUID]] and [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID|NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]].
|-
| 15
|
| Can use the virtual address ranges 0x0 to 0x100000000 (GPU) and 0x0 to 0xE0000000 (non-GPU) instead of 0x100000000 to 0x11FA50000 (GPU) and 0xE0000000 to 0xFFFE0000 (non-GPU).
|}
 
= NvError =
This is "nns::nvdrv::NvError".
 
{| class="wikitable" border="1"
|-
! Value || Name
|-
| 0x0 || Success
|-
| 0x1 || NotImplemented
|-
| 0x2 || NotSupported
|-
| 0x3 || NotInitialized
|-
| 0x4 || BadParameter
|-
| 0x5 || Timeout
|-
| 0x6 || InsufficientMemory
|-
| 0x7 || ReadOnlyAttribute
|-
| 0x8 || InvalidState
|-
| 0x9 || InvalidAddress
|-
| 0xA || InvalidSize
|-
| 0xB || BadValue
|-
| 0xD || AlreadyAllocated
|-
| 0xE || Busy
|-
| 0xF || ResourceError
|-
| 0x10 || CountMismatch
|-
| 0x11 || OverFlow
|-
| 0x1000 || InsufficientTransferMemory
|-
| 0x10000 || InsufficientVideoMemory
|-
| 0x10001 || BadSurfaceColorScheme
|-
| 0x10002 || InvalidSurface
|-
| 0x10003 || SurfaceNotSupported
|-
| 0x20000 || DispInitFailed
|-
| 0x20001 || DispAlreadyAttached
|-
| 0x20002 || DispTooManyDisplays
|-
| 0x20003 || DispNoDisplaysAttached
|-
| 0x20004 || DispModeNotSupported
|-
| 0x20005 || DispNotFound
|-
| 0x20006 || DispAttachDissallowed
|-
| 0x20007 || DispTypeNotSupported
|-
| 0x20008 || DispAuthenticationFailed
|-
| 0x20009 || DispNotAttached
|-
| 0x2000A || DispSamePwrState
|-
| 0x2000B || DispEdidFailure
|-
| 0x2000C || DispDsiReadAckError
|-
| 0x2000D || DispDsiReadInvalidResp
|-
| 0x30000 || FileWriteFailed
|-
| 0x30001 || FileReadFailed
|-
| 0x30002 || EndOfFile
|-
| 0x30003 || FileOperationFailed
|-
| 0x30004 || DirOperationFailed
|-
| 0x30005 || EndOfDirList
|-
| 0x30006 || ConfigVarNotFound
|-
| 0x30007 || InvalidConfigVar
|-
| 0x30008 || LibraryNotFound
|-
| 0x30009 || SymbolNotFound
|-
| 0x3000A || MemoryMapFailed
|-
| 0x3000F || IoctlFailed                       
|-
| 0x30010 || AccessDenied
|-
| 0x30011 || DeviceNotFound
|-
| 0x30012 || KernelDriverNotFound
|-
| 0x30013 || FileNotFound
|-
| 0x30014 || PathAlreadyExists
|-
| 0xA000E || ModuleNotPresent
|}
 
= NvDrvStatus =
This is "nns::nvdrv::NvDrvStatus".
 
{| class="wikitable" border="1"
|-
! Offset
! Size
! Description
|-
| 0x0
| 0x4
| FreeSize
|-
| 0x4
| 0x4
| AllocatableSize
|-
| 0x8
| 0x4
| MinimumFreeSize
|-
| 0xC
| 0x4
| MinimumAllocatableSize
|-
| 0x10
| 0x10
| Reserved
|}
 
= Notes =
In some cases, a panic may occur. NV forces a crash by doing:
(void *)0 = 0xCAFE;
End result is that the system hangs with a white-screen.
 
When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done.


= Notes =
GPU rendering (GPFIFO) is only used by applets/Applications. All sysmodules doing any gfx-display uses software rendering. During system-boot, GPU GPFIFO is not used until the applets are launched.
In some cases, a panic may occur. NV forces a crash by doing:
(void *)0 = 0xCAFE;
End result is that the system hangs with a white-screen.
 
When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done.


[[Category:Services]]
[[Category:Services]]
Retrieved from "https://switchbrew.org/wiki/NV_services"