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** EvtId=3: ErrorNotifierEvent
** EvtId=3: ErrorNotifierEvent
* /dev/nvhost-ctrl: Used to get events for syncpts.
* /dev/nvhost-ctrl: Used to get events for syncpts.
** EvtId=(event_slot | ((syncpt_id & 0xFFF) << 16) | (is_valid << 28)): New format used by NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT/NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX.
** EvtId=(event_slot | ((syncpt_id & 0xFFF) << 16) | (is_valid << 28)): New format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]/[[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]].
** EvtId=(event_slot | (syncpt_id << 4)): Old format used by NVHOST_IOCTL_CTRL_SYNCPT_WAITEX.
** EvtId=(event_slot | (syncpt_id << 4)): Old format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]].
* /dev/nvhost-ctrl-gpu
* /dev/nvhost-ctrl-gpu
** EvtId=1: Returns error_event_handle.
** EvtId=1: Returns error_event_handle.
Line 593: Line 593:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0x80040212 || Out || 4 || NVDISP_CTRL_NUM_OUTPUTS
| 0x80040212 || Out || 4 || [[#NVDISP_CTRL_NUM_OUTPUTS]]
|-
|-
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES
|-
|-
| 0xC1100214 || Inout || 272 || NVDISP_CTRL_QUERY_EDID
| 0xC2100214</br>([1.0.0-11.0.1] 0xC1100214) || Inout || 528</br>([1.0.0-11.0.1] 272) || NVDISP_CTRL_QUERY_EDID
|-
|-
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
Line 609: Line 609:
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND
|-
|-
| 0x80010224 || Out || 1 || [11.0.0+]
| 0x80010224 || Out || 1 || [11.0.0+] NVDISP_CTRL_IS_DISPLAY_OLED
|}
|}
=== NVDISP_CTRL_NUM_OUTPUTS ===
  struct {
    __out u32 num_outputs;
  };


== /dev/nvdisp-disp0, /dev/nvdisp-disp1 ==
== /dev/nvdisp-disp0, /dev/nvdisp-disp1 ==
Line 622: Line 628:
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
|-
|-
| 0x80380204 || Out || 56 || NVDISP_GET_MODE
| 0x80380204 || Out || 56 || [[#NVDISP_GET_MODE]]
|-
|-
| 0x40380205 || Out || 56 || NVDISP_SET_MODE
| 0x40380205 || In || 56 || [[#NVDISP_SET_MODE]]
|-
|-
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
Line 634: Line 640:
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
|-
|-
| 0xC038020A || Inout || 56 || NVDISP_VALIDATE_MODE
| 0xC038020A || Inout || 56 || [[#NVDISP_VALIDATE_MODE]]
|-
|-
| 0x4018020B || In || 24 || NVDISP_SET_CSC
| 0x4018020B || In || 24 || NVDISP_SET_CSC
Line 646: Line 652:
| 0xC004020F || Inout || 4 || NVDISP_DPMS
| 0xC004020F || Inout || 4 || NVDISP_DPMS
|-
|-
| 0x80600210 || Out || 96 || NVDISP_GET_AVI_INFOFRAME
| 0x80600210 || Out || 96 || [[#NVDISP_GET_AVI_INFOFRAME]]
|-
|-
| 0x40600211 || In || 96 || NVDISP_SET_AVI_INFOFRAME
| 0x40600211 || In || 96 || [[#NVDISP_SET_AVI_INFOFRAME]]
|-
|-
| 0xEBFC0215 || Inout || 11260 || NVDISP_GET_MODE_DB
| 0xEBFC0215 || Inout || 11260 || [[#NVDISP_GET_MODE_DB]]
|-
|-
| 0xC003021A || Inout || 3 || NVDISP_PANEL_GET_VENDOR_ID
| 0xC003021A || Inout || 3 || [[#NVDISP_PANEL_GET_VENDOR_ID]]
|-
|-
| 0x803C021B || Out || 60 || NVDISP_GET_MODE2
| 0x803C021B || Out || 60 || [[#NVDISP_GET_MODE2]]
|-
|-
| 0x403C021C || In || 60 || NVDISP_SET_MODE2
| 0x403C021C || In || 60 || [[#NVDISP_SET_MODE2]]
|-
|-
| 0xC03C021D || Inout || 60 || NVDISP_VALIDATE_MODE2
| 0xC03C021D || Inout || 60 || [[#NVDISP_VALIDATE_MODE2]]
|-
|-
| 0xEF20021E || Inout || 12064 || NVDISP_GET_MODE_DB2
| 0xEF20021E || Inout || 12064 || [[#NVDISP_GET_MODE_DB2]]
|-
|-
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
Line 666: Line 672:
| 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE]]
| 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE]]
|-
|-
| 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT]]
| 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MAX]]
|-
|-
| 0x40040223 || In || 4 || [11.0.0+]  
| 0x40040223 || In || 4 || [11.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MIN]]
|-
|-
| 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG]]
| 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG]]
Line 675: Line 681:
|}
|}


=== NVDISP_GET_BACKLIGHT_RANGE ===
=== NVDISP_GET_MODE ===
Returns the minimum and maximum values for the intensity of the display's backlight.
Almost identical to Linux driver.
 
  struct {
    __out u32 hActive;
    __out u32 vActive;
    __out u32 hSyncWidth;
    __out u32 vSyncWidth;
    __out u32 hFrontPorch;
    __out u32 vFrontPorch;
    __out u32 hBackPorch;
    __out u32 vBackPorch;
    __out u32 hRefToSync;
    __out u32 vRefToSync;
    __out u32 pclkKHz;
    __out u32 bitsPerPixel;      // Always 0
    __out u32 vmode;            // Always 0
    __out u32 sync;
  };
 
=== NVDISP_SET_MODE ===
Almost identical to Linux driver.


   struct {
   struct {
     __out u32 min;
     __in u32 hActive;
     __out u32 max;
     __in u32 vActive;
    __in u32 hSyncWidth;
    __in u32 vSyncWidth;
    __in u32 hFrontPorch;
    __in u32 vFrontPorch;
    __in u32 hBackPorch;
    __in u32 vBackPorch;
    __in u32 hRefToSync;
    __in u32 vRefToSync;
    __in u32 pclkKHz;
    __in u32 bitsPerPixel;
    __in u32 vmode;
    __in u32 sync;
   };
   };


=== NVDISP_SET_BACKLIGHT ===
=== NVDISP_VALIDATE_MODE ===
Sets the value for the intensity of the display's backlight.
Almost identical to Linux driver.


   struct {
   struct {
     __in u32 val;
     __inout u32 hActive;
    __inout u32 vActive;
    __inout u32 hSyncWidth;
    __inout u32 vSyncWidth;
    __inout u32 hFrontPorch;
    __inout u32 vFrontPorch;
    __inout u32 hBackPorch;
    __inout u32 vBackPorch;
    __inout u32 hRefToSync;
    __inout u32 vRefToSync;
    __inout u32 pclkKHz;
    __inout u32 bitsPerPixel;
    __inout u32 vmode;
    __inout u32 sync;
   };
   };


=== NVDISP_SEND_PANEL_MSG ===
=== NVDISP_GET_AVI_INFOFRAME ===
Sends raw data to the display panel over DPAUX.
Unpacked standard AVI infoframe struct (HDMI v1.4b/2.0)


   struct {
   struct {
     __in u32 cmd;         // DPAUX AUXCTL command (1=unk, 2=I2CWR, 4=MOTWR, 7=AUXWR)
     __out u32 csum;
     __in u32 addr;         // DPAUX AUXADDR
     __out u32 scan;
     __in u32 size;         // message size
     __out u32 bar_valid;
     __in u32 msg[4];       // raw AUXDATA message
     __out u32 act_fmt_valid;
    __out u32 rgb_ycc;
    __out u32 act_format;
    __out u32 aspect_ratio;
    __out u32 colorimetry;
    __out u32 scaling;
    __out u32 rgb_quant;
    __out u32 ext_colorimetry;
    __out u32 it_content;
    __out u32 video_format;
    __out u32 pix_rep;
    __out u32 it_content_type;
    __out u32 ycc_quant;
    __out u32 top_bar_end_line_lsb;
    __out u32 top_bar_end_line_msb;
    __out u32 bot_bar_start_line_lsb;
    __out u32 bot_bar_start_line_msb;
    __out u32 left_bar_end_pixel_lsb;
    __out u32 left_bar_end_pixel_msb;
    __out u32 right_bar_start_pixel_lsb;
    __out u32 right_bar_start_pixel_msb;
   };
   };


=== NVDISP_GET_PANEL_DATA ===
=== NVDISP_SET_AVI_INFOFRAME ===
Receives raw data from the display panel over DPAUX.
Unpacked standard AVI infoframe struct (HDMI v1.4b/2.0)


   struct {
   struct {
     __in u32 cmd;         // DPAUX AUXCTL command (3=I2CRD, 5=MOTRD, 6=AUXRD)
     __in u32 csum;
     __in u32 addr;         // DPAUX AUXADDR
     __in u32 scan;
     __in u32 size;         // message size
     __in u32 bar_valid;
     __out u32 msg[4];     // raw AUXDATA message
     __in u32 act_fmt_valid;
    __in u32 rgb_ycc;
    __in u32 act_format;
    __in u32 aspect_ratio;
    __in u32 colorimetry;
    __in u32 scaling;
    __in u32 rgb_quant;
    __in u32 ext_colorimetry;
    __in u32 it_content;
    __in u32 video_format;
    __in u32 pix_rep;
    __in u32 it_content_type;
    __in u32 ycc_quant;
    __in u32 top_bar_end_line_lsb;
    __in u32 top_bar_end_line_msb;
    __in u32 bot_bar_start_line_lsb;
    __in u32 bot_bar_start_line_msb;
    __in u32 left_bar_end_pixel_lsb;
    __in u32 left_bar_end_pixel_msb;
    __in u32 right_bar_start_pixel_lsb;
    __in u32 right_bar_start_pixel_msb;
   };
   };


== /dev/nvcec-ctrl ==
=== NVDISP_GET_MODE_DB ===
{| class="wikitable" border="1"
Almost identical to Linux driver.
! Value || Direction || Size || Description
 
|-
  struct mode {
| 0x40010301 || In || 1 || NVCEC_CTRL_ENABLE
    u32 hActive;
|-
    u32 vActive;
| 0x804C0302 || Out || 76 || NVCEC_CTRL_GET_PADDR
    u32 hSyncWidth;
|-
    u32 vSyncWidth;
| 0x40040303 || In || 4 || NVCEC_CTRL_SET_LADDR
    u32 hFrontPorch;
|-
    u32 vFrontPorch;
| 0xC04C0304 || Inout || 76 || NVCEC_CTRL_WRITE
    u32 hBackPorch;
|-
    u32 vBackPorch;
| 0xC04C0305 || Inout || 76 || NVCEC_CTRL_READ
    u32 hRefToSync;
|-
    u32 vRefToSync;
| 0x804C0306 || Out || 76 || NVCEC_CTRL_GET_CONNECTION_STATUS
    u32 pclkKHz;
|-
    u32 bitsPerPixel;
| 0x804C0307 || Out || 76 || NVCEC_CTRL_GET_WRITE_STATUS
    u32 vmode;
|}
    u32 sync;
  };
  struct {
    __out struct mode modes[201];
    __out u32 num_modes;
  };
 
=== NVDISP_PANEL_GET_VENDOR_ID ===


== /dev/nvhdcp_up-ctrl ==
Returns display panel's informations.
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0xC4880401 || Inout || 1160 || NVHDCP_READ_STATUS
|-
| 0xC4880402 || Inout || 1160 || NVHDCP_READ_M
|-
| 0x40010403 || In || 1 || NVHDCP_ENABLE
|-
| 0xC0080404 || Inout || 8 || NVHDCP_CTRL_STATE_TRANSIT_EVENT_DATA
|-
| 0xC0010405 || Inout || 1 || NVHDCP_CTRL_STATE_CB
|}


== /dev/nvdcutil-disp0, /dev/nvdcutil-disp1 ==
  struct {
{| class="wikitable" border="1"
    __out u8 vendor; //0x10 - JDI, 0x20 - InnoLux, 0x30 - AUO, 0x40 - Sharp, 0x50 - Samsung
! Value || Direction || Size || Description
    __out u8 model;
|-
    __out u8 board; //0xF - 6.2", 0x10 - 5.5", 0x20 - 7.0". JDI panels have nonstandard values
| 0x40010501 || In || 1 || NVDCUTIL_ENABLE_CRC
  };
|-
| 0x40010502 || In || 1 || NVDCUTIL_VIRTUAL_EDID_ENABLE
|-
| 0x42040503 || In || 1056 || NVDCUTIL_VIRTUAL_EDID_SET_DATA
|-
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
|-
| 0x40010505 || In || 1 || NVDCUTIL_BEGIN_TELEMETRY_TEST
|-
| 0x400C0506 || In || 12 || NVDCUTIL_DSI_PACKET_TEST_SHORT_WRITE
|-
| 0x40F80507 || In || 248 || NVDCUTIL_DSI_PACKET_TEST_LONG_WRITE
|-
| 0xC0F40508 || Inout || 244 || NVDCUTIL_DSI_PACKET_TEST_READ
|-
| 0x40010509 || In || 1 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_EN
|-
| 0xC020050A || Inout || 32 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_SETTINGS
|-
| 0x8070050B || Out || 112 || [11.0.0+] NVDCUTIL_DP_CONF_READ
|}


== /dev/nvsched-ctrl ==
=== NVDISP_GET_MODE2 ===
This is a customized scheduler device.


The way this device is exposed and configured is exclusive to the Switch, since other sources don't have an actual interface for the scheduler.
  struct {
    __out u32 unk0;              //Always 0
    __out u32 hActive;
    __out u32 vActive;
    __out u32 hSyncWidth;
    __out u32 vSyncWidth;
    __out u32 hFrontPorch;
    __out u32 vFrontPorch;
    __out u32 hBackPorch;
    __out u32 vBackPorch;
    __out u32 pclkKHz;
    __out u32 bitsPerPixel;      // Always 0
    __out u32 vmode;            // Always 0
    __out u32 sync;
    __out u32 unk1;
    __out u32 reserved;
  };
 
=== NVDISP_SET_MODE2 ===
 
  struct {
    __in u32 unk0;
    __in u32 hActive;
    __in u32 vActive;
    __in u32 hSyncWidth;
    __in u32 vSyncWidth;
    __in u32 hFrontPorch;
    __in u32 vFrontPorch;
    __in u32 hBackPorch;
    __in u32 vBackPorch;
    __in u32 pclkKHz;
    __in u32 bitsPerPixel;
    __in u32 vmode;
    __in u32 sync;
    __in u32 unk1;
    __in u32 reserved;
  };
 
=== NVDISP_VALIDATE_MODE2 ===
 
  struct {
    __inout u32 unk0;
    __inout u32 hActive;
    __inout u32 vActive;
    __inout u32 hSyncWidth;
    __inout u32 vSyncWidth;
    __inout u32 hFrontPorch;
    __inout u32 vFrontPorch;
    __inout u32 hBackPorch;
    __inout u32 vBackPorch;
    __inout u32 pclkKHz;
    __inout u32 bitsPerPixel;
    __inout u32 vmode;
    __inout u32 sync;
    __inout u32 unk1;
    __inout u32 reserved;
  };
 
=== NVDISP_GET_MODE_DB2 ===


{| class="wikitable" border="1"
  struct mode2 {
! Value || Direction || Size || Description
    u32 unk0;
|-
    u32 hActive;
| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE]]
    u32 vActive;
|-
    u32 hSyncWidth;
| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE]]
    u32 vSyncWidth;
|-
    u32 hFrontPorch;
| 0x40180603 || In || 24 || [[#NVSCHED_CTRL_ADD_APPLICATION]]
    u32 vFrontPorch;
|-
    u32 hBackPorch;
| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION]]
    u32 vBackPorch;
|-
    u32 pclkKHz;
| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION]]
    u32 bitsPerPixel;
|-
    u32 vmode;
| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID]]
    u32 sync;
|-
    u32 unk1;
| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST]]
    u32 reserved;
|-
  };
| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST]]
|-
  struct {
| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST]]
    __out struct mode2 modes[201];
|-
    __out u32 num_modes;
| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST]]
  };
|-
| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST]]
|-
| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]]
|-
| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]
|-
| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]
|-
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]
|-
| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT
|-
| 0x40100611 || In || 16 || NVSCHED_CTRL_SET_RUNLIST_MAX_DEBT
|-
| 0x40010612 || In || 1 || NVSCHED_CTRL_OVERRUN_EVENTS_ENABLE
|}


=== NVSCHED_CTRL_ENABLE ===
=== NVDISP_GET_BACKLIGHT_RANGE ===
Enables the scheduler.
Returns the minimum and maximum values for the intensity of the display's backlight.


=== NVSCHED_CTRL_DISABLE ===
  struct {
Disables the scheduler.
    __out u32 min;
    __out u32 max;
  };


=== NVSCHED_CTRL_ADD_APPLICATION ===
=== NVDISP_SET_BACKLIGHT_RANGE_MAX ===
Adds a new application to the scheduler.
Sets the maximum value for the intensity of the display's backlight.


   struct {
   struct {
     __in u64 application_id;
     __in u32 max;
    __in u64 priority;
    __in u64 timeslice;
   };
   };


=== NVSCHED_CTRL_UPDATE_APPLICATION ===
=== NVDISP_SET_BACKLIGHT_RANGE_MIN ===
Updates the application parameters in the scheduler.
Sets the minimum value for the intensity of the display's backlight.


   struct {
   struct {
     __in u64 application_id;
     __in u32 min;
    __in u64 priority;
    __in u64 timeslice;
   };
   };


=== NVSCHED_CTRL_REMOVE_APPLICATION ===
=== NVDISP_SEND_PANEL_MSG ===
Removes the application from the scheduler.
Sends raw data to the display panel over DPAUX.


   struct {
   struct {
     __in u64 application_id;
     __in u32 cmd;         // DPAUX AUXCTL command (1=unk, 2=I2CWR, 4=MOTWR, 7=AUXWR)
    __in u32 addr;        // DPAUX AUXADDR
    __in u32 size;        // message size
    __in u32 msg[4];      // raw AUXDATA message
   };
   };


=== NVSCHED_CTRL_GET_ID ===
=== NVDISP_GET_PANEL_DATA ===
Returns the ID of the last scheduled object.
Receives raw data from the display panel over DPAUX.


   struct {
   struct {
     __out u64 id;
    __in u32 cmd;          // DPAUX AUXCTL command (3=I2CRD, 5=MOTRD, 6=AUXRD)
    __in u32 addr;        // DPAUX AUXADDR
    __in u32 size;        // message size
     __out u32 msg[4];     // raw AUXDATA message
   };
   };


=== NVSCHED_CTRL_ADD_RUNLIST ===
== /dev/nvcec-ctrl ==
Creates a new runlist and returns it's ID.
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0x40010301 || In || 1 || NVCEC_CTRL_ENABLE
|-
| 0x804C0302 || Out || 76 || NVCEC_CTRL_GET_PADDR
|-
| 0x40040303 || In || 4 || NVCEC_CTRL_SET_LADDR
|-
| 0xC04C0304 || Inout || 76 || NVCEC_CTRL_WRITE
|-
| 0xC04C0305 || Inout || 76 || NVCEC_CTRL_READ
|-
| 0x804C0306 || Out || 76 || NVCEC_CTRL_GET_CONNECTION_STATUS
|-
| 0x804C0307 || Out || 76 || NVCEC_CTRL_GET_WRITE_STATUS
|}


  struct {
== /dev/nvhdcp_up-ctrl ==
    __out u64 runlist_id;
{| class="wikitable" border="1"
  };
! Value || Direction || Size || Description
 
|-
=== NVSCHED_CTRL_UPDATE_RUNLIST ===
| 0xC4880401 || Inout || 1160 || NVHDCP_READ_STATUS
Updates the runlist parameters in the scheduler.
|-
| 0xC4880402 || Inout || 1160 || NVHDCP_READ_M
|-
| 0x40010403 || In || 1 || NVHDCP_ENABLE
|-
| 0xC0080404 || Inout || 8 || NVHDCP_CTRL_STATE_TRANSIT_EVENT_DATA
|-
| 0xC0010405 || Inout || 1 || NVHDCP_CTRL_STATE_CB
|}


  struct {
== /dev/nvdcutil-disp0, /dev/nvdcutil-disp1 ==
    __in u64 runlist_id;
{| class="wikitable" border="1"
    __in u64 priority;
! Value || Direction || Size || Description
    __in u64 timeslice;
|-
  };
| 0x40010501 || In || 1 || NVDCUTIL_ENABLE_CRC
 
|-
=== NVSCHED_CTRL_LINK_RUNLIST ===
| 0x40010502 || In || 1 || [[#NVDCUTIL_VIRTUAL_EDID_ENABLE]]
Links a runlist to a given application in the scheduler.
|-
 
| 0x42040503 || In || 516 || [[#NVDCUTIL_VIRTUAL_EDID_SET_DATA]]
  struct {
|-
    __in u64 runlist_id;
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
    __in u64 application_id;
|-
  };
| 0x40010505 || In || 1 || NVDCUTIL_BEGIN_TELEMETRY_TEST
|-
| 0x400C0506 || In || 12 || NVDCUTIL_DSI_PACKET_TEST_SHORT_WRITE
|-
| 0x40F80507 || In || 248 || NVDCUTIL_DSI_PACKET_TEST_LONG_WRITE
|-
| 0xC0F40508 || Inout || 244 || NVDCUTIL_DSI_PACKET_TEST_READ
|-
| 0x40010509 || In || 1 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_EN
|-
| 0xC020050A || Inout || 32 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_SETTINGS
|-
| 0x8070050B || Out || 112 || [11.0.0+] NVDCUTIL_DP_CONF_READ
|}


=== NVSCHED_CTRL_UNLINK_RUNLIST ===
=== NVDCUTIL_VIRTUAL_EDID_ENABLE ===
Unlinks a runlist from a given application in the scheduler.


   struct {
   struct {
     __in u64 runlist_id;
     __in u8 enable;
    __in u64 application_id;
   };
   };


=== NVSCHED_CTRL_REMOVE_RUNLIST ===
=== NVDCUTIL_VIRTUAL_EDID_SET_DATA ===
Removes the runlist from the scheduler.


   struct {
   struct {
     __in u64 runlist_id;
     __in u8 edid[512];
    __in u32 edid_size;
   };
   };


=== NVSCHED_CTRL_HAS_OVERRUN_EVENT ===
== /dev/nvsched-ctrl ==
Returns a boolean to tell if the scheduler has an overrun event or not.
This is a customized scheduler device.


  struct {
The way this device is exposed and configured is exclusive to the Switch, since other sources don't have an actual interface for the scheduler.
    __out u8 has_overrun;
  };


=== NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT ===
{| class="wikitable" border="1"
Returns the overrun event's data from the scheduler.
 
  struct {
    __out u64 runlist_id;
    __out u64 debt;
    __out u64 unk0;          // 3.0.0+ only
    __out u64 unk1;          // 3.0.0+ only
  };
 
=== NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE ===
Installs a fence swap event?
 
  struct {
    __in u32 fence_id;
    __in u32 fence_value;
    __in u32 swap_interval;
  };
 
=== NVSCHED_CTRL_DETACH_APPLICATION ===
Places the given application in detached state.
 
  struct {
    __in u64 application_id;
  };
 
== /dev/nverpt-ctrl ==
Added in firmware version 3.0.0.
 
{| class="wikitable" border="1"
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA]]
| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE]]
|-
| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE]]
|-
| 0x40180603 || In || 24 || [[#NVSCHED_CTRL_ADD_APPLICATION]]
|-
| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION]]
|-
| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION]]
|-
| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID]]
|-
| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST]]
|-
| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST]]
|-
|-
| 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]]
| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST]]
|}
|-
 
| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST]]
=== NVERPT_TELEMETRY_SUBMIT_DATA ===
|-
Sends test data for creating a new [[Error_Report_services|Error Report]].
| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST]]
 
|-
  struct {
| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]]
    __in u64 TestU64;
|-
    __in u32 TestU32;
| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]
    __in u8  padding0[4];
|-
    __in s64 TestI64;
| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]
    __in s32 TestI32;
|-
    __in u8  TestString[32];
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]
    __in u8  TestU8Array[8];
|-
    __in u32 TestU8Array_size;
| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT
    __in u32 TestU32Array[8];
|-
    __in u32 TestU32Array_size;
| 0x40100611 || In || 16 || NVSCHED_CTRL_SET_RUNLIST_MAX_DEBT
    __in u64 TestU64Array[8];
|-
    __in u32 TestU64Array_size;
| 0x40010612 || In || 1 || NVSCHED_CTRL_OVERRUN_EVENTS_ENABLE
    __in s32 TestI32Array[8];
|}
    __in u32 TestI32Array_size;
 
    __in s64 TestI64Array[8];
=== NVSCHED_CTRL_ENABLE ===
    __in u32 TestI64Array_size;
Enables the scheduler.
    __in u16 TestU16;
 
    __in u8  TestU8;
=== NVSCHED_CTRL_DISABLE ===
    __in s16 TestI16;
Disables the scheduler.
    __in s8  TestI8;
 
    __in u8  padding1[5];
=== NVSCHED_CTRL_ADD_APPLICATION ===
  };
Adds a new application to the scheduler.
 
=== NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA ===
Sends display data for creating a new [[Error_Report_services|Error Report]].


   struct {
   struct {
     __in u32 CodecType;
     __in u64 application_id;
     __in u32 DecodeBuffers;
     __in u64 priority;
     __in u32 FrameWidth;
     __in u64 timeslice;
    __in u32 FrameHeight;
  };
    __in u8  ColorPrimaries;
 
    __in u8  TransferCharacteristics;
=== NVSCHED_CTRL_UPDATE_APPLICATION ===
    __in u8  MatrixCoefficients;
Updates the application parameters in the scheduler.
    __in u8  padding;
 
    __in u32 DisplayWidth;
  struct {
    __in u32 DisplayHeight;
     __in u64 application_id;
    __in u32 DARWidth;
     __in u64 priority;
    __in u32 DARHeight;
     __in u64 timeslice;
    __in u32 ColorFormat;
    __in u32 ColorSpace[8];
    __in u32 ColorSpace_size;
    __in u32 SurfaceLayout[8];
    __in u32 SurfaceLayout_size;
    __in u8  ErrorString[64];      // must be "Error detected = 0x1000000"
     __in u32 VideoDecState;
     __in u8  VideoLog[3712];
     __in u32 VideoLog_size;
   };
   };


== /dev/nvhost-as-gpu ==
=== NVSCHED_CTRL_REMOVE_APPLICATION ===
Each fd opened to this device creates an address space. An address space is then later bound with a channel.
Removes the application from the scheduler.
 
  struct {
    __in u64 application_id;
  };


Once a nvgpu channel has been bound to an address space it cannot be unbound. There is no support for allowing an nvgpu channel to change from one address space to another (or from one to none).
=== NVSCHED_CTRL_GET_ID ===
                                                                                                                             
Returns the ID of the last scheduled object.
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL]]
|-
| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE]]
|-
| 0xC0104103 || Inout || 16 || [[#NVGPU_AS_IOCTL_FREE_SPACE]]
|-
| 0xC0184104 || Inout || 24 || [[#NVGPU_AS_IOCTL_MAP_BUFFER]]
|-
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
|-
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
|-
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]
|-
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS]]
|-
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
|}
 
=== NVGPU_AS_IOCTL_BIND_CHANNEL ===
Identical to Linux driver.


   struct {
   struct {
     __in u32 channel_fd;
     __out u64 id;
   };
   };


=== NVGPU_AS_IOCTL_ALLOC_SPACE ===
=== NVSCHED_CTRL_ADD_RUNLIST ===
Reserves pages in the device address space.
Creates a new runlist and returns it's ID.


   struct {
   struct {
     __in u32 pages;
     __out u64 runlist_id;
    __in u32 page_size;
    __in u32 flags;
    u32      padding;
    union {
      __out u64 offset;
      __in  u64 align;
    };
   };
   };


=== NVGPU_AS_IOCTL_FREE_SPACE ===
=== NVSCHED_CTRL_UPDATE_RUNLIST ===
Frees pages from the device address space.
Updates the runlist parameters in the scheduler.


   struct {
   struct {
     __in u64 offset;
     __in u64 runlist_id;
     __in u32 pages;
     __in u64 priority;
     __in u32 page_size;
     __in u64 timeslice;
   };
   };


=== NVGPU_AS_IOCTL_MAP_BUFFER ===
=== NVSCHED_CTRL_LINK_RUNLIST ===
Maps a memory region in the device address space.
Links a runlist to a given application in the scheduler.


Unaligned size will cause a [[#Panic]].
  struct {
    __in u64 runlist_id;
    __in u64 application_id;
  };


On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
=== NVSCHED_CTRL_UNLINK_RUNLIST ===
Unlinks a runlist from a given application in the scheduler.


   struct {
   struct {
     __in   u32 flags;        // bit0: fixed_offset, bit2: cacheable
     __in u64 runlist_id;
    u32        reserved0;
     __in u64 application_id;
    __in    u32 mem_id;      // nvmap handle
    u32        reserved1;
     union {
      __out u64 offset;
      __in u64 align;
    };
   };
   };


=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
=== NVSCHED_CTRL_REMOVE_RUNLIST ===
Maps a memory region in the device address space with extra params.
Removes the runlist from the scheduler.


Unaligned size will cause a [[#Panic]].
  struct {
    __in u64 runlist_id;
  };


On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
=== NVSCHED_CTRL_HAS_OVERRUN_EVENT ===
Returns a boolean to tell if the scheduler has an overrun event or not.


   struct {
   struct {
     __in      u32 flags;         // bit0: fixed_offset, bit2: cacheable
     __out u8 has_overrun;
    __inout   u32 kind;           // -1 is default
   };
    __in      u32 mem_id;        // nvmap handle
 
    u32          reserved;
=== NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT ===
     __in      u64 buffer_offset;
Returns the overrun event's data from the scheduler.
     __in      u64 mapping_size;
 
     union {
  struct {
      __out   u64 offset;
     __out u64 runlist_id;
      __in    u64 align;
     __out u64 debt;
    };
     __out u64 unk0;           // 3.0.0+ only
    __out u64 unk1;           // 3.0.0+ only
   };
   };


=== NVGPU_AS_IOCTL_UNMAP_BUFFER ===
=== NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE ===
Unmaps a memory region from the device address space.
Installs a fence swap event?


struct {
  struct {
     __in u64 offset;
     __in u32 fence_id;
    __in u32 fence_value;
    __in u32 swap_interval;
   };
   };


=== NVGPU_AS_IOCTL_ALLOC_AS ===
=== NVSCHED_CTRL_DETACH_APPLICATION ===
Nintendo's custom implementation for allocating an address space.
Places the given application in detached state.


   struct {
   struct {
    __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
     __in u64 application_id;
    __in s32 as_fd;          // ignored; passes 0
     __in u64 reserved;        // ignored; passes 0
   };
   };


=== NVGPU_AS_IOCTL_GET_VA_REGIONS ===
== /dev/nverpt-ctrl ==
Nintendo's custom implementation to get rid of pointer in struct.
Added in firmware version 3.0.0.


Uses [[#Ioctl3|Ioctl3]].
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA]]
|-
| 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]]
|}


  struct va_region {
=== NVERPT_TELEMETRY_SUBMIT_DATA ===
    u64 offset;
Sends test data for creating a new [[Error_Report_services|Error Report]].
    u32 page_size;
    u32 reserved;
    u64 pages;
  };
 
  struct {
    u64          buf_addr;    // (contained output user ptr on linux, ignored)
    __inout u32  buf_size;    // forced to 2*sizeof(struct va_region)
    u32          reserved;
    __out struct  va_region regions[2];
  };
 
=== NVGPU_AS_IOCTL_ALLOC_AS_EX ===
Nintendo's custom implementation for allocating an address space with extra params.


   struct {
   struct {
     __in u32 big_page_size;   // depends on GPU's available_big_page_sizes; 0=default
    __in u64 TestU64;
     __in s32 as_fd;           // ignored; passes 0
     __in u32 TestU32;
     __in u32 flags;           // passes 0
    __in u8  padding0[4];
     __in u32 reserved;       // ignored; passes 0
    __in s64 TestI64;
     __in u64 va_range_start;
     __in s32 TestI32;
     __in u64 va_range_end;
    __in u8  TestString[32];
     __in u64 va_range_split;
    __in u8  TestU8Array[8];
     __in u32 TestU8Array_size;
     __in u32 TestU32Array[8];
    __in u32 TestU32Array_size;
     __in u64 TestU64Array[8];
     __in u32 TestU64Array_size;
    __in s32 TestI32Array[8];
    __in u32 TestI32Array_size;
    __in s64 TestI64Array[8];
    __in u32 TestI64Array_size;
    __in u16 TestU16;
    __in u8  TestU8;
    __in s16 TestI16;
    __in s8  TestI8;
     __in u8  padding1[5];
   };
   };


=== NVGPU_AS_IOCTL_MAP_BUFFER_EX2 ===
=== NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA ===
Maps a memory region in the device address space with extra params.
Sends display data for creating a new [[Error_Report_services|Error Report]].


Unaligned size will cause a [[#Panic]].
  struct {
    __in u32 CodecType;
    __in u32 DecodeBuffers;
    __in u32 FrameWidth;
    __in u32 FrameHeight;
    __in u8  ColorPrimaries;
    __in u8  TransferCharacteristics;
    __in u8  MatrixCoefficients;
    __in u8  padding;
    __in u32 DisplayWidth;
    __in u32 DisplayHeight;
    __in u32 DARWidth;
    __in u32 DARHeight;
    __in u32 ColorFormat;
    __in u32 ColorSpace[8];
    __in u32 ColorSpace_size;
    __in u32 SurfaceLayout[8];
    __in u32 SurfaceLayout_size;
    __in u8  ErrorString[64];      // must be "Error detected = 0x1000000"
    __in u32 VideoDecState;
    __in u8  VideoLog[3712];
    __in u32 VideoLog_size;
  };


On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
== /dev/nvhost-as-gpu ==
Each fd opened to this device creates an address space. An address space is then later bound with a channel.


  struct {
Once a nvgpu channel has been bound to an address space it cannot be unbound. There is no support for allowing an nvgpu channel to change from one address space to another (or from one to none).
    __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
                                                                                                                             
    __inout  u32 kind;          // -1 is default
{| class="wikitable" border="1"
    __in      u32 mem_id;        // nvmap handle
! Value || Direction || Size || Description
    u32          reserved0;
|-
    __in      u64 buffer_offset;
| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL]]
    __in      u64 mapping_size;
|-
    union {
| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE]]
      __out  u64 offset;
|-
      __in    u64 align;
| 0xC0104103 || Inout || 16 || [[#NVGPU_AS_IOCTL_FREE_SPACE]]
    };
|-
    __in      u64 vma_addr;
| 0xC0184104 || Inout || 24 || [[#NVGPU_AS_IOCTL_MAP_BUFFER]]
    __in      u32 pages;
|-
    u32          reserved1;
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
  };
|-
 
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
=== NVGPU_AS_IOCTL_REMAP ===
|-
Nintendo's custom implementation of address space remapping for sparse pages.
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]
|-
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS]]
|-
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
|}
 
=== NVGPU_AS_IOCTL_BIND_CHANNEL ===
Identical to Linux driver.


   struct remap_op {
   struct {
    __in u16 flags;                      // bit2: cacheable
     __in u32 channel_fd;
    __in u16 kind;         
    __in u32 mem_handle;
    __in u32 mem_offset_in_pages;
    __in u32 virt_offset_in_pages;      // (alloc_space_offset >> 0x10)
     __in u32 num_pages;                 // alloc_space_pages
   };
   };
struct {
    __in struct remap_op entries[];
};


== /dev/nvhost-dbg-gpu ==
=== NVGPU_AS_IOCTL_ALLOC_SPACE ===
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.
Reserves pages in the device address space.


{| class="wikitable" border="1"
  struct {
! Value || Direction || Size || Description
    __in u32 pages;
|-
    __in u32 page_size;
| 0x40084401 || In || 8 || NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL
    __in u32 flags;
|-
    u32      padding;
| 0xC0??4402 || Inout || Variable || NVGPU_DBG_GPU_IOCTL_REG_OPS
    union {
|-
      __out u64 offset;
| 0x40084403 || In || 8 || NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL
      __in  u64 align;
|-
    };
| 0x40044404 || In || 4 || NVGPU_DBG_GPU_IOCTL_POWERGATE
  };
|-
 
| 0x40044405 || In || 4 || NVGPU_DBG_GPU_IOCTL_SMPC_CTXSW_MODE
=== NVGPU_AS_IOCTL_FREE_SPACE ===
|-
Frees pages from the device address space.
| 0x40044406 || In || 4 || NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_ALL_SMS
 
|-
  struct {
| 0xC0184407 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_PERFBUF_MAP
    __in u64 offset;
|-
    __in u32 pages;
| 0x40084408 || In || 8 || NVGPU_DBG_GPU_IOCTL_PERFBUF_UNMAP
    __in u32 page_size;
|-
  };
| 0x40084409 || In || 8 || NVGPU_DBG_GPU_IOCTL_PC_SAMPLING
 
|-
=== NVGPU_AS_IOCTL_MAP_BUFFER ===
| 0x4008440A || In || 8 || NVGPU_DBG_GPU_IOCTL_TIMEOUT
Maps a memory region in the device address space.
|-
 
| 0x8008440B || Out || 8 || NVGPU_DBG_GPU_IOCTL_GET_TIMEOUT
Unaligned size will cause a [[#Panic]].
|-
 
| 0x8004440C || Out || 4 || NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT_SIZE
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
|-
 
| 0x0000440D || None || 0 || [[#NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT]]
  struct {
|-
    __in    u32 flags;        // bit0: fixed_offset, bit2: cacheable
| 0xC018440E || Inout || 24 || NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
    u32        reserved0;
|-
    __in    u32 mem_id;      // nvmap handle
| 0xC018440F || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PDES
    u32        reserved1;
|-
    union {
| 0xC0104410 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES]]
      __out u64 offset;
|-
      __in  u64 align;
| 0xC0184411 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PTES
    };
|-
  };
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
 
|-
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
| 0xC0684413 || Inout || 104 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
Maps a memory region in the device address space with extra params.
|-
 
| 0xC0184414 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
Unaligned size will cause a [[#Panic]].
|-
 
| 0xC0184415 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
|-
 
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
  struct {
|-
    __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
| 0xC0104417 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_COMPTAGS
    __inout  u32 kind;          // -1 is default
|-
    __in      u32 mem_id;        // nvmap handle
| 0xC0104418 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_PA
    u32          reserved;
|-
    __in      u64 buffer_offset;
| 0xC0104419 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_PA
    __in      u64 mapping_size;
|-
    union {
| 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA
      __out  u64 offset;
|-
      __in    u64 align;
| 0xC020441B || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA_EX
    };
|-
  };
| 0xC084441C || Inout || 132 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SETTINGS
|-
| 0xC018441D || Inout || 24 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SERIAL_NUMBER
|-
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
|}


=== NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT ===
=== NVGPU_AS_IOCTL_UNMAP_BUFFER ===
Uses [[#Ioctl3|Ioctl3]].
Unmaps a memory region from the device address space.


=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES ===
struct {
Uses [[#Ioctl3|Ioctl3]].
    __in u64 offset;
  };


=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES ===
=== NVGPU_AS_IOCTL_ALLOC_AS ===
Uses [[#Ioctl3|Ioctl3]].
Nintendo's custom implementation for allocating an address space.


=== NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS ===
  struct {
Uses [[#Ioctl3|Ioctl3]].
    __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
    __in s32 as_fd;          // ignored; passes 0
    __in u64 reserved;        // ignored; passes 0
  };


=== NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS ===
=== NVGPU_AS_IOCTL_GET_VA_REGIONS ===
Uses [[#Ioctl2|Ioctl2]].
Nintendo's custom implementation to get rid of pointer in struct.


== /dev/nvhost-prof-gpu ==
Uses [[#Ioctl3|Ioctl3]].
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.
 
This device is identical to [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]].
 
== /dev/nvhost-ctrl-gpu ==
This device is for global (context independent) operations on the gpu. 
                                                                                                                                             
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0x80044701 || Out || 4 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE]]
|-
| 0x80284702 || Out || 40 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_INFO]]
|-
| 0x402C4703 || In || 44 || [[#NVGPU_GPU_IOCTL_ZBC_SET_TABLE]]
|-
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
|-
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
|-
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
|-
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
|-
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]
|-
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
|-
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
|-
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
|-
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
|-
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
|-
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
|-
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
|-
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
|-
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
|-
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
|-
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
|-
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
|-
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
|-
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
|-
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
|-
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|}
 
=== NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE ===
Returns the GPU's ZCULL context size. Identical to Linux driver.


  struct va_region {
    u64 offset;
    u32 page_size;
    u32 reserved;
    u64 pages;
  };
 
  struct {
    u64          buf_addr;    // (contained output user ptr on linux, ignored)
    __inout u32  buf_size;    // forced to 2*sizeof(struct va_region)
    u32          reserved;
    __out struct  va_region regions[2];
  };
=== NVGPU_AS_IOCTL_ALLOC_AS_EX ===
Nintendo's custom implementation for allocating an address space with extra params.
  struct {
    __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
    __in s32 as_fd;          // ignored; passes 0
    __in u32 flags;          // passes 0
    __in u32 reserved;        // ignored; passes 0
    __in u64 va_range_start;
    __in u64 va_range_end;
    __in u64 va_range_split;
  };
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX2 ===
Maps a memory region in the device address space with extra params.
Unaligned size will cause a [[#Panic]].
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
  struct {
    __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
    __inout  u32 kind;          // -1 is default
    __in      u32 mem_id;        // nvmap handle
    u32          reserved0;
    __in      u64 buffer_offset;
    __in      u64 mapping_size;
    union {
      __out  u64 offset;
      __in    u64 align;
    };
    __in      u64 vma_addr;
    __in      u32 pages;
    u32          reserved1;
  };
=== NVGPU_AS_IOCTL_REMAP ===
Nintendo's custom implementation of address space remapping for sparse pages.
  struct remap_op {
    __in u16 flags;                      // bit2: cacheable
    __in u16 kind;         
    __in u32 mem_handle;
    __in u32 mem_offset_in_pages;
    __in u32 virt_offset_in_pages;      // (alloc_space_offset >> 0x10)
    __in u32 num_pages;                  // alloc_space_pages
  };
  struct {
  struct {
     __out u32 size;
     __in struct remap_op entries[];
  };
};


=== NVGPU_GPU_IOCTL_ZCULL_GET_INFO ===
== /dev/nvhost-dbg-gpu ==
Returns GPU's ZCULL information. Identical to Linux driver.
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.


struct {
{| class="wikitable" border="1"
    __out u32 width_align_pixels;
! Value || Direction || Size || Description
    __out u32 height_align_pixels;
|-
    __out u32 pixel_squares_by_aliquots;
| 0x40084401 || In || 8 || NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL
    __out u32 aliquot_total;
|-
    __out u32 region_byte_multiplier;
| 0xC0??4402 || Inout || Variable || NVGPU_DBG_GPU_IOCTL_REG_OPS
    __out u32 region_header_size;
|-
    __out u32 subregion_header_size;
| 0x40084403 || In || 8 || NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL
    __out u32 subregion_width_align_pixels;
|-
    __out u32 subregion_height_align_pixels;
| 0x40044404 || In || 4 || NVGPU_DBG_GPU_IOCTL_POWERGATE
    __out u32 subregion_count;
|-
  };
| 0x40044405 || In || 4 || NVGPU_DBG_GPU_IOCTL_SMPC_CTXSW_MODE
 
|-
=== NVGPU_GPU_IOCTL_ZBC_SET_TABLE ===
| 0x40044406 || In || 4 || NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_ALL_SMS
Sets the active ZBC table. Identical to Linux driver.
|-
 
| 0xC0184407 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_PERFBUF_MAP
struct {
|-
    __in u32 color_ds[4];
| 0x40084408 || In || 8 || NVGPU_DBG_GPU_IOCTL_PERFBUF_UNMAP
    __in u32 color_l2[4];
|-
    __in u32 depth;
| 0x40084409 || In || 8 || NVGPU_DBG_GPU_IOCTL_PC_SAMPLING
    __in u32 format;
|-
    __in u32 type;        // 1=color, 2=depth
| 0x4008440A || In || 8 || NVGPU_DBG_GPU_IOCTL_TIMEOUT
  };
|-
 
| 0x8008440B || Out || 8 || NVGPU_DBG_GPU_IOCTL_GET_TIMEOUT
=== NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE ===
|-
Queries the active ZBC table. Identical to Linux driver.
| 0x8004440C || Out || 4 || NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT_SIZE
 
|-
struct {
| 0x0000440D || None || 0 || [[#NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT]]
    __out u32 color_ds[4];
|-
    __out u32 color_l2[4];
| 0xC018440E || Inout || 24 || NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
    __out u32 depth;
|-
    __out u32 ref_cnt;
| 0xC018440F || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PDES
    __out u32 format;
|-
    __out u32 type;
| 0xC0104410 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES]]
    __inout u32 index_size;
|-
  };
| 0xC0184411 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PTES
 
|-
=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.
|-
 
| 0xC0684413 || Inout || 104 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
|-
 
| 0xC0184414 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
  struct gpu_characteristics {
|-
    u32 arch;                      // 0x120 (NVGPU_GPU_ARCH_GM200)
| 0xC0184415 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
    u32 impl;                      // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
|-
    u32 rev;                        // 0xA1 (Revision A1)
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
    u32 num_gpc;                    // 0x1
|-
    u64 l2_cache_size;              // 0x40000
| 0xC0104417 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_COMPTAGS
    u64 on_board_video_memory_size; // 0x0 (not used)
|-
    u32 num_tpc_per_gpc;            // 0x2
| 0xC0104418 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_PA
    u32 bus_type;                  // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
|-
    u32 big_page_size;              // 0x20000
| 0xC0104419 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_PA
    u32 compression_page_size;      // 0x20000
|-
    u32 pde_coverage_bit_count;    // 0x1B
| 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA
    u32 available_big_page_sizes;  // 0x30000
|-
    u32 gpc_mask;                  // 0x1
| 0xC020441B || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA_EX
    u32 sm_arch_sm_version;        // 0x503 (Maxwell Generation 5.0.3)
|-
    u32 sm_arch_spa_version;        // 0x503 (Maxwell Generation 5.0.3)
| 0xC084441C || Inout || 132 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SETTINGS
    u32 sm_arch_warp_count;        // 0x80
|-
    u32 gpu_va_bit_count;          // 0x28
| 0xC018441D || Inout || 24 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SERIAL_NUMBER
    u32 reserved;                  // NULL
|-
    u64 flags;                      // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
    u32 twod_class;                // 0x902D (FERMI_TWOD_A)
|}
    u32 threed_class;              // 0xB197 (MAXWELL_B)
 
    u32 compute_class;              // 0xB1C0 (MAXWELL_COMPUTE_B)
=== NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT ===
    u32 gpfifo_class;              // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
Uses [[#Ioctl3|Ioctl3]].
    u32 inline_to_memory_class;    // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
 
    u32 dma_copy_class;            // 0xB0B5 (MAXWELL_DMA_COPY_A)
=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES ===
    u32 max_fbps_count;            // 0x1
Uses [[#Ioctl3|Ioctl3]].
    u32 fbp_en_mask;                // 0x0 (disabled)
    u32 max_ltc_per_fbp;            // 0x2
    u32 max_lts_per_ltc;            // 0x1
    u32 max_tex_per_tpc;            // 0x0 (not supported)
    u32 max_gpc_count;              // 0x1
    u32 rop_l2_en_mask_0;          // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
    u32 rop_l2_en_mask_1;          // 0x0
    u64 chipname;                  // 0x6230326D67 ("gm20b")
    u64 gr_compbit_store_base_hw;  // 0x0 (not supported)
  };
  struct {
    __inout u64 gpu_characteristics_buf_size;  // must not be NULL, but gets overwritten with 0xA0=max_size
    __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
    __out struct gpu_characteristics gc;
  };


=== NVGPU_GPU_IOCTL_GET_TPC_MASKS ===
=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES ===
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer.
Uses [[#Ioctl3|Ioctl3]].


[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
=== NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS ===
Uses [[#Ioctl3|Ioctl3]].


  struct {
=== NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS ===
    __in u32 mask_buf_size;      // ignored, but must not be NULL
Uses [[#Ioctl2|Ioctl2]].
    __in u32 reserved[3];
    __out u64 mask_buf;          // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
  };


=== NVGPU_GPU_IOCTL_FLUSH_L2 ===
== /dev/nvhost-prof-gpu ==
Flushes the GPU L2 cache.
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.


  struct {
This device is identical to [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]].
    __in u32 flush;          // l2_flush | l2_invalidate << 1 | fb_flush << 2
    __in u32 reserved;
  };


=== NVGPU_GPU_IOCTL_INVAL_ICACHE ===
== /dev/nvhost-ctrl-gpu ==
Invalidates the GPU instruction cache. Identical to Linux driver.
This device is for global (context independent) operations on the gpu.
 
                                                                                                                                             
  struct {
{| class="wikitable" border="1"
    __in s32 channel_fd;
! Value || Direction || Size || Description
    __in u32 reserved;
|-
  };
| 0x80044701 || Out || 4 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE]]
 
|-
=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE ===
| 0x80284702 || Out || 40 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_INFO]]
Sets the GPU MMU debug mode. Identical to Linux driver.
|-
 
| 0x402C4703 || In || 44 || [[#NVGPU_GPU_IOCTL_ZBC_SET_TABLE]]
  struct {
|-
    __in u32 state;
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
    __in u32 reserved;
|-
  };
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
 
|-
=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE ===
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
Sets the GPU SM debug mode. Identical to Linux driver.
|-
 
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
  struct {
|-
    __in s32 channel_fd;
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]
    __in u32 enable;
|-
    __in u64 sms;
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
  };
|-
 
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
|-
Waits until all valid warps on the GPU SM are paused and returns their current state.
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
 
|-
  struct {
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
    __in u64 pwarpstate;
|-
  };
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
 
|-
[6.1.0+] This command was modified to return inline data instead of using a pointer.
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
 
|-
  struct {
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
    __out u64 sm0_valid_warps;
|-
    __out u64 sm0_trapped_warps;
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
    __out u64 sm0_paused_warps;
|-
    __out u64 sm1_valid_warps;
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
    __out u64 sm1_trapped_warps;
|-
    __out u64 sm1_paused_warps;
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
  };
|-
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
|-
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
|-
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
|-
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
|-
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
|-
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|}


=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
=== NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE ===
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.
Returns the GPU's ZCULL context size. Identical to Linux driver.


  struct {
struct {
     __out u64 tpc_exception_en_sm_mask;
     __out u32 size;
   };
   };


=== NVGPU_GPU_IOCTL_NUM_VSMS ===
=== NVGPU_GPU_IOCTL_ZCULL_GET_INFO ===
Returns the number of GPU SM units present. Identical to Linux driver.
Returns GPU's ZCULL information. Identical to Linux driver.


  struct {
struct {
     __out u32 num_vsms;
     __out u32 width_align_pixels;
     __out u32 reserved;
     __out u32 height_align_pixels;
    __out u32 pixel_squares_by_aliquots;
    __out u32 aliquot_total;
    __out u32 region_byte_multiplier;
    __out u32 region_header_size;
    __out u32 subregion_header_size;
    __out u32 subregion_width_align_pixels;
    __out u32 subregion_height_align_pixels;
    __out u32 subregion_count;
   };
   };


=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
=== NVGPU_GPU_IOCTL_ZBC_SET_TABLE ===
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.
Sets the active ZBC table. Identical to Linux driver.


  struct {
struct {
     __out u8 sm0_gpc_index;
     __in u32 color_ds[4];
     __out u8 sm0_tpc_index;
     __in u32 color_l2[4];
     __out u8 sm1_gpc_index;
     __in u32 depth;
     __out u8 sm1_tpc_index;
     __in u32 format;
    __in u32 type;        // 1=color, 2=depth
   };
   };


=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
=== NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE ===
Returns the mask value for a ZBC slot.
Queries the active ZBC table. Identical to Linux driver.


  struct {
struct {
     __out u32 slot;       // always 0x07
     __out u32 color_ds[4];
     __out u32 mask;
     __out u32 color_l2[4];
    __out u32 depth;
    __out u32 ref_cnt;
    __out u32 format;
    __out u32 type;
    __inout u32 index_size;
   };
   };


=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
Returns the GPU load value from the PMU.
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.


  struct {
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
    __out u32 pmu_gpu_load;
  };
 
=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
Sets the clock gate control value.
 
  struct {
    __in u32 cg_mask;
    __in u32 cg_value;
  };
 
=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
Returns the clock gate control value.
 
  struct {
    __in u32 cg_mask;
    __out u32 cg_value;
  };
 
=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
Sets the power gate control value.


  struct gpu_characteristics {
    u32 arch;                      // 0x120 (NVGPU_GPU_ARCH_GM200)
    u32 impl;                      // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
    u32 rev;                        // 0xA1 (Revision A1)
    u32 num_gpc;                    // 0x1
    u64 l2_cache_size;              // 0x40000
    u64 on_board_video_memory_size; // 0x0 (not used)
    u32 num_tpc_per_gpc;            // 0x2
    u32 bus_type;                  // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
    u32 big_page_size;              // 0x20000
    u32 compression_page_size;      // 0x20000
    u32 pde_coverage_bit_count;    // 0x1B
    u32 available_big_page_sizes;  // 0x30000
    u32 gpc_mask;                  // 0x1
    u32 sm_arch_sm_version;        // 0x503 (Maxwell Generation 5.0.3)
    u32 sm_arch_spa_version;        // 0x503 (Maxwell Generation 5.0.3)
    u32 sm_arch_warp_count;        // 0x80
    u32 gpu_va_bit_count;          // 0x28
    u32 reserved;                  // NULL
    u64 flags;                      // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
    u32 twod_class;                // 0x902D (FERMI_TWOD_A)
    u32 threed_class;              // 0xB197 (MAXWELL_B)
    u32 compute_class;              // 0xB1C0 (MAXWELL_COMPUTE_B)
    u32 gpfifo_class;              // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
    u32 inline_to_memory_class;    // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
    u32 dma_copy_class;            // 0xB0B5 (MAXWELL_DMA_COPY_A)
    u32 max_fbps_count;            // 0x1
    u32 fbp_en_mask;                // 0x0 (disabled)
    u32 max_ltc_per_fbp;            // 0x2
    u32 max_lts_per_ltc;            // 0x1
    u32 max_tex_per_tpc;            // 0x0 (not supported)
    u32 max_gpc_count;              // 0x1
    u32 rop_l2_en_mask_0;          // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
    u32 rop_l2_en_mask_1;          // 0x0
    u64 chipname;                  // 0x6230326D67 ("gm20b")
    u64 gr_compbit_store_base_hw;  // 0x0 (not supported)
  };
   struct {
   struct {
     __in u32 pg_mask;
    __inout u64 gpu_characteristics_buf_size;  // must not be NULL, but gets overwritten with 0xA0=max_size
     __in u32 pg_value;
     __in   u64 gpu_characteristics_buf_addr;   // ignored, but must not be NULL
     __out struct gpu_characteristics gc;
   };
   };


=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
=== NVGPU_GPU_IOCTL_GET_TPC_MASKS ===
Returns the power gate control value.
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer.
 
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].


   struct {
   struct {
     __in u32 pg_mask;
     __in u32 mask_buf_size;      // ignored, but must not be NULL
     __out u32 pg_value;
    __in u32 reserved[3];
     __out u64 mask_buf;           // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
   };
   };


=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
=== NVGPU_GPU_IOCTL_FLUSH_L2 ===
Returns the GPU PMU ELPG residency gating values.
Flushes the GPU L2 cache.


   struct {
   struct {
     __out u64 pg_ingating_time_us;
     __in u32 flush;         // l2_flush | l2_invalidate << 1 | fb_flush << 2
     __out u64 pg_ungating_time_us;
     __in u32 reserved;
    __out u64 pg_gating_cnt;
   };
   };


=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
=== NVGPU_GPU_IOCTL_INVAL_ICACHE ===
Returns user specific data from the error channel, if one exists.
Invalidates the GPU instruction cache. Identical to Linux driver.


   struct {
   struct {
     __out u64 data;
     __in s32 channel_fd;
    __in u32 reserved;
   };
   };


=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE ===
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.
Sets the GPU MMU debug mode. Identical to Linux driver.


   struct {
   struct {
     __out u64 gpu_timestamp;     // raw GPU counter (PTIMER) value
     __in u32 state;
     __out u64 reserved;
     __in u32 reserved;
   };
   };


=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE ===
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.
Sets the GPU SM debug mode. Identical to Linux driver.


struct time_correlation_sample {
  struct {
  u64 cpu_timestamp;                                 // from CPU's CNTPCT_EL0 register
    __in s32 channel_fd;
  u64 gpu_timestamp;                                 // from GPU's PTIMER registers
    __in u32 enable;
};
    __in u64 sms;
  };
struct {
 
  __out struct time_correlation_sample samples[16];  // timestamp pairs
=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
  __in u32     count;                                // number of pairs to read
Waits until all valid warps on the GPU SM are paused and returns their current state.
  __in u32    source_id;                             // cpu clock source id (must be 1)
 
};
  struct {
     __in u64 pwarpstate;
  };


= Channels =
[6.1.0+] This command was modified to return inline data instead of using a pointer.
Channels are a concept for NVIDIA hardware blocks that share a common interface.


{| class="wikitable" border="1"
  struct {
! Path || Name
    __out u64 sm0_valid_warps;
|-
    __out u64 sm0_trapped_warps;
| /dev/nvhost-gpu || GPU
    __out u64 sm0_paused_warps;
|-
    __out u64 sm1_valid_warps;
| /dev/nvhost-msenc || Video Encoder
    __out u64 sm1_trapped_warps;
|-
    __out u64 sm1_paused_warps;
| /dev/nvhost-nvdec || Video Decoder
  };
|-
 
| /dev/nvhost-nvjpg || JPEG Decoder
=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
|-
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.
| /dev/nvhost-vic || Video Image Compositor
 
|-
  struct {
| /dev/nvhost-display || Display
    __out u64 tpc_exception_en_sm_mask;
|}
  };


== Ioctls ==
=== NVGPU_GPU_IOCTL_NUM_VSMS ===
{| class="wikitable" border="1"
Returns the number of GPU SM units present. Identical to Linux driver.
! Value || Size || Description
 
|-
  struct {
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
    __out u32 num_vsms;
|-
    __out u32 reserved;
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
  };
|-
 
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
|-
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
 
|-
  struct {
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
    __out u8 sm0_gpc_index;
|-
    __out u8 sm0_tpc_index;
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
    __out u8 sm1_gpc_index;
|-
    __out u8 sm1_tpc_index;
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
  };
|-
 
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
|-
Returns the mask value for a ZBC slot.
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
 
|-
  struct {
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
    __out u32 slot;      // always 0x07
|-
    __out u32 mask;
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
  };
|-
 
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
|-
Returns the GPU load value from the PMU.
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
 
|- style="border-top: double"
  struct {
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
    __out u32 pmu_gpu_load;
|-
  };
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
 
|-
=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
Sets the clock gate control value.
|-
 
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
  struct {
|-
    __in u32 cg_mask;
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
    __in u32 cg_value;
|-
  };
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
 
|-
=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
Returns the clock gate control value.
|-
 
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
  struct {
|-
    __in u32 cg_mask;
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
    __out u32 cg_value;
|-
  };
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
 
|-
=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
Sets the power gate control value.
|-
 
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
  struct {
|-
    __in u32 pg_mask;
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
    __in u32 pg_value;
|-
  };
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
 
|-
=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
Returns the power gate control value.
|-
 
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
  struct {
|-
    __in u32 pg_mask;
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
    __out u32 pg_value;
|-
  };
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
 
|-
=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
Returns the GPU PMU ELPG residency gating values.
|-
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
|-
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
|-
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
|-
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
|-
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
|-
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
|- style="border-top: double"
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|}


=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
  struct {
Submits data to the channel.
    __out u64 pg_ingating_time_us;
    __out u64 pg_ungating_time_us;
    __out u64 pg_gating_cnt;
  };
 
=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
Returns user specific data from the error channel, if one exists.


  struct cmdbuf {
    u32 mem;
    u32 offset;
    u32 words;
  };
 
  struct reloc {
    u32 cmdbuf_mem;
    u32 cmdbuf_offset;
    u32 target;
    u32 target_offset;
  };
 
  struct reloc_shift {
    u32 shift;
  };
 
  struct syncpt_incr {
    u32 syncpt_id;
    u32 syncpt_incrs;
    u32 reserved[3];
  };
 
   struct {
   struct {
    __in    u32 num_cmdbufs;
     __out u64 data;
    __in    u32 num_relocs;
    __in    u32 num_syncpt_incrs;
    __in    u32 num_fences;
    __in    struct cmdbuf cmdbufs[];              // depends on num_cmdbufs
    __in    struct reloc relocs[];                // depends on num_relocs
    __in    struct reloc_shift reloc_shifts[];    // depends on num_relocs
    __in    struct syncpt_incr syncpt_incrs[];    // depends on num_syncpt_incrs
     __out   u32 fence_thresholds[];               // depends on num_fences
   };
   };


=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
Returns the current syncpoint value for a given module. Identical to Linux driver.
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.


   struct {
   struct {
     __in    u32 module_id;
     __out u64 gpu_timestamp;     // raw GPU counter (PTIMER) value
     __out   u32 syncpt_value;
     __out u64 reserved;
   };
   };


=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
Returns the current waitbase value for a given module. Always returns 0.
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.


  struct {
struct time_correlation_sample {
    __in   u32 module_id;
   u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register
    __out  u32 waitbase_value;
  u64 gpu_timestamp;                                  // from GPU's PTIMER registers
  };
};
struct {
  __out struct time_correlation_sample samples[16];   // timestamp pairs
  __in u32    count;                                // number of pairs to read
  __in u32     source_id;                             // cpu clock source id (must be 1)
};


=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
= Channels =
Stubbed. Does a debug print and returns 0.
Channels are a concept for NVIDIA hardware blocks that share a common interface.


=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
{| class="wikitable" border="1"
Sets the submit timeout value for the channel. Identical to Linux driver.
! Path || Name
|-
| /dev/nvhost-gpu || GPU
|-
| /dev/nvhost-msenc || Video Encoder
|-
| /dev/nvhost-nvdec || Video Decoder
|-
| /dev/nvhost-nvjpg || JPEG Decoder
|-
| /dev/nvhost-vic || Video Image Compositor
|-
| /dev/nvhost-display || Display
|-
| /dev/nvhost-tsec || TSEC
|}


  struct {
== Ioctls ==
    __in    u32 timeout;
{| class="wikitable" border="1"
  };
! Value || Size || Description
 
|-
=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
Sets the clock rate value for a given module. Identical to Linux driver.
|-
 
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
  struct {
|-
    __in    u32 clk_rate;
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
    __in    u32 module_id;
|-
  };
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
 
|-
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.
|-
 
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
  struct handle {
|-
    u32 handle_id_in;                // nvmap handle to map
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
    u32 phys_addr_out;                // returned device physical address mapped to the handle
|-
  };
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
|-
  struct {
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
    __in    u32 num_handles;          // number of nvmap handles to map
|-
    __in    u32 reserved;            // ignored
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
    __in    u8  is_compr;            // memory to map is compressed
|-
    __in    u8  padding[3];          // ignored
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
    __inout struct handle handles[];  // depends on num_handles
|-
  };
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
 
|-
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER ===
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
Uses '''nvmap_unpin''' internally to unpin a given number of nvmap handles from their device physical address.
|- style="border-top: double"
 
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
  struct handle {
|-
    u32 handle_id_in;                // nvmap handle to unmap
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
    u32 reserved;                    // ignored
|-
  };
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
|-
  struct {
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
    __in    u32 num_handles;          // number of nvmap handles to unmap
|-
    __in    u32 reserved;            // ignored
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
    __in    u8  is_compr;            // memory to unmap is compressed
|-
    __in    u8  padding[3];          // ignored
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
    __inout struct handle handles[];  // depends on num_handles
|-
  };
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
 
|-
=== NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX ===
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
Sets the global timeout value for the channel. Identical to Linux driver.
|-
 
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
  struct {
|-
    __in    u32 timeout;
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
    __in    u32 flags;
|-
  };
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
 
|-
=== NVHOST_IOCTL_CHANNEL_GET_CLK_RATE ===
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
Returns the clock rate value for a given module. Identical to Linux driver.
|-
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
|-
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
|-
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
|-
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
|-
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
|-
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
|-
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
|-
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
|-
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
|-
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
|-
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
|-
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
|-
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
|- style="border-top: double"
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|}


  struct {
=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
    __out  u32 clk_rate;
Submits data to the channel.
    __in    u32 module_id;
  };


=== NVHOST_IOCTL_CHANNEL_SUBMIT_EX ===
   struct cmdbuf {
Same as [[#NVHOST_IOCTL_CHANNEL_SUBMIT|NVHOST_IOCTL_CHANNEL_SUBMIT]].
     u32 mem;
 
    u32 offset;
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX ===
    u32 words;
Same as [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]], but calls '''nvmap_unpin''' internally in case of error.
 
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]].
 
=== NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD ===
Binds a nvmap object to this channel. Identical to Linux driver.
 
   struct {
     __in u32 nvmap_fd;
   };
   };
 
 
=== NVGPU_IOCTL_CHANNEL_SET_TIMEOUT ===
  struct reloc {
Sets the timeout value for the GPU channel. Identical to Linux driver.
    u32 cmdbuf_mem;
 
    u32 cmdbuf_offset;
    u32 target;
    u32 target_offset;
  };
 
  struct reloc_shift {
    u32 shift;
  };
 
  struct syncpt_incr {
    u32 syncpt_id;
    u32 syncpt_incrs;
    u32 reserved[3];
  };
 
   struct {
   struct {
     __in u32 timeout;
     __in   u32 num_cmdbufs;
    __in    u32 num_relocs;
    __in    u32 num_syncpt_incrs;
    __in    u32 num_fences;
    __in    struct cmdbuf cmdbufs[];              // depends on num_cmdbufs
    __in    struct reloc relocs[];                // depends on num_relocs
    __in    struct reloc_shift reloc_shifts[];    // depends on num_relocs
    __in    struct syncpt_incr syncpt_incrs[];    // depends on num_syncpt_incrs
    __out  u32 fence_thresholds[];                // depends on num_fences
   };
   };


=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO ===
=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
Allocates gpfifo entries. Identical to Linux driver.
Returns the current syncpoint value for a given module. Identical to Linux driver.


   struct {
   struct {
     __in u32 num_entries;
     __in   u32 module_id;
     __in u32 flags;
     __out  u32 syncpt_value;
   };
   };


=== NVGPU_IOCTL_CHANNEL_WAIT ===
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
Waits on channel. Identical to Linux driver.
Returns the current waitbase value for a given module. Always returns 0.


   struct {
   struct {
     __in u32 type;           // wait type (0=notifier, 1=semaphore)
     __in   u32 module_id;
     __in u32 timeout;         // wait timeout value
     __out  u32 waitbase_value;
    __in u32 dmabuf_fd;      // nvmap handle
    __in u32 offset;          // nvmap memory offset
    __in u32 payload;        // payload data (semaphore only)
    __in u32 padding;        // ignored
   };
   };


=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS ===
=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
Maps memory for the cycle stats buffer. Identical to Linux driver.
Stubbed. Does a debug print and returns 0.
 
=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
Sets the submit timeout value for the channel. Identical to Linux driver.


   struct {
   struct {
     __in u32 dmabuf_fd;   // nvmap handle
     __in   u32 timeout;
   };
   };


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO ===
=== NVHOST_IOCTL_CHANNEL_SET_CLK_RATE ===
Submits a gpfifo object. Modified to take inline entry objects instead of a pointer.
Sets the clock rate value for a given module. Identical to Linux driver.


   struct fence {
   struct {
     u32 id;
     __in    u32 clk_rate;
     u32 value;
     __in    u32 module_id;
   };
   };
 
 
   struct gpfifo_entry {
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER ===
     u32 entry0;                             // gpu_iova_lo
Uses '''nvmap_pin''' internally to pin a given number of nvmap handles to an appropriate device physical address.
     u32 entry1;                             // gpu_iova_hi | (allow_flush << 8) | (is_push_buf << 9) | (size << 10) | (sync << 31)
 
   struct handle {
     u32 handle_id_in;                 // nvmap handle to map
     u32 phys_addr_out;               // returned device physical address mapped to the handle
   };
   };
 
   struct {
   struct {
     __in    u64 gpfifo;                     // (ignored) pointer to gpfifo fence structs
     __in    u32 num_handles;         // number of nvmap handles to map
     __in    u32 num_entries;                 // number of fence objects being submitted
     __in    u32 reserved;             // ignored
     union {
     __in   u8 is_compr;             // memory to map is compressed
      __out u32 detailed_error;
     __in    u8  padding[3];           // ignored
      __in  u32 flags;
     __inout struct handle handles[]; // depends on num_handles
     };
    __inout struct fence fence_out;          // returned new fence object for others to wait on
     __in    struct gpfifo_entry entries[];   // depends on num_entries
   };
   };


=== NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX ===
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER ===
Allocates a graphics context object. Modified to ignore object's ID.
Uses '''nvmap_unpin''' internally to unpin a given number of nvmap handles from their device physical address.
 
You can only have one object context allocated at a time. You must have bound an address space before using this.


  struct handle {
    u32 handle_id_in;                // nvmap handle to unmap
    u32 reserved;                    // ignored
  };
   struct {
   struct {
     __in u32 class_num;    // 0x902D=2d, 0xB197=3d, 0xB1C0=compute, 0xA140=kepler, 0xB0B5=DMA, 0xB06F=channel_gpfifo
     __in   u32 num_handles;         // number of nvmap handles to unmap
     __in  u32 flags;       // bit0: LOCKBOOST_ZERO
    __in   u32 reserved;            // ignored
     __out u64 obj_id;       // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
     __in   u8 is_compr;             // memory to unmap is compressed
     __in    u8  padding[3];           // ignored
    __inout struct handle handles[];  // depends on num_handles
   };
   };


=== NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX ===
=== NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX ===
Frees a graphics context object. Not supported.
Sets the global timeout value for the channel. Identical to Linux driver.


   struct {
   struct {
     __in u64 obj_id;       // ignored
     __in   u32 timeout;
    __in    u32 flags;
   };
   };


=== NVGPU_IOCTL_CHANNEL_ZCULL_BIND ===
=== NVHOST_IOCTL_CHANNEL_GET_CLK_RATE ===
Binds a ZCULL context to the channel. Identical to Linux driver.
Returns the clock rate value for a given module. Identical to Linux driver.


struct {
  struct {
     __in u64 gpu_va;
     __out  u32 clk_rate;
     __in u32 mode;         // 0=global, 1=no_ctxsw, 2=separate_buffer, 3=part_of_regular_buf
     __in   u32 module_id;
    __in u32 reserved;
  };
  };
 
=== NVHOST_IOCTL_CHANNEL_SUBMIT_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_SUBMIT|NVHOST_IOCTL_CHANNEL_SUBMIT]].
 
=== NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]], but calls '''nvmap_unpin''' internally in case of error.
 
=== NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX ===
Same as [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER|NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]].


=== NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER ===
=== NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD ===
Initializes the error notifier for this channel. Unlike for the Linux kernel, the Switch driver cannot write to an arbitrary userspace buffer. Thus new ioctls have been introduced to fetch the error information rather than using a shared memory buffer.
Binds a nvmap object to this channel. Identical to Linux driver.


   struct {
   struct {
    __in u64 offset;  // ignored
     __in u32 nvmap_fd;
    __in u64 size;    // ignored
    __in u32 mem;      // must be non-zero to initialize, zero to de-initialize
     __in u32 reserved; // ignored
   };
   };


=== NVGPU_IOCTL_CHANNEL_SET_PRIORITY ===
=== NVGPU_IOCTL_CHANNEL_SET_TIMEOUT ===
Changes channel's priority. Identical to Linux driver.
Sets the timeout value for the GPU channel. Identical to Linux driver.


   struct {
   struct {
     __in u32 priority;   // 0x32 is low, 0x64 is medium and 0x96 is high
     __in u32 timeout;
   };
   };


=== NVGPU_IOCTL_CHANNEL_ENABLE ===
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO ===
Enables the current channel. Identical to Linux driver.
Allocates gpfifo entries. Identical to Linux driver.


=== NVGPU_IOCTL_CHANNEL_DISABLE ===
  struct {
Disables the current channel. Identical to Linux driver.
    __in u32 num_entries;
    __in u32 flags;          // bit0: vpr_enabled
  };


=== NVGPU_IOCTL_CHANNEL_PREEMPT ===
=== NVGPU_IOCTL_CHANNEL_WAIT ===
Clears the FIFO pipe for this channel. Identical to Linux driver.
Waits on channel. Identical to Linux driver.


=== NVGPU_IOCTL_CHANNEL_FORCE_RESET ===
  struct {
Forces the channel to reset. Identical to Linux driver.
    __in u32 type;            // wait type (0=notifier, 1=semaphore)
    __in u32 timeout;        // wait timeout value
    __in u32 dmabuf_fd;      // nvmap handle
    __in u32 offset;          // nvmap memory offset
    __in u32 payload;        // payload data (semaphore only)
    __in u32 padding;        // ignored
  };


=== NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL ===
=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS ===
Controls event notifications.
Maps memory for the cycle stats buffer. Identical to Linux driver.


   struct {
   struct {
     __in u32 cmd;   // 0=disable, 1=enable, 2=clear
     __in u32 dmabuf_fd;   // nvmap handle
    __in u32 id;    // same id's as for [[#QueryEvent]]
   };
   };


=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT ===
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO ===
Controls the cycle stats snapshot buffer. Identical to Linux driver.
Submits a gpfifo object. Modified to take inline entry objects instead of a pointer.


  struct fence {
    u32 id;
    u32 value;
  };
 
  struct gpfifo_entry {
    u32 entry0;                              // gpu_iova_lo
    u32 entry1;                              // gpu_iova_hi | (allow_flush << 8) | (is_push_buf << 9) | (size << 10) | (sync << 31)
  };
 
   struct {
   struct {
     __in    u32 cmd;         // command to handle (0=flush, 1=attach, 2=detach)
     __in    u64 gpfifo;                     // (ignored) pointer to gpfifo fence structs
     __in    u32 dmabuf_fd;   // nvmap handle
     __in    u32 num_entries;                 // number of fence objects being submitted
     __inout u32 extra;      // extra payload data/result
     union {
     __in    u32 padding;     // ignored
      __out u32 detailed_error;
       __in  u32 flags;                      // bit0: fence_wait, bit1: fence_get, bit2: hw_format, bit3: sync_fence, bit4: suppress_wfi, bit5: skip_buffer_refcounting
    };
    __inout struct fence fence_out;          // returned new fence object for others to wait on
     __in    struct gpfifo_entry entries[];   // depends on num_entries
   };
   };


=== NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO ===
=== NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX ===
Returns information on the current error notification caught by the error notifier. Exclusive to the Switch.
Allocates a graphics context object. Modified to ignore object's ID.
 
You can only have one object context allocated at a time. You must have bound an address space before using this.


   struct {
   struct {
     __out u32 error_info[32];    // first word is an error code (0=no_error, 1=gr_error, 2=gr_error, 3=invalid, 4=invalid)
     __in  u32 class_num;    // 0x902D=2d, 0xB197=3d, 0xB1C0=compute, 0xA140=kepler, 0xB0B5=DMA, 0xB06F=channel_gpfifo
    __in  u32 flags;        // bit0: LOCKBOOST_ZERO
    __out u64 obj_id;      // (ignored) used for FREE_OBJ_CTX ioctl, which is not supported
   };
   };


=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
=== NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX ===
Returns the current error notification caught by the error notifier. Exclusive to the Switch.
Frees a graphics context object. Not supported.


   struct {
   struct {
     __out u64 timestamp;    // fetched straight from armGetSystemTick
     __in u64 obj_id;      // ignored
    __out u32 info32;      // error code
    __out u16 info16;      // additional error info
    __out u16 status;      // always 0xFFFF
   };
   };


=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX ===
=== NVGPU_IOCTL_CHANNEL_ZCULL_BIND ===
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.
Binds a ZCULL context to the channel. Identical to Linux driver.


struct fence {
    u32 id;
    u32 value;
};
  struct {
  struct {
  __in   u32 num_entries;
    __in u64 gpu_va;
  __in   u32 num_jobs;
    __in u32 mode;         // 0=global, 1=no_ctxsw, 2=separate_buffer, 3=part_of_regular_buf
  __in    u32 flags;
    __in u32 reserved;
  __out  struct fence fence_out;          // returned new fence object for others to wait on
  };
  __in   u32 reserved[3];                 // ignored
};


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY ===
=== NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]].
Initializes the error notifier for this channel. Unlike for the Linux kernel, the Switch driver cannot write to an arbitrary userspace buffer. Thus new ioctls have been introduced to fetch the error information rather than using a shared memory buffer.


=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2 ===
  struct {
Same as [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]].
    __in u64 offset;  // ignored
    __in u64 size;    // ignored
    __in u32 mem;      // must be non-zero to initialize, zero to de-initialize
    __in u32 reserved; // ignored
  };


=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2 ===
=== NVGPU_IOCTL_CHANNEL_SET_PRIORITY ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]], but uses [[#Ioctl2|Ioctl2]].
Changes channel's priority. Identical to Linux driver.
 
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]], but uses [[#Ioctl2|Ioctl2]].
 
=== NVGPU_IOCTL_CHANNEL_SET_TIMESLICE ===
Changes channel's timeslice. Identical to Linux driver.


   struct {
   struct {
     __in u32 timeslice;
     __in u32 priority;   // 0x32 is low, 0x64 is medium and 0x96 is high
   };
   };


=== NVGPU_IOCTL_CHANNEL_SET_USER_DATA ===
=== NVGPU_IOCTL_CHANNEL_ENABLE ===
Sets user specific data.
Enables the current channel. Identical to Linux driver.


  struct {
=== NVGPU_IOCTL_CHANNEL_DISABLE ===
    __in u64 data;
Disables the current channel. Identical to Linux driver.
  };
 
 
=== NVGPU_IOCTL_CHANNEL_PREEMPT ===
=== NVGPU_IOCTL_CHANNEL_GET_USER_DATA ===
Clears the FIFO pipe for this channel. Identical to Linux driver.
Returns user specific data.
 
=== NVGPU_IOCTL_CHANNEL_FORCE_RESET ===
Forces the channel to reset. Identical to Linux driver.
 
=== NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL ===
Controls event notifications.


   struct {
   struct {
     __out u64 data;
     __in u32 cmd;   // 0=disable, 1=enable, 2=clear
    __in u32 id;    // same id's as for [[#QueryEvent]]
   };
   };


= NvDrvPermission =
=== NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT ===
This is "nns::nvdrv::NvDrvPermission".
Controls the cycle stats snapshot buffer. Identical to Linux driver.
 
  struct {
    __in    u32 cmd;        // command to handle (0=flush, 1=attach, 2=detach)
    __in    u32 dmabuf_fd;  // nvmap handle
    __inout u32 extra;      // extra payload data/result
    __in    u32 padding;    // ignored
  };


{| class="wikitable" border="1"
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO ===
!  Bits
Returns information on the current error notification caught by the error notifier. Exclusive to the Switch.
! Name
 
! Description
  struct {
|-
    __out u32 type;    // Error type (0=no_error, 1=mmu_error, 2=gr_error, 3=pbdma_error, 4=timeout)
| 0
    __out u32 info[31]; // Infor depends on the error type
| Gpu
  };
| Can access [[#Channels|/dev/nvhost-gpu]], [[#/dev/nvhost-ctrl-gpu|/dev/nvhost-ctrl-gpu]] and [[#/dev/nvhost-as-gpu|/dev/nvhost-as-gpu]].
 
==== GR Error Code Format ====
When <code>type == 2</code> (GR Error), the returned data is formatted as follows:
  struct {
    __out u32 type;      // 2=gr_error
    __out u32 intr_value; // Interrupt bits
    __out u32 addr;      // Register address (in bytes)
    __out u32 data_hi;    // Data high 32 bits
    __out u32 data_lo;    // Data low 32 bits
    __out u32 class_num;  // GPU class number (e.g., 0xb197 for MAXWELL_B)
  };
 
{| class="wikitable"
|+ GR Error Interrupt Bits
|-
! Bit(s)
! Description
|-
| 0
| GR_INTR_NOTIFY
|-
|-
| 1
| 1
| GpuDebug
| GR_INTR_SEMAPHORE
| Can access [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]] and [[#/dev/nvhost-prof-gpu|/dev/nvhost-prof-gpu]].
|-
|-
| 2
| 2
| GpuSchedule
| unknown
| Can access [[#/dev/nvsched-ctrl|/dev/nvsched-ctrl]].
|-
|-
| 3
| 3
| VIC
| unknown
| Can access [[#Channels|/dev/nvhost-vic]].
|-
|-
| 4
| 4
| VideoEncoder
| GR_INTR_ILLEGAL_METHOD
| Can access [[#Channels|/dev/nvhost-msenc]].
|-
|-
| 5
| 5
| VideoDecoder
| GR_INTR_ILLEGAL_CLASS
| Can access [[#Channels|/dev/nvhost-nvdec]].
|-
|-
| 6
| 6
| TSEC
| GR_INTR_ILLEGAL_NOTIFY
| Can access [[#Channels|/dev/nvhost-tsec]].
|-
|-
| 7
| 7
| JPEG
| unknown
| Can access [[#Channels|/dev/nvhost-nvjpg]].
|-
|-
| 8
| 8
| Display
| GR_INTR_FIRMWARE_METHOD
| Can access [[#Channels|/dev/nvhost-display]], [[#/dev/nvcec-ctrl|/dev/nvcec-ctrl]], [[#/dev/nvhdcp_up-ctrl|/dev/nvhdcp_up-ctrl]], [[#/dev/nvdisp-ctrl|/dev/nvdisp-ctrl]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp0]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp1]], [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp0]] and [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp1]].
|-
| 9–18
| unknown
|-
|-
| 9
| 19
| ImportMemory
| GR_INTR_FECS_ERROR
| Can duplicate [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
|-
| 10
| 20
| NoCheckedAruid
| GR_INTR_CLASS_ERROR
| Can use [[#SetAruidWithoutCheck|SetAruidWithoutCheck]].
|-
| 11
|
| Can use [[#SetGraphicsFirmwareMemoryMarginEnabled|SetGraphicsFirmwareMemoryMarginEnabled]].
|-
| 12
|
| Can duplicate exported [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
|-
| 13
| 21
|
| GR_INTR_EXCEPTION
| Can use the GPU virtual address range 0xC0000 to 0x580000 instead of 0x0 to 0xC0000.
|-
|-
| 14
| 22–31
|
| unknown
| Can use [[#NVMAP_IOC_EXPORT_FOR_ARUID|NVMAP_IOC_EXPORT_FOR_ARUID]] and [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID|NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]].
|-
| 15
|
| Can use the virtual address ranges 0x0 to 0x100000000 (GPU) and 0x0 to 0xE0000000 (non-GPU) instead of 0x100000000 to 0x11FA50000 (GPU) and 0xE0000000 to 0xFFFE0000 (non-GPU).
|}
|}


= NvError =
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
This is "nns::nvdrv::NvError".
Returns the current error notification caught by the error notifier. Exclusive to the Switch.


{| class="wikitable" border="1"
  struct {
|-
    __out u64 timestamp;    // fetched straight from armGetSystemTick
! Value || Name
    __out u32 info32;      // error code
|-
    __out u16 info16;      // additional error info
| 0x0 || Success
    __out u16 status;      // always 0xFFFF
|-
  };
| 0x1 || NotImplemented
 
|-
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX ===
| 0x2 || NotSupported
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.
|-
 
| 0x3 || NotInitialized
struct fence {
|-
    u32 id;
| 0x4 || BadParameter
    u32 value;
|-
};
| 0x5 || Timeout
|-
struct {
| 0x6 || InsufficientMemory
  __in    u32 num_entries;
|-
  __in    u32 num_jobs;
| 0x7 || ReadOnlyAttribute
  __in    u32 flags;                      // bit0: vpr_enabled
|-
  __out  struct fence fence_out;          // returned new fence object for others to wait on
| 0x8 || InvalidState
  __in    u32 reserved[3];                // ignored
|-
};
| 0x9 || InvalidAddress
 
|-
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY ===
| 0xA || InvalidSize
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]].
|-
 
| 0xB || BadValue
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2 ===
|-
Same as [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX|NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]].
| 0xD || AlreadyAllocated
 
|-
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2 ===
| 0xE || Busy
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]], but uses [[#Ioctl2|Ioctl2]].
|-
 
| 0xF || ResourceError
=== NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY ===
Same as [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY|NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]], but uses [[#Ioctl2|Ioctl2]].
 
=== NVGPU_IOCTL_CHANNEL_SET_TIMESLICE ===
Changes channel's timeslice. Identical to Linux driver.
 
  struct {
    __in u32 timeslice;
  };
 
=== NVGPU_IOCTL_CHANNEL_SET_USER_DATA ===
Sets user specific data.
 
  struct {
    __in u64 data;
  };
 
=== NVGPU_IOCTL_CHANNEL_GET_USER_DATA ===
Returns user specific data.
 
  struct {
    __out u64 data;
  };
 
= NvDrvPermission =
This is "nns::nvdrv::NvDrvPermission".
 
{| class="wikitable" border="1"
!  Bits
!  Name
!  Description
|-
|-
| 0x10 || CountMismatch
| 0
| Gpu
| Can access [[#Channels|/dev/nvhost-gpu]], [[#/dev/nvhost-ctrl-gpu|/dev/nvhost-ctrl-gpu]] and [[#/dev/nvhost-as-gpu|/dev/nvhost-as-gpu]].
|-
|-
| 0x11 || OverFlow
| 1
| GpuDebug
| Can access [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]] and [[#/dev/nvhost-prof-gpu|/dev/nvhost-prof-gpu]].
|-
|-
| 0x1000 || InsufficientTransferMemory
| 2
| GpuSchedule
| Can access [[#/dev/nvsched-ctrl|/dev/nvsched-ctrl]].
|-
|-
| 0x10000 || InsufficientVideoMemory
| 3
| VIC
| Can access [[#Channels|/dev/nvhost-vic]].
|-
|-
| 0x10001 || BadSurfaceColorScheme
| 4
| VideoEncoder
| Can access [[#Channels|/dev/nvhost-msenc]].
|-
|-
| 0x10002 || InvalidSurface
| 5
| VideoDecoder
| Can access [[#Channels|/dev/nvhost-nvdec]].
|-
|-
| 0x10003 || SurfaceNotSupported
| 6
| TSEC
| Can access [[#Channels|/dev/nvhost-tsec]].
|-
|-
| 0x20000 || DispInitFailed
| 7
| JPEG
| Can access [[#Channels|/dev/nvhost-nvjpg]].
|-
|-
| 0x20001 || DispAlreadyAttached
| 8
| Display
| Can access [[#Channels|/dev/nvhost-display]], [[#/dev/nvcec-ctrl|/dev/nvcec-ctrl]], [[#/dev/nvhdcp_up-ctrl|/dev/nvhdcp_up-ctrl]], [[#/dev/nvdisp-ctrl|/dev/nvdisp-ctrl]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp0]], [[#/dev/nvdisp-disp0, /dev/nvdisp-disp1|/dev/nvdisp-disp1]], [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp0]] and [[#/dev/nvdcutil-disp0, /dev/nvdcutil-disp1|/dev/nvdcutil-disp1]].
|-
|-
| 0x20002 || DispTooManyDisplays
| 9
| ImportMemory
| Can duplicate [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
|-
| 0x20003 || DispNoDisplaysAttached
| 10
| NoCheckedAruid
| Can use [[#SetAruidWithoutCheck|SetAruidWithoutCheck]].
|-
|-
| 0x20004 || DispModeNotSupported
| 11
|
| Can use [[#SetGraphicsFirmwareMemoryMarginEnabled|SetGraphicsFirmwareMemoryMarginEnabled]].
|-
|-
| 0x20005 || DispNotFound
| 12
|
| Can duplicate exported [[#/dev/nvmap|nvmap]] handles from other processes with [[#NVMAP_IOC_FROM_ID|NVMAP_IOC_FROM_ID]].
|-
|-
| 0x20006 || DispAttachDissallowed
| 13
|
| Can use the GPU virtual address range 0xC0000 to 0x580000 instead of 0x0 to 0xC0000.
|-
|-
| 0x20007 || DispTypeNotSupported
| 14
|
| Can use [[#NVMAP_IOC_EXPORT_FOR_ARUID|NVMAP_IOC_EXPORT_FOR_ARUID]] and [[#NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID|NVMAP_IOC_REMOVE_EXPORT_FOR_ARUID]].
|-
|-
| 0x20008 || DispAuthenticationFailed
| 15
|-
|
| 0x20009 || DispNotAttached
| Can use the virtual address ranges 0x0 to 0x100000000 (GPU) and 0x0 to 0xE0000000 (non-GPU) instead of 0x100000000 to 0x11FA50000 (GPU) and 0xE0000000 to 0xFFFE0000 (non-GPU).
|}
 
= NvError =
This is "nns::nvdrv::NvError".
 
{| class="wikitable" border="1"
|-
|-
| 0x2000A || DispSamePwrState
! Value || Name
|-
|-
| 0x2000B || DispEdidFailure
| 0x0 || Success
|-
|-
| 0x2000C || DispDsiReadAckError
| 0x1 || NotImplemented
|-
|-
| 0x2000D || DispDsiReadInvalidResp
| 0x2 || NotSupported
|-
|-
| 0x30000 || FileWriteFailed
| 0x3 || NotInitialized
|-
|-
| 0x30001 || FileReadFailed
| 0x4 || BadParameter
|-
|-
| 0x30002 || EndOfFile
| 0x5 || Timeout
|-
|-
| 0x30003 || FileOperationFailed
| 0x6 || InsufficientMemory
|-
|-
| 0x30004 || DirOperationFailed
| 0x7 || ReadOnlyAttribute
|-
|-
| 0x30005 || EndOfDirList
| 0x8 || InvalidState
|-
|-
| 0x30006 || ConfigVarNotFound
| 0x9 || InvalidAddress
|-
|-
| 0x30007 || InvalidConfigVar
| 0xA || InvalidSize
|-
|-
| 0x30008 || LibraryNotFound
| 0xB || BadValue
|-
| 0xD || AlreadyAllocated
|-
| 0xE || Busy
|-
| 0xF || ResourceError
|-
| 0x10 || CountMismatch
|-
| 0x11 || OverFlow
|-
|-
| 0x30009 || SymbolNotFound
| 0x1000 || InsufficientTransferMemory
|-
|-
| 0x3000A || MemoryMapFailed
| 0x10000 || InsufficientVideoMemory
|-
|-
| 0x3000F || IoctlFailed                       
| 0x10001 || BadSurfaceColorScheme
|-
|-
| 0x30010 || AccessDenied
| 0x10002 || InvalidSurface
|-
|-
| 0x30011 || DeviceNotFound
| 0x10003 || SurfaceNotSupported
|-
|-
| 0x30012 || KernelDriverNotFound
| 0x20000 || DispInitFailed
|-
|-
| 0x30013 || FileNotFound
| 0x20001 || DispAlreadyAttached
|-
|-
| 0x30014 || PathAlreadyExists
| 0x20002 || DispTooManyDisplays
|-
|-
| 0xA000E || ModuleNotPresent
| 0x20003 || DispNoDisplaysAttached
|}
|-
 
| 0x20004 || DispModeNotSupported
= NvDrvStatus =
|-
This is "nns::nvdrv::NvDrvStatus".
| 0x20005 || DispNotFound
|-
| 0x20006 || DispAttachDissallowed
|-
| 0x20007 || DispTypeNotSupported
|-
| 0x20008 || DispAuthenticationFailed
|-
| 0x20009 || DispNotAttached
|-
| 0x2000A || DispSamePwrState
|-
| 0x2000B || DispEdidFailure
|-
| 0x2000C || DispDsiReadAckError
|-
| 0x2000D || DispDsiReadInvalidResp
|-
| 0x30000 || FileWriteFailed
|-
| 0x30001 || FileReadFailed
|-
| 0x30002 || EndOfFile
|-
| 0x30003 || FileOperationFailed
|-
| 0x30004 || DirOperationFailed
|-
| 0x30005 || EndOfDirList
|-
| 0x30006 || ConfigVarNotFound
|-
| 0x30007 || InvalidConfigVar
|-
| 0x30008 || LibraryNotFound
|-
| 0x30009 || SymbolNotFound
|-
| 0x3000A || MemoryMapFailed
|-
| 0x3000F || IoctlFailed                       
|-
| 0x30010 || AccessDenied
|-
| 0x30011 || DeviceNotFound
|-
| 0x30012 || KernelDriverNotFound
|-
| 0x30013 || FileNotFound
|-
| 0x30014 || PathAlreadyExists
|-
| 0xA000E || ModuleNotPresent
|}
 
= NvDrvStatus =
This is "nns::nvdrv::NvDrvStatus".


{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
! Offset
! Offset
! Size
! Size
! Description
! Description
|-
|-
| 0x0
| 0x0
| 0x4
| 0x4
| FreeSize
| FreeSize
|-
|-
| 0x4
| 0x4
| 0x4
| 0x4
| AllocatableSize
| AllocatableSize
|-
|-
| 0x8
| 0x8
| 0x4
| 0x4
| MinimumFreeSize
| MinimumFreeSize
|-
|-
| 0xC
| 0xC
| 0x4
| 0x4
| MinimumAllocatableSize
| MinimumAllocatableSize
|-
|-
| 0x10
| 0x10
| 0x10
| 0x10
| Reserved
| Reserved
|}
|}
 
= Notes =
In some cases, a panic may occur. NV forces a crash by doing:
(void *)0 = 0xCAFE;
End result is that the system hangs with a white-screen.
 
When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done.


= Notes =
GPU rendering (GPFIFO) is only used by applets/Applications. All sysmodules doing any gfx-display uses software rendering. During system-boot, GPU GPFIFO is not used until the applets are launched.
In some cases, a panic may occur. NV forces a crash by doing:
(void *)0 = 0xCAFE;
End result is that the system hangs with a white-screen.
 
When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done.


[[Category:Services]]
[[Category:Services]]
Retrieved from "https://switchbrew.org/wiki/NV_services"