TSEC: Difference between revisions
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==== IV0 ==== | ==== IV0 ==== | ||
This is a SPR (special purpose register) that holds the address for interrupt vector 0. | This is a SPR (special purpose register) that holds the address for interrupt vector 0. Only bits 0 to 15 are used. | ||
==== IV1 ==== | ==== IV1 ==== | ||
This is a SPR (special purpose register) that holds the address for interrupt vector 1. | This is a SPR (special purpose register) that holds the address for interrupt vector 1. Only bits 0 to 15 are used. | ||
==== IV2 ==== | ==== IV2 ==== | ||
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==== EV ==== | ==== EV ==== | ||
This is a SPR (special purpose register) that holds the address for the exception vector. | This is a SPR (special purpose register) that holds the address for the exception vector. Only bits 0 to 15 are used. | ||
Alternative name (envytools): "tv". | Alternative name (envytools): "tv". | ||
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|- | |- | ||
| 11 || ALU zero flag | | 11 || ALU zero flag | ||
|- | |- | ||
| 16 || Interrupt 0 enable | | 16 || Interrupt 0 enable | ||
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|- | |- | ||
| 18 || Interrupt 2 enable (undefined) | | 18 || Interrupt 2 enable (undefined) | ||
|- | |- | ||
| 20 || Interrupt 0 saved enable | | 20 || Interrupt 0 saved enable | ||
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|- | |- | ||
| 22 || Interrupt 2 saved enable (undefined) | | 22 || Interrupt 2 saved enable (undefined) | ||
|- | |- | ||
| 24 || Exception active | | 24 || Exception active | ||
|- | |- | ||
| 26-31 || Unknown | |||
| 26 | |||
|} | |} | ||
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0: DMEM | 0: DMEM | ||
1: IMEM | 1: IMEM | ||
|} | |} | ||
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|- | |- | ||
| 0-7 || Start of region to authenticate (in 0x100 pages) | | 0-7 || Start of region to authenticate (in 0x100 pages) | ||
|- | |- | ||
| 16 || Mark all subsequent code transfers as secret | | 16 || Mark all subsequent code transfers as secret | ||
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|- | |- | ||
| 19 || Block traps and interrupts (set in HS mode) | | 19 || Block traps and interrupts (set in HS mode) | ||
|- | |- | ||
| 24-31 || Size of region to authenticate (in 0x100 pages) | | 24-31 || Size of region to authenticate (in 0x100 pages) | ||
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|- | |- | ||
| 0-2 || CTXDMA port for code loads (xcld) | | 0-2 || CTXDMA port for code loads (xcld) | ||
|- | |- | ||
| 4-6 || CTXDMA port for code stores (invalid) | | 4-6 || CTXDMA port for code stores (invalid) | ||
|- | |- | ||
| 8-10 || CTXDMA port for data loads (xdld) | | 8-10 || CTXDMA port for data loads (xdld) | ||
|- | |- | ||
| 12-14 || CTXDMA port for data stores (xdst) | | 12-14 || CTXDMA port for data stores (xdst) | ||
|} | |} | ||
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! Description | ! Description | ||
|- | |- | ||
| 0- | | 0-15 || Exception PC | ||
|- | |- | ||
| 20-23 || Exception cause | | 20-23 || Exception cause | ||
|} | |} | ||