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→KernelLdr_MapInitialIdentityMapping
// Architecture is 0xD07 (Cortex-A57).
// Architecture is 0xD07 (Cortex-A57).
cpuactlr_value = 0x1000000; // Non-cacheable load forwarding enabled
cpuactlr_value = 0x1000000; // Non-cacheable load forwarding enabled
cpuectlr_value = 0x1B00000040; // TODO: What is this?
cpuectlr_value = 0x1B00000040; // Enable the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster; set the L2 load/store data prefetch distance to 8 requests; set the L2 instruction fetch prefetch distance to 3 requests.
if (hw_variant == 0 || (hw_variant == 1 && hw_revision <= 1)) {
if (hw_variant == 0 || (hw_variant == 1 && hw_revision <= 1)) {
// If supported, disable load-pass DMB.
// If supported, disable load-pass DMB.
} else if (architecture == 0xD03) { // 9.0.0+
} else if (architecture == 0xD03) { // 9.0.0+
// Architecture is 0xD03 (Cortex-A53).
// Architecture is 0xD03 (Cortex-A53).
cpuactlr_value = 0x90CA000; // TODO: What is this?
cpuactlr_value = 0x90CA000; // Set L1 data prefetch control to allow 5 outstanding prefetches; enable device split throttle; set the number of independent data prefetch streams to 2; disable transient and no-read-allocate hints for loads; set write streaming no-allocate threshold so the 128th consecutive streaming cache line does not allocate in the L1 or L2 cache.
cpuectlr_value = 0x40; // TODO: What is this?
cpuectlr_value = 0x40; // Enable hardware management of data coherency with other cores in the cluster.
if (hw_variant != 0 || (hw_variant == 0 && hw_revision > 2)) {
if (hw_variant != 0 || (hw_variant == 0 && hw_revision > 2)) {
// TODO: What is this?
// If supported, enable data cache clean as data cache clean/invalidate.
cpuactlr_value |= 0x100000000000;
cpuactlr_value |= 0x100000000000;
}
}