NV services: Difference between revisions
| Line 1,060: | Line 1,060: | ||
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]] | | 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]] | ||
|- | |- | ||
| 0xC0184706 || Inout || 24 || NVGPU_GPU_IOCTL_GET_TPC_MASKS | | 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]] | ||
|- | |- | ||
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]] | | 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]] | ||
|- | |- | ||
| 0x4008470D || In || 8 || NVGPU_GPU_IOCTL_INVAL_ICACHE | | 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]] | ||
|- | |- | ||
| 0x4008470E || In || 8 || | | 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]] | ||
|- | |- | ||
| 0x4010470F || In || 16 || NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE | | 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]] | ||
|- | |- | ||
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE | | 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE | ||
| Line 1,191: | Line 1,191: | ||
__in u64 gpu_characteristics_buf_addr; // ignored, but must not be NULL | __in u64 gpu_characteristics_buf_addr; // ignored, but must not be NULL | ||
__out struct gpu_characteristics gc; | __out struct gpu_characteristics gc; | ||
}; | |||
=== NVGPU_GPU_IOCTL_GET_TPC_MASKS === | |||
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer. | |||
struct { | |||
__in u32 mask_buf_size; // ignored, but must not be NULL | |||
__in u32 reserved[3]; | |||
__out u64 mask_buf; // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1) | |||
}; | }; | ||
| Line 1,198: | Line 1,207: | ||
struct { | struct { | ||
__in u32 flush; // l2_flush | l2_invalidate << 1 | fb_flush << 2 | __in u32 flush; // l2_flush | l2_invalidate << 1 | fb_flush << 2 | ||
u32 | __in u32 reserved; | ||
}; | |||
=== NVGPU_GPU_IOCTL_INVAL_ICACHE === | |||
Invalidates the GPU instruction cache. Identical to Linux driver. | |||
struct { | |||
__in s32 channel_fd; | |||
__in u32 reserved; | |||
}; | |||
=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE === | |||
Sets the GPU MMU debug mode. Identical to Linux driver. | |||
struct { | |||
__in u32 state; | |||
__in u32 reserved; | |||
}; | |||
=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE === | |||
Sets the GPU SM debug mode. Identical to Linux driver. | |||
struct { | |||
__in s32 channel_fd; | |||
__in u32 enable; | |||
__in u64 sms; | |||
}; | }; | ||