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TSEC (view source)

Revision as of 18:49, 23 August 2019

4,618 bytes added ,  18:49, 23 August 2019
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Line 21: Line 21:  
| TSEC_THI_INCR_SYNCPT
 
| TSEC_THI_INCR_SYNCPT
 
| 0x54500000
 
| 0x54500000
 +
| 0x04
 +
|-
 +
| TSEC_THI_INCR_SYNCPT_CTRL
 +
| 0x54500004
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 33: Line 37:  
| TSEC_THI_CTXSW
 
| TSEC_THI_CTXSW
 
| 0x54500020
 
| 0x54500020
 +
| 0x04
 +
|-
 +
| TSEC_THI_CTXSW_NEXT
 +
| 0x54500024
 
| 0x04
 
| 0x04
 
|-
 
|-
 
| TSEC_THI_CONT_SYNCPT_EOF
 
| TSEC_THI_CONT_SYNCPT_EOF
 
| 0x54500028
 
| 0x54500028
 +
| 0x04
 +
|-
 +
| TSEC_THI_CONT_SYNCPT_L1
 +
| 0x5450002C
 +
| 0x04
 +
|-
 +
| TSEC_THI_STREAMID0
 +
| 0x54500030
 +
| 0x04
 +
|-
 +
| TSEC_THI_STREAMID1
 +
| 0x54500034
 +
| 0x04
 +
|-
 +
| TSEC_THI_THI_SEC
 +
| 0x54500038
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 45: Line 69:  
| [[#TSEC_THI_METHOD1|TSEC_THI_METHOD1]]
 
| [[#TSEC_THI_METHOD1|TSEC_THI_METHOD1]]
 
| 0x54500044
 
| 0x54500044
 +
| 0x04
 +
|-
 +
| TSEC_THI_CONTEXT_SWITCH
 +
| 0x54500060
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 55: Line 83:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_THI_INT_CLEAR
+
| TSEC_THI_CONFIG0
 
| 0x54500080
 
| 0x54500080
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_THI_INT_ENABLE
+
| TSEC_THI_DBG_MISC
 
| 0x54500084
 
| 0x54500084
 
| 0x04
 
| 0x04
Line 135: Line 163:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_3C
+
| [[#FALCON_IRQDEST2|FALCON_IRQDEST2]]
 
| 0x5450103C
 
| 0x5450103C
 
| 0x04
 
| 0x04
Line 267: Line 295:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_D4
+
| [[#FALCON_SVEC_SPR|FALCON_SVEC_SPR]]
 
| 0x545010D4
 
| 0x545010D4
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_D8
+
| [[#FALCON_RSTAT0|FALCON_RSTAT0]]
 
| 0x545010D8
 
| 0x545010D8
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_DC
+
| [[#FALCON_RSTAT3|FALCON_RSTAT3]]
 
| 0x545010DC
 
| 0x545010DC
 
| 0x04
 
| 0x04
Line 323: Line 351:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_CPUSTAT
+
| FALCON_DBG_STATE
 
| 0x54501128
 
| 0x54501128
 
| 0x04
 
| 0x04
Line 333: Line 361:  
| FALCON_CPUCTL_ALIAS
 
| FALCON_CPUCTL_ALIAS
 
| 0x54501130
 
| 0x54501130
 +
| 0x04
 +
|-
 +
| FALCON_STACKCFG
 +
| 0x54501138
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 383: Line 415:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_CG1_SLCG
+
| FALCON_CG2
 
| 0x5450117C
 
| 0x5450117C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_IMEMC|FALCON_IMEMC]]
+
| [[#FALCON_IMEMC0|FALCON_IMEMC0]]
 
| 0x54501180
 
| 0x54501180
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_IMEMD|FALCON_IMEMD]]
+
| [[#FALCON_IMEMD0|FALCON_IMEMD0]]
 
| 0x54501184
 
| 0x54501184
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_IMEMT|FALCON_IMEMT]]
+
| [[#FALCON_IMEMT0|FALCON_IMEMT0]]
 
| 0x54501188
 
| 0x54501188
 +
| 0x04
 +
|-
 +
| FALCON_IMEMC1
 +
| 0x54501190
 +
| 0x04
 +
|-
 +
| FALCON_IMEMD1
 +
| 0x54501194
 +
| 0x04
 +
|-
 +
| FALCON_IMEMT1
 +
| 0x54501198
 +
| 0x04
 +
|-
 +
| FALCON_IMEMC2
 +
| 0x545011A0
 +
| 0x04
 +
|-
 +
| FALCON_IMEMD2
 +
| 0x545011A4
 +
| 0x04
 +
|-
 +
| FALCON_IMEMT2
 +
| 0x545011A8
 +
| 0x04
 +
|-
 +
| FALCON_IMEMC3
 +
| 0x545011B0
 +
| 0x04
 +
|-
 +
| FALCON_IMEMD3
 +
| 0x545011B4
 +
| 0x04
 +
|-
 +
| FALCON_IMEMT3
 +
| 0x545011B8
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 483: Line 551:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#FALCON_SCTL_STAT|FALCON_SCTL_STAT]]
+
| [[#FALCON_SSTAT|FALCON_SSTAT]]
 
| 0x54501244
 
| 0x54501244
 
| 0x04
 
| 0x04
Line 535: Line 603:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_2C0
+
| FALCON_DMAINFO_FINISHED_FBRD_LOW
 
| 0x545012C0
 
| 0x545012C0
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_2C4
+
| FALCON_DMAINFO_FINISHED_FBRD_HIGH
 
| 0x545012C4
 
| 0x545012C4
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_2C8
+
| FALCON_DMAINFO_FINISHED_FBWR_LOW
 
| 0x545012C8
 
| 0x545012C8
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_2CC
+
| FALCON_DMAINFO_FINISHED_FBWR_HIGH
 
| 0x545012CC
 
| 0x545012CC
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| FALCON_UNK_2E0
+
| FALCON_DMAINFO_CURRENT_FBRD_LOW
 +
| 0x545012D0
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CURRENT_FBRD_HIGH
 +
| 0x545012D4
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CURRENT_FBWR_LOW
 +
| 0x545012D8
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CURRENT_FBWR_HIGH
 +
| 0x545012DC
 +
| 0x04
 +
|-
 +
| FALCON_DMAINFO_CTL
 
| 0x545012E0
 
| 0x545012E0
 
| 0x04
 
| 0x04
Line 687: Line 771:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_CTL
+
| [[#TSEC_TFBIF_CTL|TSEC_TFBIF_CTL]]
 
| 0x54501600
 
| 0x54501600
 
| 0x04
 
| 0x04
Line 695: Line 779:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_THROTTLE
+
| [[#TSEC_TFBIF_THROTTLE|TSEC_TFBIF_THROTTLE]]
 
| 0x54501608
 
| 0x54501608
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_UNK_0C
+
| [[#TSEC_TFBIF_DBG_STAT0|TSEC_TFBIF_DBG_STAT0]]
 
| 0x5450160C
 
| 0x5450160C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| TSEC_TFBIF_DEBUG_STAT
+
| TSEC_TFBIF_DBG_STAT1
 +
| 0x54501610
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_RDCOUNT_LO
 +
| 0x54501614
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_RDCOUNT_HI
 +
| 0x54501618
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_WRCOUNT_LO
 +
| 0x5450161C
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_WRCOUNT_HI
 +
| 0x54501620
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_R32COUNT
 +
| 0x54501624
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_R64COUNT
 +
| 0x54501628
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_DBG_R128COUNT
 +
| 0x5450162C
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_UNK_30
 
| 0x54501630
 
| 0x54501630
 
| 0x04
 
| 0x04
Line 711: Line 827:  
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_TFBIF_MMU_PROT|TSEC_TFBIF_MMU_PROT]]
+
| TSEC_TFBIF_WRR_RDP
 +
| 0x54501638
 +
| 0x04
 +
|-
 +
| [[#TSEC_TFBIF_SPROT_EMEM|TSEC_TFBIF_SPROT_EMEM]]
 
| 0x54501640
 
| 0x54501640
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_TFBIF_MMU_PHYS_SEC|TSEC_TFBIF_MMU_PHYS_SEC]]
+
| [[#TSEC_TFBIF_TRANSCFG|TSEC_TFBIF_TRANSCFG]]
 
| 0x54501644
 
| 0x54501644
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_TFBIF_MMU_TRANSCFG|TSEC_TFBIF_MMU_TRANSCFG]]
+
| [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]]
 
| 0x54501648
 
| 0x54501648
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_TFBIF_ACTMON_MAMASK|TSEC_TFBIF_ACTMON_MAMASK]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_MASK|TSEC_TFBIF_ACTMON_ACTIVE_MASK]]
 
| 0x5450164C
 
| 0x5450164C
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_TFBIF_ACTMON_BORPS|TSEC_TFBIF_ACTMON_BORPS]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_BORPS|TSEC_TFBIF_ACTMON_ACTIVE_BORPS]]
 
| 0x54501650
 
| 0x54501650
 
| 0x04
 
| 0x04
 
|-
 
|-
−
| [[#TSEC_TFBIF_ACTMON_CTL|TSEC_TFBIF_ACTMON_CTL]]
+
| [[#TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT|TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT]]
 
| 0x54501654
 
| 0x54501654
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_ACTMON_MCB_MASK
 +
| 0x54501660
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_ACTMON_MCB_BORPS
 +
| 0x54501664
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_ACTMON_MCB_WEIGHT
 +
| 0x54501668
 +
| 0x04
 +
|-
 +
| TSEC_TFBIF_THI_TRANSPROP
 +
| 0x54501670
 
| 0x04
 
| 0x04
 
|-
 
|-
Line 820: Line 956:  
!  ID
 
!  ID
 
!  Method
 
!  Method
 +
|-
 +
| 0x100
 +
| NOP
 +
|-
 +
| 0x140
 +
| PM_TRIGGER
 
|-
 
|-
 
| 0x200
 
| 0x200
 
| SET_APPLICATION_ID
 
| SET_APPLICATION_ID
 +
|-
 +
| 0x204
 +
| SET_WATCHDOG_TIMER
 +
|-
 +
| 0x240
 +
| SEMAPHORE_A
 +
|-
 +
| 0x244
 +
| SEMAPHORE_B
 +
|-
 +
| 0x248
 +
| SEMAPHORE_C
 +
|-
 +
| 0x24C
 +
|
 +
|-
 +
| 0x250
 +
|
 
|-
 
|-
 
| 0x300
 
| 0x300
 
| EXECUTE
 
| EXECUTE
 +
|-
 +
| 0x304
 +
| SEMAPHORE_D
 
|-
 
|-
 
| 0x500
 
| 0x500
Line 973: Line 1,136:  
| 0x740
 
| 0x740
 
| [6.0.0+] HDCP_GET_CURRENT_NONCE
 
| [6.0.0+] HDCP_GET_CURRENT_NONCE
 +
|-
 +
| 0x1114
 +
| PM_TRIGGER_END
 
|}
 
|}
   Line 1,029: Line 1,195:  
| 8-15
 
| 8-15
 
| FALCON_IRQSSET_EXT
 
| FALCON_IRQSSET_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQSSET_DMA
 
|}
 
|}
   Line 1,064: Line 1,233:  
| 8-15
 
| 8-15
 
| FALCON_IRQSCLR_EXT
 
| FALCON_IRQSCLR_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQSCLR_DMA
 
|}
 
|}
   Line 1,099: Line 1,271:  
| 8-15
 
| 8-15
 
| FALCON_IRQSTAT_EXT
 
| FALCON_IRQSTAT_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQSTAT_DMA
 
|}
 
|}
   Line 1,134: Line 1,309:  
| 8-15
 
| 8-15
 
| FALCON_IRQMODE_LVL_EXT
 
| FALCON_IRQMODE_LVL_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQMODE_LVL_DMA
 
|}
 
|}
   Line 1,169: Line 1,347:  
| 8-15
 
| 8-15
 
| FALCON_IRQMSET_EXT
 
| FALCON_IRQMSET_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQMSET_DMA
 
|}
 
|}
   Line 1,204: Line 1,385:  
| 8-15
 
| 8-15
 
| FALCON_IRQMCLR_EXT
 
| FALCON_IRQMCLR_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQMCLR_DMA
 
|}
 
|}
   Line 1,239: Line 1,423:  
| 8-15
 
| 8-15
 
| FALCON_IRQMASK_EXT
 
| FALCON_IRQMASK_EXT
 +
|-
 +
| 16
 +
| FALCON_IRQMASK_DMA
 
|}
 
|}
   Line 1,305: Line 1,492:  
Used for routing Falcon's IRQs.
 
Used for routing Falcon's IRQs.
   −
=== FALCON_MAILBOX0 ===
+
=== FALCON_IRQDEST2 ===
−
Scratch register for reading/writing data to Falcon.
  −
 
  −
=== FALCON_MAILBOX1 ===
  −
Scratch register for reading/writing data to Falcon.
  −
 
  −
=== FALCON_ITFEN ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,317: Line 1,498:  
|-
 
|-
 
| 0
 
| 0
−
| FALCON_ITFEN_CTXEN
+
| FALCON_IRQDEST2_HOST_DMA
 +
|-
 +
| 16
 +
| FALCON_IRQDEST2_TARGET_DMA
 +
|}
 +
 
 +
Used for routing Falcon's IRQs.
 +
 
 +
=== FALCON_MAILBOX0 ===
 +
Scratch register for reading/writing data to Falcon.
 +
 
 +
=== FALCON_MAILBOX1 ===
 +
Scratch register for reading/writing data to Falcon.
 +
 
 +
=== FALCON_ITFEN ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| FALCON_ITFEN_CTXEN
 
|-
 
|-
 
| 1
 
| 1
Line 1,349: Line 1,550:  
| 16
 
| 16
 
| FALCON_DEBUG1_CTXSW_MODE
 
| FALCON_DEBUG1_CTXSW_MODE
 +
|-
 +
| 17
 +
| FALCON_DEBUG1_TRACE_FORMAT
 
|}
 
|}
   Line 1,362: Line 1,566:  
|-
 
|-
 
| 0-19
 
| 0-19
−
| PC that originated the exception
+
| FALCON_EXCI_EXPC
 
|-
 
|-
 
| 20-23
 
| 20-23
−
| Exception type
+
| FALCON_EXCI_EXCAUSE
−
  0x00: Trap 0
+
  0x00: TRAP0
−
  0x01: Trap 1
+
  0x01: TRAP1
−
  0x02: Trap 2
+
  0x02: TRAP2
−
  0x03: Trap 3
+
  0x03: TRAP3
−
  0x08: Invalid opcode
+
  0x08: ILL_INS (invalid opcode)
−
  0x09: Authentication entry
+
  0x09: INV_INS (authentication entry)
−
  0x0A: Page fault (no hit)
+
  0x0A: MISS_INS (page miss)
−
  0x0B: Page fault (multi hit)
+
  0x0B: DHIT_INS (page multiple hit)
−
  0x0F: Breakpoint
+
  0x0F: BRKPT_INS (breakpoint hit)
 
|}
 
|}
    
Contains information about raised exceptions.
 
Contains information about raised exceptions.
 +
 +
=== FALCON_SVEC_SPR ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 18
 +
| FALCON_SVEC_SPR_SIGPASS
 +
|}
 +
 +
=== FALCON_RSTAT0 ===
 +
Mirror of the ICD status register 0.
 +
 +
=== FALCON_RSTAT3 ===
 +
Mirror of the ICD status register 3.
    
=== FALCON_CPUCTL ===
 
=== FALCON_CPUCTL ===
Line 1,403: Line 1,622:  
|-
 
|-
 
| 6
 
| 6
−
| FALCON_CPUCTL_CPUCTL_ALIAS_EN
+
| FALCON_CPUCTL_ALIAS_EN
 
|}
 
|}
   Line 1,590: Line 1,809:  
|-
 
|-
 
| 0-23
 
| 0-23
−
| Address
+
| FALCON_IMCTL_ADDR_BLK
 
|-
 
|-
 
| 24-26
 
| 24-26
−
| Command
+
| FALCON_IMCTL_CMD
 
  0x00: NOP
 
  0x00: NOP
 
  0x01: IMINV (ITLB)
 
  0x01: IMINV (ITLB)
 
  0x02: IMBLK (PTLB)
 
  0x02: IMBLK (PTLB)
 
  0x03: IMTAG (VTLB)
 
  0x03: IMTAG (VTLB)
 +
0x04: IMTAG_SETVLD
 
|}
 
|}
   Line 1,611: Line 1,831:  
|-
 
|-
 
| 0-7
 
| 0-7
−
| Index of where to start tracing from
+
| FALCON_TRACEIDX_IDX
 
|-
 
|-
 
| 16-23
 
| 16-23
−
| Maximum valid index
+
| FALCON_TRACEIDX_MAXIDX
 
|-
 
|-
 
| 24-31
 
| 24-31
−
| Number of trace reads remaining
+
| FALCON_TRACEIDX_CNT
 
|}
 
|}
   Line 1,625: Line 1,845:  
Returns the PC of the last call or branch executed.
 
Returns the PC of the last call or branch executed.
   −
=== FALCON_IMEMC ===
+
=== FALCON_IMEMC0 ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 1,631: Line 1,851:  
|-
 
|-
 
| 2-7
 
| 2-7
−
| Offset in IMEM block to read/write
+
| FALCON_IMEMC_OFFS
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| IMEM block to read/write
+
| FALCON_IMEMC_BLK
 
|-
 
|-
 
| 24
 
| 24
−
| Write auto-increment
+
| FALCON_IMEMC_AINCW
 
|-
 
|-
 
| 25
 
| 25
−
| Read auto-increment
+
| FALCON_IMEMC_AINCR
 
|-
 
|-
 
| 28
 
| 28
−
| Mark uploaded code as secret
+
| FALCON_IMEMC_SECURE
 
|-
 
|-
 
| 29
 
| 29
−
| Secret code upload lockdown status (read-only)
+
| FALCON_IMEMC_SEC_ATOMIC
 
|-
 
|-
 
| 30
 
| 30
−
| Secret code upload failure status (read-only)
+
| FALCON_IMEMC_SEC_WR_VIO
 
|-
 
|-
 
| 31
 
| 31
−
| Secret code upload reset scrubber status (read-only)
+
| FALCON_IMEMC_SEC_LOCK
 
|}
 
|}
    
Used for configuring access to Falcon's IMEM.
 
Used for configuring access to Falcon's IMEM.
   −
=== FALCON_IMEMD ===
+
=== FALCON_IMEMD0 ===
 
Returns or takes the value for an IMEM read/write operation.
 
Returns or takes the value for an IMEM read/write operation.
   −
=== FALCON_IMEMT ===
+
=== FALCON_IMEMT0 ===
 
Returns or takes the virtual page index for an IMEM read/write operation.
 
Returns or takes the virtual page index for an IMEM read/write operation.
   Line 1,669: Line 1,889:  
|-
 
|-
 
| 2-7
 
| 2-7
−
| Offset in DMEM block to read/write
+
| FALCON_DMEMC_OFFS
 
|-
 
|-
 
| 8-15
 
| 8-15
−
| DMEM block to read/write
+
| FALCON_DMEMC_BLK
 
|-
 
|-
 
| 24
 
| 24
−
| Write auto-increment
+
| FALCON_DMEMC_AINCW
 
|-
 
|-
 
| 25
 
| 25
−
| Read auto-increment
+
| FALCON_DMEMC_AINCR
 
|}
 
|}
   Line 1,747: Line 1,967:  
  0x1B: CTX
 
  0x1B: CTX
 
  0x1C: EXCI
 
  0x1C: EXCI
 +
0x1D: SEC1
 +
0x1E: IMB1
 +
0x1F: DMB1
 
|-
 
|-
 
| 14
 
| 14
Line 2,084: Line 2,307:  
|}
 
|}
   −
=== FALCON_SCTL_STAT ===
+
=== FALCON_SSTAT ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,155: Line 2,378:  
* [[#FALCON_IMSTAT|FALCON_IMSTAT]]
 
* [[#FALCON_IMSTAT|FALCON_IMSTAT]]
 
* FALCON_UNK_250
 
* FALCON_UNK_250
−
* FALCON_UNK_2E0
+
* FALCON_DMAINFO_CTL
    
=== FALCON_SPROT_IRQ ===
 
=== FALCON_SPROT_IRQ ===
Line 2,177: Line 2,400:  
* FALCON_GPTMRVAL
 
* FALCON_GPTMRVAL
 
* FALCON_GPTMRCTL
 
* FALCON_GPTMRCTL
−
* FALCON_UNK_3C
+
* FALCON_IRQDEST2
 
* FALCON_UNK_E0
 
* FALCON_UNK_E0
   Line 2,547: Line 2,770:  
Contains information on crypto errors generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_INSN_ERROR]] IRQ.
 
Contains information on crypto errors generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_INSN_ERROR]] IRQ.
   −
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
+
=== TSEC_TFBIF_CTL ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,553: Line 2,776:  
|-
 
|-
 
| 0
 
| 0
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
+
| TSEC_TFBIF_CTL_CLR_BWCOUNT
 
|-
 
|-
 
| 1
 
| 1
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
+
| TSEC_TFBIF_CTL_ENABLE
 
|-
 
|-
 
| 2
 
| 2
−
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
+
| TSEC_TFBIF_CTL_CLR_IDLEWDERR
 +
|-
 +
| 3
 +
| TSEC_TFBIF_CTL_RESET
 +
|-
 +
| 4
 +
| TSEC_TFBIF_CTL_IDLE
 +
|-
 +
| 5
 +
| TSEC_TFBIF_CTL_IDLEWDERR
 +
|-
 +
| 6
 +
| TSEC_TFBIF_CTL_SRTOUT
 +
|-
 +
| 7
 +
| TSEC_TFBIF_CTL_CLR_SRTOUT
 +
|-
 +
| 8-11
 +
| TSEC_TFBIF_CTL_SRTOVAL
 +
|-
 +
| 12
 +
| TSEC_TFBIF_CTL_VPR
 +
|}
 +
 
 +
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
 +
|-
 +
| 1
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
 +
|-
 +
| 2
 +
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
 
|-
 
|-
 
| 3
 
| 3
Line 2,592: Line 2,851:  
|}
 
|}
   −
=== TSEC_TFBIF_MMU_PROT ===
+
=== TSEC_TFBIF_THROTTLE ===
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
 
!  Description
 
!  Description
 
|-
 
|-
−
| 0-3
+
| 0-11
−
| Read access level
+
| TSEC_TFBIF_THROTTLE_BUCKET_SIZE
 +
|-
 +
| 16-27
 +
| TSEC_TFBIF_THROTTLE_LEAK_COUNT
 
|-
 
|-
−
| 4-7
+
| 30-31
−
| Write access level
+
| TSEC_TFBIF_THROTTLE_LEAK_SIZE
 
|}
 
|}
   −
Controls accesses to external memory at the MMU level. Accessible in HS mode only.
+
=== TSEC_TFBIF_DBG_STAT0 ===
−
 
  −
=== TSEC_TFBIF_MMU_PHYS_SEC ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,612: Line 2,872:  
|-
 
|-
 
| 0
 
| 0
−
| Bypass MMU translation on CTXDMA port 0
+
| TSEC_TFBIF_DBG_STAT0_1K_TRANSFER
 +
|-
 +
| 1
 +
| TSEC_TFBIF_DBG_STAT0_RREQ_ISSUED
 +
|-
 +
| 2
 +
| TSEC_TFBIF_DBG_STAT0_WREQ_ISSUED
 +
|-
 +
| 3
 +
| TSEC_TFBIF_DBG_STAT0_TAGQ_ISSUED
 
|-
 
|-
 
| 4
 
| 4
−
| Bypass MMU translation on CTXDMA port 1
+
| TSEC_TFBIF_DBG_STAT0_STALL_RDATQ
 +
|-
 +
| 5
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RACKQ
 +
|-
 +
| 6
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WREQQ
 +
|-
 +
| 7
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WDATQ
 
|-
 
|-
 
| 8
 
| 8
−
| Bypass MMU translation on CTXDMA port 2
+
| TSEC_TFBIF_DBG_STAT0_STALL_WACKQ
 +
|-
 +
| 9
 +
| TSEC_TFBIF_DBG_STAT0_STALL_RREQ_PENDING
 +
|-
 +
| 10
 +
| TSEC_TFBIF_DBG_STAT0_STALL_WREQ_PENDING
 +
|-
 +
| 11
 +
| TSEC_TFBIF_DBG_STAT0_STALL_MREQ
 
|-
 
|-
 
| 12
 
| 12
−
| Bypass MMU translation on CTXDMA port 3
+
| TSEC_TFBIF_DBG_STAT0_ENGINE_IDLE
 +
|-
 +
| 13
 +
| TSEC_TFBIF_DBG_STAT0_RMCCIF_IDLE
 +
|-
 +
| 14
 +
| TSEC_TFBIF_DBG_STAT0_WMCCIF_IDLE
 +
|-
 +
| 15
 +
| TSEC_TFBIF_DBG_STAT0_CSB_IDLE
 
|-
 
|-
 
| 16
 
| 16
−
| Bypass MMU translation on CTXDMA port 4
+
| TSEC_TFBIF_DBG_STAT0_RU_IDLE
 
|-
 
|-
−
| 20
+
| 17
−
| Bypass MMU translation on CTXDMA port 5
+
| TSEC_TFBIF_DBG_STAT0_WU_IDLE
 
|-
 
|-
−
| 24
+
| 19
−
| Bypass MMU translation on CTXDMA port 6
+
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_ACTIVE
 
|-
 
|-
−
| 28
+
| 20
−
| Bypass MMU translation on CTXDMA port 7
+
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_MCB
 
|}
 
|}
   −
Controls MMU bypass mode. Accessible in HS mode only.
+
=== TSEC_TFBIF_SPROT_EMEM ===
−
 
  −
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
  −
 
  −
=== TSEC_TFBIF_MMU_TRANSCFG ===
   
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
 
!  Bits
 
!  Bits
Line 2,646: Line 2,938:  
|-
 
|-
 
| 0-3
 
| 0-3
−
| Transfer configuration for CTXDMA port 0
+
| Read access level
 
|-
 
|-
 
| 4-7
 
| 4-7
−
| Transfer configuration for CTXDMA port 1
+
| Write access level
 +
|}
 +
 
 +
Controls accesses to external memory regions. Accessible in HS mode only.
 +
 
 +
=== TSEC_TFBIF_TRANSCFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0
 +
| TSEC_TFBIF_TRANSCFG_ATT0_SWID
 +
|-
 +
| 4
 +
| TSEC_TFBIF_TRANSCFG_ATT1_SWID
 +
|-
 +
| 8
 +
| TSEC_TFBIF_TRANSCFG_ATT2_SWID
 +
|-
 +
| 12
 +
| TSEC_TFBIF_TRANSCFG_ATT3_SWID
 +
|-
 +
| 16
 +
| TSEC_TFBIF_TRANSCFG_ATT4_SWID
 +
|-
 +
| 20
 +
| TSEC_TFBIF_TRANSCFG_ATT5_SWID
 +
|-
 +
| 24
 +
| TSEC_TFBIF_TRANSCFG_ATT6_SWID
 
|-
 
|-
−
| 8-11
+
| 28
−
| Transfer configuration for CTXDMA port 2
+
| TSEC_TFBIF_TRANSCFG_ATT7_SWID
 +
|}
 +
 
 +
Configures the software ID per CTXDMA port for memory transactions. Software ID 0 (HW_SWID) forces all transactions to go through the SMMU while software ID 1 (PHY_SWID) bypasses it. Accessible in HS mode only.
 +
 
 +
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
 +
 
 +
=== TSEC_TFBIF_REGIONCFG ===
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-2
 +
| TSEC_TFBIF_REGIONCFG_T0_APERT_ID
 +
|-
 +
| 3
 +
| TSEC_TFBIF_REGIONCFG_T0_VPR
 +
|-
 +
| 4-6
 +
| TSEC_TFBIF_REGIONCFG_T1_APERT_ID
 +
|-
 +
| 7
 +
| TSEC_TFBIF_REGIONCFG_T1_VPR
 +
|-
 +
| 8-10
 +
| TSEC_TFBIF_REGIONCFG_T2_APERT_ID
 +
|-
 +
| 11
 +
| TSEC_TFBIF_REGIONCFG_T2_VPR
 +
|-
 +
| 12-14
 +
| TSEC_TFBIF_REGIONCFG_T3_APERT_ID
 +
|-
 +
| 15
 +
| TSEC_TFBIF_REGIONCFG_T3_VPR
 +
|-
 +
| 16-18
 +
| TSEC_TFBIF_REGIONCFG_T4_APERT_ID
 +
|-
 +
| 19
 +
| TSEC_TFBIF_REGIONCFG_T4_VPR
 +
|-
 +
| 20-22
 +
| TSEC_TFBIF_REGIONCFG_T5_APERT_ID
 
|-
 
|-
−
| 12-15
+
| 23
−
| Transfer configuration for CTXDMA port 3
+
| TSEC_TFBIF_REGIONCFG_T5_VPR
 
|-
 
|-
−
| 16-19
+
| 24-26
−
| Transfer configuration for CTXDMA port 4
+
| TSEC_TFBIF_REGIONCFG_T6_APERT_ID
 
|-
 
|-
−
| 20-23
+
| 27
−
| Transfer configuration for CTXDMA port 5
+
| TSEC_TFBIF_REGIONCFG_T6_VPR
 
|-
 
|-
−
| 24-27
+
| 28-30
−
| Transfer configuration for CTXDMA port 6
+
| TSEC_TFBIF_REGIONCFG_T7_APERT_ID
 
|-
 
|-
−
| 28-31
+
| 31
−
| Transfer configuration for CTXDMA port 7
+
| TSEC_TFBIF_REGIONCFG_T7_VPR
 
|}
 
|}
   −
Controls external memory transfers' configuration at the MMU level. Accessible in HS mode only.
+
Configures the aperture ID and VPR mode per CTXDMA port for memory region accessing. Accessible in HS mode only.
    
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
 
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
   −
=== TSEC_TFBIF_ACTMON_MAMASK ===
+
=== TSEC_TFBIF_ACTMON_ACTIVE_MASK ===
 
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
 
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
   −
=== TSEC_TFBIF_ACTMON_BORPS ===
+
=== TSEC_TFBIF_ACTMON_ACTIVE_BORPS ===
 
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
 
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
   −
=== TSEC_TFBIF_ACTMON_CTL ===
+
=== TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT ===
 
Controls the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
 
Controls the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
  
Retrieved from "https://switchbrew.org/wiki/Special:MobileDiff/7331...7496"