Nintendo Switch Brew

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Line 21: Line 21:
| TSEC_THI_INCR_SYNCPT
| TSEC_THI_INCR_SYNCPT
| 0x54500000
| 0x54500000
| 0x04
|-
| TSEC_THI_INCR_SYNCPT_CTRL
| 0x54500004
| 0x04
| 0x04
|-
|-
Line 33: Line 37:
| TSEC_THI_CTXSW
| TSEC_THI_CTXSW
| 0x54500020
| 0x54500020
| 0x04
|-
| TSEC_THI_CTXSW_NEXT
| 0x54500024
| 0x04
| 0x04
|-
|-
| TSEC_THI_CONT_SYNCPT_EOF
| TSEC_THI_CONT_SYNCPT_EOF
| 0x54500028
| 0x54500028
| 0x04
|-
| TSEC_THI_CONT_SYNCPT_L1
| 0x5450002C
| 0x04
|-
| TSEC_THI_STREAMID0
| 0x54500030
| 0x04
|-
| TSEC_THI_STREAMID1
| 0x54500034
| 0x04
|-
| TSEC_THI_THI_SEC
| 0x54500038
| 0x04
| 0x04
|-
|-
Line 45: Line 69:
| [[#TSEC_THI_METHOD1|TSEC_THI_METHOD1]]
| [[#TSEC_THI_METHOD1|TSEC_THI_METHOD1]]
| 0x54500044
| 0x54500044
| 0x04
|-
| TSEC_THI_CONTEXT_SWITCH
| 0x54500060
| 0x04
| 0x04
|-
|-
Line 55: Line 83:
| 0x04
| 0x04
|-
|-
| TSEC_THI_INT_CLEAR
| TSEC_THI_CONFIG0
| 0x54500080
| 0x54500080
| 0x04
| 0x04
|-
|-
| TSEC_THI_INT_ENABLE
| TSEC_THI_DBG_MISC
| 0x54500084
| 0x54500084
| 0x04
| 0x04
Line 135: Line 163:
| 0x04
| 0x04
|-
|-
| FALCON_UNK_3C
| [[#FALCON_IRQDEST2|FALCON_IRQDEST2]]
| 0x5450103C
| 0x5450103C
| 0x04
| 0x04
Line 267: Line 295:
| 0x04
| 0x04
|-
|-
| FALCON_UNK_D4
| [[#FALCON_SVEC_SPR|FALCON_SVEC_SPR]]
| 0x545010D4
| 0x545010D4
| 0x04
| 0x04
|-
|-
| FALCON_UNK_D8
| [[#FALCON_RSTAT0|FALCON_RSTAT0]]
| 0x545010D8
| 0x545010D8
| 0x04
| 0x04
|-
|-
| FALCON_UNK_DC
| [[#FALCON_RSTAT3|FALCON_RSTAT3]]
| 0x545010DC
| 0x545010DC
| 0x04
| 0x04
Line 323: Line 351:
| 0x04
| 0x04
|-
|-
| FALCON_CPUSTAT
| FALCON_DBG_STATE
| 0x54501128
| 0x54501128
| 0x04
| 0x04
Line 333: Line 361:
| FALCON_CPUCTL_ALIAS
| FALCON_CPUCTL_ALIAS
| 0x54501130
| 0x54501130
| 0x04
|-
| FALCON_STACKCFG
| 0x54501138
| 0x04
| 0x04
|-
|-
Line 383: Line 415:
| 0x04
| 0x04
|-
|-
| FALCON_CG1_SLCG
| FALCON_CG2
| 0x5450117C
| 0x5450117C
| 0x04
| 0x04
Line 571: Line 603:
| 0x04
| 0x04
|-
|-
| FALCON_UNK_2C0
| FALCON_DMAINFO_FINISHED_FBRD_LOW
| 0x545012C0
| 0x545012C0
| 0x04
| 0x04
|-
|-
| FALCON_UNK_2C4
| FALCON_DMAINFO_FINISHED_FBRD_HIGH
| 0x545012C4
| 0x545012C4
| 0x04
| 0x04
|-
|-
| FALCON_UNK_2C8
| FALCON_DMAINFO_FINISHED_FBWR_LOW
| 0x545012C8
| 0x545012C8
| 0x04
| 0x04
|-
|-
| FALCON_UNK_2CC
| FALCON_DMAINFO_FINISHED_FBWR_HIGH
| 0x545012CC
| 0x545012CC
| 0x04
| 0x04
|-
|-
| FALCON_UNK_2E0
| FALCON_DMAINFO_CURRENT_FBRD_LOW
| 0x545012D0
| 0x04
|-
| FALCON_DMAINFO_CURRENT_FBRD_HIGH
| 0x545012D4
| 0x04
|-
| FALCON_DMAINFO_CURRENT_FBWR_LOW
| 0x545012D8
| 0x04
|-
| FALCON_DMAINFO_CURRENT_FBWR_HIGH
| 0x545012DC
| 0x04
|-
| FALCON_DMAINFO_CTL
| 0x545012E0
| 0x545012E0
| 0x04
| 0x04
Line 723: Line 771:
| 0x04
| 0x04
|-
|-
| TSEC_TFBIF_CTL
| [[#TSEC_TFBIF_CTL|TSEC_TFBIF_CTL]]
| 0x54501600
| 0x54501600
| 0x04
| 0x04
Line 731: Line 779:
| 0x04
| 0x04
|-
|-
| TSEC_TFBIF_THROTTLE
| [[#TSEC_TFBIF_THROTTLE|TSEC_TFBIF_THROTTLE]]
| 0x54501608
| 0x54501608
| 0x04
| 0x04
|-
|-
| TSEC_TFBIF_UNK_0C
| [[#TSEC_TFBIF_DBG_STAT0|TSEC_TFBIF_DBG_STAT0]]
| 0x5450160C
| 0x5450160C
| 0x04
| 0x04
|-
|-
| TSEC_TFBIF_DEBUG_STAT
| TSEC_TFBIF_DBG_STAT1
| 0x54501630
| 0x54501610
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_MCCIF_FIFOCTRL1|TSEC_TFBIF_MCCIF_FIFOCTRL1]]
| TSEC_TFBIF_DBG_RDCOUNT_LO
| 0x54501634
| 0x54501614
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_MMU_PROT|TSEC_TFBIF_MMU_PROT]]
| TSEC_TFBIF_DBG_RDCOUNT_HI
| 0x54501640
| 0x54501618
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_MMU_PHYS_SEC|TSEC_TFBIF_MMU_PHYS_SEC]]
| TSEC_TFBIF_DBG_WRCOUNT_LO
| 0x54501644
| 0x5450161C
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_MMU_APERTURE_CTL|TSEC_TFBIF_MMU_APERTURE_CTL]]
| TSEC_TFBIF_DBG_WRCOUNT_HI
| 0x54501648
| 0x54501620
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_ACTMON_MAMASK|TSEC_TFBIF_ACTMON_MAMASK]]
| TSEC_TFBIF_DBG_R32COUNT
| 0x5450164C
| 0x54501624
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_ACTMON_BORPS|TSEC_TFBIF_ACTMON_BORPS]]
| TSEC_TFBIF_DBG_R64COUNT
| 0x54501650
| 0x54501628
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_ACTMON_CTL|TSEC_TFBIF_ACTMON_CTL]]
| TSEC_TFBIF_DBG_R128COUNT
| 0x54501654
| 0x5450162C
| 0x04
| 0x04
|-
|-
| [[#TSEC_CG|TSEC_CG]]
| TSEC_TFBIF_TRANSCFG
| 0x54501630
| 0x04
|-
| [[#TSEC_TFBIF_MCCIF_FIFOCTRL1|TSEC_TFBIF_MCCIF_FIFOCTRL1]]
| 0x54501634
| 0x04
|-
| TSEC_TFBIF_WRR_RDP
| 0x54501638
| 0x04
|-
| [[#FALCON_SPROT_REGION|FALCON_SPROT_REGION]]
| 0x54501640
| 0x04
|-
| [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]]
| 0x54501644
| 0x04
|-
| [[#TSEC_TFBIF_REGIONCFG1|TSEC_TFBIF_REGIONCFG1]]
| 0x54501648
| 0x04
|-
| [[#TSEC_TFBIF_ACTMON_ACTIVE_MASK|TSEC_TFBIF_ACTMON_ACTIVE_MASK]]
| 0x5450164C
| 0x04
|-
| [[#TSEC_TFBIF_ACTMON_ACTIVE_BORPS|TSEC_TFBIF_ACTMON_ACTIVE_BORPS]]
| 0x54501650
| 0x04
|-
| [[#TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT|TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT]]
| 0x54501654
| 0x04
|-
| TSEC_TFBIF_ACTMON_MCB_MASK
| 0x54501660
| 0x04
|-
| TSEC_TFBIF_ACTMON_MCB_BORPS
| 0x54501664
| 0x04
|-
| TSEC_TFBIF_ACTMON_MCB_WEIGHT
| 0x54501668
| 0x04
|-
| TSEC_TFBIF_THI_TRANSPROP
| 0x54501670
| 0x04
|-
| [[#TSEC_CG|TSEC_CG]]
| 0x545016D0
| 0x545016D0
| 0x04
| 0x04
Line 1,095: Line 1,195:
| 8-15
| 8-15
| FALCON_IRQSSET_EXT
| FALCON_IRQSSET_EXT
|-
| 16
| FALCON_IRQSSET_DMA
|}
|}


Line 1,130: Line 1,233:
| 8-15
| 8-15
| FALCON_IRQSCLR_EXT
| FALCON_IRQSCLR_EXT
|-
| 16
| FALCON_IRQSCLR_DMA
|}
|}


Line 1,165: Line 1,271:
| 8-15
| 8-15
| FALCON_IRQSTAT_EXT
| FALCON_IRQSTAT_EXT
|-
| 16
| FALCON_IRQSTAT_DMA
|}
|}


Line 1,200: Line 1,309:
| 8-15
| 8-15
| FALCON_IRQMODE_LVL_EXT
| FALCON_IRQMODE_LVL_EXT
|-
| 16
| FALCON_IRQMODE_LVL_DMA
|}
|}


Line 1,235: Line 1,347:
| 8-15
| 8-15
| FALCON_IRQMSET_EXT
| FALCON_IRQMSET_EXT
|-
| 16
| FALCON_IRQMSET_DMA
|}
|}


Line 1,270: Line 1,385:
| 8-15
| 8-15
| FALCON_IRQMCLR_EXT
| FALCON_IRQMCLR_EXT
|-
| 16
| FALCON_IRQMCLR_DMA
|}
|}


Line 1,305: Line 1,423:
| 8-15
| 8-15
| FALCON_IRQMASK_EXT
| FALCON_IRQMASK_EXT
|-
| 16
| FALCON_IRQMASK_DMA
|}
|}


Line 1,367: Line 1,488:
| 24-31
| 24-31
| FALCON_IRQDEST_TARGET_EXT
| FALCON_IRQDEST_TARGET_EXT
|}
Used for routing Falcon's IRQs.
=== FALCON_IRQDEST2 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0
| FALCON_IRQDEST2_HOST_DMA
|-
| 16
| FALCON_IRQDEST2_TARGET_DMA
|}
|}


Line 1,415: Line 1,550:
| 16
| 16
| FALCON_DEBUG1_CTXSW_MODE
| FALCON_DEBUG1_CTXSW_MODE
|-
| 17
| FALCON_DEBUG1_TRACE_FORMAT
|}
|}


Line 1,428: Line 1,566:
|-
|-
| 0-19
| 0-19
| PC that originated the exception
| FALCON_EXCI_EXPC
|-
|-
| 20-23
| 20-23
| Exception type
| FALCON_EXCI_EXCAUSE
  0x00: Trap 0
  0x00: TRAP0
  0x01: Trap 1
  0x01: TRAP1
  0x02: Trap 2
  0x02: TRAP2
  0x03: Trap 3
  0x03: TRAP3
  0x08: Invalid opcode
  0x08: ILL_INS (invalid opcode)
  0x09: Authentication entry
  0x09: INV_INS (authentication entry)
  0x0A: Page fault (no hit)
  0x0A: MISS_INS (page miss)
  0x0B: Page fault (multi hit)
  0x0B: DHIT_INS (page multiple hit)
  0x0F: Breakpoint
  0x0F: BRKPT_INS (breakpoint hit)
|}
|}


Contains information about raised exceptions.
Contains information about raised exceptions.


=== FALCON_CPUCTL ===
=== FALCON_SVEC_SPR ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 18
| FALCON_CPUCTL_IINVAL
| FALCON_SVEC_SPR_SIGPASS
|-
|}
 
=== FALCON_RSTAT0 ===
Mirror of the ICD status register 0.
 
=== FALCON_RSTAT3 ===
Mirror of the ICD status register 3.
 
=== FALCON_CPUCTL ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0
| FALCON_CPUCTL_IINVAL
|-
| 1
| 1
| FALCON_CPUCTL_STARTCPU
| FALCON_CPUCTL_STARTCPU
Line 1,469: Line 1,622:
|-
|-
| 6
| 6
| FALCON_CPUCTL_CPUCTL_ALIAS_EN
| FALCON_CPUCTL_ALIAS_EN
|}
|}


Line 1,656: Line 1,809:
|-
|-
| 0-23
| 0-23
| Address
| FALCON_IMCTL_ADDR_BLK
|-
|-
| 24-26
| 24-26
| Command
| FALCON_IMCTL_CMD
  0x00: NOP
  0x00: NOP
  0x01: IMINV (ITLB)
  0x01: IMINV (ITLB)
  0x02: IMBLK (PTLB)
  0x02: IMBLK (PTLB)
  0x03: IMTAG (VTLB)
  0x03: IMTAG (VTLB)
0x04: IMTAG_SETVLD
|}
|}


Line 1,813: Line 1,967:
  0x1B: CTX
  0x1B: CTX
  0x1C: EXCI
  0x1C: EXCI
0x1D: SEC1
0x1E: IMB1
0x1F: DMB1
|-
|-
| 14
| 14
Line 2,221: Line 2,378:
* [[#FALCON_IMSTAT|FALCON_IMSTAT]]
* [[#FALCON_IMSTAT|FALCON_IMSTAT]]
* FALCON_UNK_250
* FALCON_UNK_250
* FALCON_UNK_2E0
* FALCON_DMAINFO_CTL


=== FALCON_SPROT_IRQ ===
=== FALCON_SPROT_IRQ ===
Line 2,243: Line 2,400:
* FALCON_GPTMRVAL
* FALCON_GPTMRVAL
* FALCON_GPTMRCTL
* FALCON_GPTMRCTL
* FALCON_UNK_3C
* FALCON_IRQDEST2
* FALCON_UNK_E0
* FALCON_UNK_E0


Line 2,612: Line 2,769:


Contains information on crypto errors generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_INSN_ERROR]] IRQ.
Contains information on crypto errors generated by the [[#TSEC_SCP_IRQSTAT|TSEC_SCP_IRQSTAT_INSN_ERROR]] IRQ.
=== TSEC_TFBIF_CTL ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0
| TSEC_TFBIF_CTL_CLR_BWCOUNT
|-
| 1
| TSEC_TFBIF_CTL_ENABLE
|-
| 2
| TSEC_TFBIF_CTL_CLR_IDLEWDERR
|-
| 3
| TSEC_TFBIF_CTL_RESET
|-
| 4
| TSEC_TFBIF_CTL_IDLE
|-
| 5
| TSEC_TFBIF_CTL_IDLEWDERR
|-
| 6
| TSEC_TFBIF_CTL_SRTOUT
|-
| 7
| TSEC_TFBIF_CTL_CLR_SRTOUT
|-
| 8-11
| TSEC_TFBIF_CTL_SRTOVAL
|-
| 12
| TSEC_TFBIF_CTL_VPR
|}


=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
Line 2,658: Line 2,851:
|}
|}


=== TSEC_TFBIF_MMU_PROT ===
=== TSEC_TFBIF_THROTTLE ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-11
| TSEC_TFBIF_THROTTLE_BUCKET_SIZE
|-
| 16-27
| TSEC_TFBIF_THROTTLE_LEAK_COUNT
|-
| 30-31
| TSEC_TFBIF_THROTTLE_LEAK_SIZE
|}
 
=== TSEC_TFBIF_DBG_STAT0 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0
| TSEC_TFBIF_DBG_STAT0_1K_TRANSFER
|-
| 1
| TSEC_TFBIF_DBG_STAT0_RREQ_ISSUED
|-
| 2
| TSEC_TFBIF_DBG_STAT0_WREQ_ISSUED
|-
| 3
| TSEC_TFBIF_DBG_STAT0_TAGQ_ISSUED
|-
| 4
| TSEC_TFBIF_DBG_STAT0_STALL_RDATQ
|-
| 5
| TSEC_TFBIF_DBG_STAT0_STALL_RACKQ
|-
| 6
| TSEC_TFBIF_DBG_STAT0_STALL_WREQQ
|-
| 7
| TSEC_TFBIF_DBG_STAT0_STALL_WDATQ
|-
| 8
| TSEC_TFBIF_DBG_STAT0_STALL_WACKQ
|-
| 9
| TSEC_TFBIF_DBG_STAT0_STALL_RREQ_PENDING
|-
| 10
| TSEC_TFBIF_DBG_STAT0_STALL_WREQ_PENDING
|-
| 11
| TSEC_TFBIF_DBG_STAT0_STALL_MREQ
|-
| 12
| TSEC_TFBIF_DBG_STAT0_ENGINE_IDLE
|-
| 13
| TSEC_TFBIF_DBG_STAT0_RMCCIF_IDLE
|-
| 14
| TSEC_TFBIF_DBG_STAT0_WMCCIF_IDLE
|-
| 15
| TSEC_TFBIF_DBG_STAT0_CSB_IDLE
|-
| 16
| TSEC_TFBIF_DBG_STAT0_RU_IDLE
|-
| 17
| TSEC_TFBIF_DBG_STAT0_WU_IDLE
|-
| 19
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_ACTIVE
|-
| 20
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_MCB
|}
 
=== TSEC_TFBIF_SPROT_REGION ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 2,670: Line 2,944:
|}
|}


Controls accesses to external memory at the MMU level. Accessible in HS mode only.
Controls accesses to external memory regions. Accessible in HS mode only.


=== TSEC_TFBIF_MMU_PHYS_SEC ===
=== TSEC_TFBIF_REGIONCFG ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 2,678: Line 2,952:
|-
|-
| 0
| 0
| Bypass MMU translation on CTXDMA port 0
| TSEC_TFBIF_REGIONCFG_T0_VPR
|-
|-
| 4
| 4
| Bypass MMU translation on CTXDMA port 1
| TSEC_TFBIF_REGIONCFG_T1_VPR
|-
|-
| 8
| 8
| Bypass MMU translation on CTXDMA port 2
| TSEC_TFBIF_REGIONCFG_T2_VPR
|-
|-
| 12
| 12
| Bypass MMU translation on CTXDMA port 3
| TSEC_TFBIF_REGIONCFG_T3_VPR
|-
|-
| 16
| 16
| Bypass MMU translation on CTXDMA port 4
| TSEC_TFBIF_REGIONCFG_T4_VPR
|-
|-
| 20
| 20
| Bypass MMU translation on CTXDMA port 5
| TSEC_TFBIF_REGIONCFG_T5_VPR
|-
|-
| 24
| 24
| Bypass MMU translation on CTXDMA port 6
| TSEC_TFBIF_REGIONCFG_T6_VPR
|-
|-
| 28
| 28
| Bypass MMU translation on CTXDMA port 7
| TSEC_TFBIF_REGIONCFG_T7_VPR
|}
|}


Controls MMU bypass mode. Accessible in HS mode only.
Controls VPR request mode (which bypasses MMU). Accessible in HS mode only.


[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.


=== TSEC_TFBIF_MMU_APERTURE_CTL ===
=== TSEC_TFBIF_REGIONCFG1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 2,712: Line 2,986:
|-
|-
| 0-2
| 0-2
| Aperture ID for CTXDMA port 0
| TSEC_TFBIF_REGIONCFG1_T0_APERT_ID
|-
|-
| 4-6
| 4-6
| Aperture ID for CTXDMA port 1
| TSEC_TFBIF_REGIONCFG1_T1_APERT_ID
|-
|-
| 8-10
| 8-10
| Aperture ID for CTXDMA port 2
| TSEC_TFBIF_REGIONCFG1_T2_APERT_ID
|-
|-
| 12-14
| 12-14
| Aperture ID for CTXDMA port 3
| TSEC_TFBIF_REGIONCFG1_T3_APERT_ID
|-
|-
| 16-18
| 16-18
| Aperture ID for CTXDMA port 4
| TSEC_TFBIF_REGIONCFG1_T4_APERT_ID
|-
|-
| 20-22
| 20-22
| Aperture ID for CTXDMA port 5
| TSEC_TFBIF_REGIONCFG1_T5_APERT_ID
|-
|-
| 24-26
| 24-26
| Aperture ID for CTXDMA port 6
| TSEC_TFBIF_REGIONCFG1_T6_APERT_ID
|-
|-
| 28-30
| 28-30
| Aperture ID for CTXDMA port 7
| TSEC_TFBIF_REGIONCFG1_T7_APERT_ID
|}
|}


Line 2,740: Line 3,014:
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.


=== TSEC_TFBIF_ACTMON_MAMASK ===
=== TSEC_TFBIF_ACTMON_ACTIVE_MASK ===
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.


=== TSEC_TFBIF_ACTMON_BORPS ===
=== TSEC_TFBIF_ACTMON_ACTIVE_BORPS ===
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.


=== TSEC_TFBIF_ACTMON_CTL ===
=== TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT ===
Controls the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.
Controls the Activity Monitor. Disconnected on the TSEC, but available on NVDEC, NVENC and NVJPG.


Retrieved from "https://switchbrew.org/wiki/TSEC"