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# VERTEX_BUFFER_COUNT is set to 4, because the Vertex Buffer with the square has 4 vertices.
 
# VERTEX_BUFFER_COUNT is set to 4, because the Vertex Buffer with the square has 4 vertices.
 
# VERTEX_END_GL is used with value 0 (currently unknown what this value means).
 
# VERTEX_END_GL is used with value 0 (currently unknown what this value means).
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== Texture View ==
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Texture information such as address, format and size is sent to the GPU through a structure know as Texture View (a.k.a Texture Image Control, or TIC). Each texture that the game uses needs a separate TIC, and those TICs are written to a table, one after the other. Each [[#TIC_Structure|TIC entry]] has 0x20 bytes, and is composed of 8 32-bits words where the texture information is packed.
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The index of the TIC entries that should be used by the shader is sent to the GPU with the CB_POS/CB_DATA (0) methods. Games usually follows the following steps to write the TIC entry indexes:
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* CB_ADDRESS_HIGH/LOW method is used to set the GPU Virtual Address of the Const Buffer.
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* CB_POS is used to set the write offset of the Const Buffer to 0x20 + n * 4, where ''n'' is the is the index of the active texture that will be used by the shader (?).
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* CB_DATA (0) method is used to write the value into the Const Buffer. The value is a word where the lower 20 bits is the TIC index.
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The address of a given TIC entry can be calculates as:
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tic_entry_address = tic_base_address + tic_index * 0x20
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Where ''tic_base_address'' is the address written to TIC_ADDRESS_HIGH/LOW (methods 0x1574 and 0x1578), ''tic_index'' is the lower 20 bits of the word written into the Const Buffer with CB_DATA (0), and 0x20 is the size of each TIC entry in bytes.
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Note: More research still needs to be done on the Const Buffer and how it is used by the shader.
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=== TIC Structure ===
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{| class="wikitable" border="1"
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|-
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! Word || Bits || Description
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|-
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| 0 || 6-0 || [[GPU_Texture_Formats#Texture_Formats|Texture Format]]
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|-
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| 0 || 9-7 || [[#Channel_Data_Type|R Channel Data Type]]
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|-
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| 0 || 12-10 || [[#Channel_Data_Type|G Channel Data Type]]
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|-
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| 0 || 15-13 || [[#Channel_Data_Type|B Channel Data Type]]
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|-
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| 0 || 18-16 || [[#Channel_Data_Type|A Channel Data Type]]
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|-
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| 1 || 31-0 || Lower 32-bits of the Texture GPU Virtual Address
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|-
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| 2 || 15-0 || Higher 16-bits of the Texture GPU Virtual Address
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|-
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| 4 || 15-0 || Texture Width minus 1
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|-
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| 5 || 15-0 || Texture Height minus 1
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|}
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==== Channel Data Type ====
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{| class="wikitable" border="1"
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|-
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! Value || Type
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|-
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| 1 || SNORM
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|-
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| 2 || UNORM
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|-
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| 3 || SINT
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|-
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| 4 || UINT
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|-
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| 5 || SNORM_FORCE_FP16
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|-
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| 6 || UNORM_FORCE_FP16
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|-
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| 7 || FLOAT
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|}
    
== References ==
 
== References ==
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Method values from the Fermi family GPU (a bit older than the Tegra X1, but values seems to be mostly the same):
 
Method values from the Fermi family GPU (a bit older than the Tegra X1, but values seems to be mostly the same):
 
[https://github.com/envytools/envytools/blob/master/rnndb/graph/gf100_3d.xml]
 
[https://github.com/envytools/envytools/blob/master/rnndb/graph/gf100_3d.xml]
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TIC structure used on a Maxwell GPU:
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[https://github.com/envytools/envytools/blob/master/rnndb/graph/gm200_texture.xml]
    
Values for some types used on the above XML:
 
Values for some types used on the above XML:
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Command word packing code used on Mesa3d:
 
Command word packing code used on Mesa3d:
 
[https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h]
 
[https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h]
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TIC entry pack/write code used on Mesa3d:
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[https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c#n65]
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