TSEC: Difference between revisions - Nintendo Switch Brew

Line 1:

~~Like most~~ Tegra ~~based devices, the Switch's GPU also includes a Falcon microprocessor.~~

TSEC (Tegra Security Engine Controller) is a NVIDIA Falcon microprocessor with crypto extensions. Therefore, all information in this page related to Falcon is identical for TSEC and vice versa.

~~TSEC~~ is a NVIDIA Falcon microprocessor with crypto extensions.

= Driver =

Line 146:

Line 145:

= Boot Process =

~~The Falcon~~ is configured and initialized by the first bootloader during key generation (sub_400114FC).

TSEC is configured and initialized by the first bootloader during key generation (sub_400114FC).

== Initialization ==

During this stage several clocks are programmed.

// Program the HOST1X clock and resets

~~set_host1x_clkrst~~();

// Uses RST_DEVICES_L, CLK_OUT_ENB_L, CLK_SOURCE_HOST1X and CLK_L_HOST1X

enable_host1x_clkrst();

// Program the TSEC clock and resets

~~set_tsec_clkrst~~();

// Uses RST_DEVICES_U, CLK_OUT_ENB_U, CLK_SOURCE_TSEC and CLK_U_TSEC

enable_tsec_clkrst();

// Program the ~~QSPI~~ clock and resets ~~(no source)~~

// Program the SOR_SAFE clock and resets

~~set_qspi_clkrst~~();

// Uses RST_DEVICES_Y, CLK_OUT_ENB_Y and CLK_Y_SOR_SAFE

enable_sor_safe_clkrst();

// Program the ~~SOR1~~ clock and resets ~~(no source)~~

// Program the SOR0 clock and resets

~~set_sor1_clkrst0~~();

// Uses RST_DEVICES_X, CLK_OUT_ENB_X and CLK_X_SOR0

enable_sor0_clkrst();

// Program the SOR1 clock and resets

~~set_sor1_clkrst1~~();

// Uses RST_DEVICES_X, CLK_OUT_ENB_X, CLK_SOURCE_SOR1 and CLK_X_SOR1

enable_sor1_clkrst();

// ~~Enable~~ clock and ~~resets for H group~~

// Program the KFUSE clock resets

~~set_h_clkrst~~();

// Uses RST_DEVICES_H, CLK_OUT_ENB_H and CLK_H_KFUSE

enable_kfuse_clkrst();

== Configuration ==

Line 265:

Line 270:

// Copy back the Falcon key

memcpy(out_buf, falcon_device_key, out_size);

// Deprogram ~~UARTC and I2C5~~ clock and resets

// Deprogram KFUSE clock and resets

~~unset_uartc_i2c5_clkrst~~();

// Uses RST_DEVICES_H, CLK_OUT_ENB_H and CLK_H_KFUSE

disable_kfuse_clkrst();

// Deprogram SOR1 clock and resets

~~unset_sor1_clkrst1~~();

// Uses RST_DEVICES_X, CLK_OUT_ENB_X, CLK_SOURCE_SOR1 and CLK_X_SOR1

disable_sor1_clkrst();

// Deprogram ~~SOR1~~ clock and resets ~~(no source)~~

// Deprogram SOR0 clock and resets

~~unset_sor1_clkrst0~~();

// Uses RST_DEVICES_X, CLK_OUT_ENB_X and CLK_X_SOR0

disable_sor0_clkrst();

// Deprogram ~~QSPI~~ clock and resets ~~(no source)~~

// Deprogram SOR_SAFE clock and resets

~~unset_qspi_clkrst~~();

// Uses RST_DEVICES_Y, CLK_OUT_ENB_Y and CLK_Y_SOR_SAFE

disable_sor_safe_clkrst();

// Deprogram TSEC clock and resets

~~unset_tsec_clkrst~~();

// Uses RST_DEVICES_U, CLK_OUT_ENB_U, CLK_SOURCE_TSEC and CLK_U_TSEC

disable_tsec_clkrst();

// Deprogram HOST1X clock and resets

~~unset_host1x_clkrst~~()

// Uses RST_DEVICES_L, CLK_OUT_ENB_L, CLK_SOURCE_HOST1X and CLK_L_HOST1X

disable_host1x_clkrst();

return;

@@ Line 1: / Line 1: @@
-Like most Tegra based devices, the Switch's GPU also includes a Falcon microprocessor.
+TSEC (Tegra Security Engine Controller) is a NVIDIA Falcon microprocessor with crypto extensions. Therefore, all information in this page related to Falcon is identical for TSEC and vice versa.
-TSEC is a NVIDIA Falcon microprocessor with crypto extensions.
 = Driver =
@@ Line 146: / Line 145: @@
 = Boot Process =
-The Falcon is configured and initialized by the first bootloader during key generation (sub_400114FC).
+TSEC is configured and initialized by the first bootloader during key generation (sub_400114FC).
 == Initialization ==
 During this stage several clocks are programmed.
   // Program the HOST1X clock and resets
-  set_host1x_clkrst();
+  // Uses RST_DEVICES_L, CLK_OUT_ENB_L, CLK_SOURCE_HOST1X and CLK_L_HOST1X
+ enable_host1x_clkrst();
   // Program the TSEC clock and resets
-  set_tsec_clkrst();
+  // Uses RST_DEVICES_U, CLK_OUT_ENB_U, CLK_SOURCE_TSEC and CLK_U_TSEC
+ enable_tsec_clkrst();
-  // Program the QSPI clock and resets (no source)
+  // Program the SOR_SAFE clock and resets
-  set_qspi_clkrst();
+  // Uses RST_DEVICES_Y, CLK_OUT_ENB_Y and CLK_Y_SOR_SAFE
+ enable_sor_safe_clkrst();
-  // Program the SOR1 clock and resets (no source)
+  // Program the SOR0 clock and resets
-  set_sor1_clkrst0();
+  // Uses RST_DEVICES_X, CLK_OUT_ENB_X and CLK_X_SOR0
+ enable_sor0_clkrst();
   // Program the SOR1 clock and resets
-  set_sor1_clkrst1();
+  // Uses RST_DEVICES_X, CLK_OUT_ENB_X, CLK_SOURCE_SOR1 and CLK_X_SOR1
+ enable_sor1_clkrst();
-  // Enable clock and resets for H group
+  // Program the KFUSE clock resets
-  set_h_clkrst();
+ // Uses RST_DEVICES_H, CLK_OUT_ENB_H and CLK_H_KFUSE
+  enable_kfuse_clkrst();
 == Configuration ==
@@ Line 265: / Line 270: @@
   // Copy back the Falcon key
   memcpy(out_buf, falcon_device_key, out_size);
-  // Deprogram UARTC and I2C5 clock and resets
+  // Deprogram KFUSE clock and resets
-  unset_uartc_i2c5_clkrst();
+  // Uses RST_DEVICES_H, CLK_OUT_ENB_H and CLK_H_KFUSE
+ disable_kfuse_clkrst();
   // Deprogram SOR1 clock and resets
-  unset_sor1_clkrst1();
+  // Uses RST_DEVICES_X, CLK_OUT_ENB_X, CLK_SOURCE_SOR1 and CLK_X_SOR1
+ disable_sor1_clkrst();
-  // Deprogram SOR1 clock and resets (no source)
+  // Deprogram SOR0 clock and resets
-  unset_sor1_clkrst0();
+  // Uses RST_DEVICES_X, CLK_OUT_ENB_X and CLK_X_SOR0
+ disable_sor0_clkrst();
-  // Deprogram QSPI clock and resets (no source)
+  // Deprogram SOR_SAFE clock and resets
-  unset_qspi_clkrst();
+  // Uses RST_DEVICES_Y, CLK_OUT_ENB_Y and CLK_Y_SOR_SAFE
+ disable_sor_safe_clkrst();
   // Deprogram TSEC clock and resets
-  unset_tsec_clkrst();
+  // Uses RST_DEVICES_U, CLK_OUT_ENB_U, CLK_SOURCE_TSEC and CLK_U_TSEC
+ disable_tsec_clkrst();
   // Deprogram HOST1X clock and resets
-  unset_host1x_clkrst()
+  // Uses RST_DEVICES_L, CLK_OUT_ENB_L, CLK_SOURCE_HOST1X and CLK_L_HOST1X
+ disable_host1x_clkrst();
   return;