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Takes two input u32s '''Fd''' and '''EvtId'''. Returns an output u32 '''Err''' and an output Event handle.
Takes two input u32s '''Fd''' and '''EvtId'''. Returns an output u32 '''Err''' and an output Event handle.


QueryEvent is only supported on (and implemented differently on):
QueryEvent is only supported by:
* /dev/nvhost-gpu
* '''/dev/nvcec-ctrl'''
** EvtId=1: SmException_BptIntReport
** EvtId=0
** EvtId=2: SmException_BptPauseReport
** EvtId=1
** EvtId=2
** EvtId=3
** EvtId=4
** EvtId=5
** EvtId=6
** EvtId=7
** EvtId=8
** EvtId=9
 
* '''/dev/nvhdcp_up-ctrl'''
** EvtId=0: DphdcpStateEvent
 
* '''/dev/nvdisp-ctrl'''
** EvtId=0: HpdInEvent
** EvtId=1: HpdOutEvent
** EvtId=2: VblankHead0Event
 
* '''/dev/nvhost-gpu'''
** EvtId=1: BptIntEvent
** EvtId=2: BptPauseEvent
** EvtId=3: ErrorNotifierEvent
** EvtId=3: ErrorNotifierEvent
* /dev/nvhost-ctrl: Used to get events for syncpts.
 
** EvtId=(event_slot | ((syncpt_id & 0xFFF) << 16) | (is_valid << 28)): New format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]/[[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]].
* '''/dev/nvhost-ctrl'''
** EvtId=(event_slot | (syncpt_id << 4)): Old format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]].
** EvtId=(EventSlot | ((SyncptId & 0xFFF) << 16) | (IsValid << 28)): New format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]/[[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]].
* /dev/nvhost-ctrl-gpu
** EvtId=(EventSlot | (SyncptId << 4)): Old format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]].
** EvtId=1: Returns error_event_handle.
 
** EvtId=2: Returns unknown event.
* '''/dev/nvhost-ctrl-gpu'''
* /dev/nvhost-dbg-gpu
** EvtId=1: ErrorEvent
** Ignores EvtId.
** EvtId=2: SemaphoreEvent
 
* '''/dev/nvhost-dbg-gpu'''
** EvtId=Any: DbgEvents
 
* '''/dev/nvsched-ctrl'''
** EvtId=0: ApplicationAddedEvent
** EvtId=1: ApplicationUpdatedEvent
** EvtId=2: ApplicationMaxDebtUpdatedEvent
** EvtId=3: ApplicationRemovedEvent
** EvtId=4: ApplicationDetachedEvent
** EvtId=5: RunlistAddedEvent
** EvtId=6: RunlistUpdatedEvent
** EvtId=7: RunlistMaxDebtUpdatedEvent
** EvtId=8: RunlistLinkedEvent
** EvtId=9: RunlistUnlinkedEvent
** EvtId=10: RunlistRemovedEvent
** EvtId=11: ConductorSwapintervalUpdatedEvent
** EvtId=12: ChannelAcquiredEvent
** EvtId=13: ChannelReleasedEvent


== MapSharedMem ==
== MapSharedMem ==
Line 299: Line 338:
|-
|-
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]
|-
| 0xC0080027 || Inout || 8 || [S2] NVHOST_IOCTL_CTRL_ALLOC_SYNCPT
|-
| 0x40040028 || In || 4 || [S2] NVHOST_IOCTL_CTRL_FREE_SYNCPT
|-
| 0xC010002A || Inout || 16 || [S2] NVHOST_IOCTL_CTRL_GET_CHARACTERISTICS
|-
| 0xC008002B || Inout || 8 || [S2] NVHOST_IOCTL_CTRL_CHECK_MODULE_SUPPORT
|}
|}


Line 601: Line 648:
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
|-
|-
| ([1.0.0-3.0.0] 0xC0040217) || ([1.0.0-3.0.0] Inout) || ([1.0.0-3.0.0] 4) || ([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_OUT_EVENT)
| 0xC0040217 || Inout || 4 || [1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_OUT_EVENT
|-
|-
| 0xC0100218 || Inout || 16 || NVDISP_CTRL_GET_VBLANK_HEAD0_EVENT
| 0xC0100218 || Inout || 16 || NVDISP_CTRL_GET_VBLANK_HEAD0_EVENT
Line 625: Line 672:


   struct {
   struct {
     __out u8 isOLED;
     __out u8 is_display_oled;
   };
   };


Line 1,295: Line 1,342:
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
|-
|-
| 0x8010410B || Out || 16 || [S2]
| 0x8010410B || Out || 16 || [S2] NVGPU_AS_IOCTL_GET_SYNC_RO_MAP
|-
|-
| 0xC020410C || Inout || 32 || [S2]
| 0xC020410C || Inout || 32 || [S2] NVGPU_AS_IOCTL_MAPPING_MODIFY
|-
|-
| 0xC???410D || Inout || Variable || [S2]
| 0xC???410D || Inout || Variable || [S2] NVGPU_AS_IOCTL_REMAP
|-
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
Line 1,501: Line 1,548:
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
|-
|-
| 0xC0684413 || Inout || 104 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
| 0xC0684413</br>[S2] 0xC0304413 || Inout || 104</br>48 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
|-
|-
| 0xC0184414 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
| 0xC0184414</br>[S2] 0xC0084414 || Inout || 24</br>8 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
|-
|-
| 0xC0184415 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
| 0xC0184415</br>[S2] 0xC0084415 || Inout || 24</br>8 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
|-
|-
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
Line 1,525: Line 1,572:
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
|-
|-
| [S2] 0xC0184421 || || ||
| 0x4008441F || In || 8 || [S2]
|-
|-
| [S2] 0x40084422 || || ||
| 0x00004420 || None || 0 || [S2]
|-
|-
| [S2] 0xC0084423 || || ||
| 0xC0184421 || Inout || 24 || [S2]
|-
|-
| [S2] 0x40084424 || || ||
| 0x40084422 || In || 8 || [S2]
|-
|-
| [S2] 0xC0104425 || || ||
| 0xC0084423 || Inout || 8 || [S2]
|-
|-
| [S2] 0x40084427 || || ||
| 0x40084424 || In || 8 || [S2]
|-
|-
| [S2] 0x40044428 || || ||
| 0xC0104425 || Inout || 16 || [S2]
|-
|-
| [S2] 0xC0184429 || || ||
| 0xC0184426 || Inout || 24 || [S2]
|-
|-
| [S2] 0x4010442A || || ||
| 0x40084427 || In || 8 || [S2]
|-
|-
| [S2] 0x4010442B || || ||
| 0x40044428 || In || 4 || [S2]  
|-
| 0xC0184429 || Inout || 24 || [S2]
|-
| 0x4010442A || In || 16 || [S2]
|-
| 0x4010442B || In || 16 || [S2]
|}
|}


Line 1,580: Line 1,633:
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
|-
|-
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
| 0xC0B04705</br>[S2] 0xC0E04705 || Inout || 176</br>[S2] 224|| [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
|-
|-
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
Line 1,598: Line 1,651:
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
|-
|-
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
| 0xC0044713</br>[S2] 0xC0084713 || Inout || 4</br>[S2] 8 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
|-
|-
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
Line 1,619: Line 1,672:
|-
|-
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
|-
| 0xC010471E || Inout || 16 || [S2]
|-
| 0xC010471F || Inout || 16 || [S2]
|}
|}


Line 1,674: Line 1,731:


   struct gpu_characteristics {
   struct gpu_characteristics {
     u32 arch;                       // 0x120 (NVGPU_GPU_ARCH_GM200)
     u32 arch;                         // 0x120 (NVGPU_GPU_ARCH_GM200)
     u32 impl;                       // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
     u32 impl;                         // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
     u32 rev;                       // 0xA1 (Revision A1)
     u32 rev;                         // 0xA1 (Revision A1)
     u32 num_gpc;                   // 0x1
     u32 num_gpc;                     // 0x1
     u64 l2_cache_size;             // 0x40000
     u64 l2_cache_size;               // 0x40000
     u64 on_board_video_memory_size; // 0x0 (not used)
     u64 on_board_video_memory_size;   // 0x0 (not used)
     u32 num_tpc_per_gpc;           // 0x2
     u32 num_tpc_per_gpc;             // 0x2
     u32 bus_type;                   // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
     u32 bus_type;                     // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
     u32 big_page_size;             // 0x20000
     u32 big_page_size;               // 0x20000
     u32 compression_page_size;     // 0x20000
     u32 compression_page_size;       // 0x20000
     u32 pde_coverage_bit_count;     // 0x1B
     u32 pde_coverage_bit_count;       // 0x1B
     u32 available_big_page_sizes;   // 0x30000
     u32 available_big_page_sizes;     // 0x30000
     u32 gpc_mask;                   // 0x1
     u32 gpc_mask;                     // 0x1
     u32 sm_arch_sm_version;         // 0x503 (Maxwell Generation 5.0.3)
     u32 sm_arch_sm_version;           // 0x503 (Maxwell Generation 5.0.3)
     u32 sm_arch_spa_version;       // 0x503 (Maxwell Generation 5.0.3)
     u32 sm_arch_spa_version;         // 0x503 (Maxwell Generation 5.0.3)
     u32 sm_arch_warp_count;         // 0x80
     u32 sm_arch_warp_count;           // 0x80
     u32 gpu_va_bit_count;           // 0x28
     u32 gpu_va_bit_count;             // 0x28
     u32 reserved;                   // NULL
     u32 reserved;                     // 0x0
     u64 flags;                     // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
     u64 flags;                       // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
     u32 twod_class;                 // 0x902D (FERMI_TWOD_A)
     u32 twod_class;                   // 0x902D (FERMI_TWOD_A)
     u32 threed_class;               // 0xB197 (MAXWELL_B)
     u32 threed_class;                 // 0xB197 (MAXWELL_B)
     u32 compute_class;             // 0xB1C0 (MAXWELL_COMPUTE_B)
     u32 compute_class;               // 0xB1C0 (MAXWELL_COMPUTE_B)
     u32 gpfifo_class;               // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
     u32 gpfifo_class;                 // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
     u32 inline_to_memory_class;     // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
     u32 inline_to_memory_class;       // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
     u32 dma_copy_class;             // 0xB0B5 (MAXWELL_DMA_COPY_A)
     u32 dma_copy_class;               // 0xB0B5 (MAXWELL_DMA_COPY_A)
     u32 max_fbps_count;             // 0x1
     u32 max_fbps_count;               // 0x1
     u32 fbp_en_mask;               // 0x0 (disabled)
     u32 fbp_en_mask;                 // 0x0 (disabled)
     u32 max_ltc_per_fbp;           // 0x2
     u32 max_ltc_per_fbp;             // 0x2
     u32 max_lts_per_ltc;           // 0x1
     u32 max_lts_per_ltc;             // 0x1
     u32 max_tex_per_tpc;           // 0x0 (not supported)
     u32 max_tex_per_tpc;             // 0x0 (not supported)
     u32 max_gpc_count;             // 0x1
     u32 max_gpc_count;               // 0x1
     u32 rop_l2_en_mask_0;           // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
     u32 rop_l2_en_mask_0;             // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
     u32 rop_l2_en_mask_1;           // 0x0
     u32 rop_l2_en_mask_1;             // 0x0
     u64 chipname;                   // 0x6230326D67 ("gm20b")
     u64 chipname;                     // 0x6230326D67 ("gm20b")
     u64 gr_compbit_store_base_hw;   // 0x0 (not supported)
     u64 gr_compbit_store_base_hw;     // 0x0 (not supported)
   };
   };
   
   
Line 1,715: Line 1,772:
     __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
     __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
     __out struct gpu_characteristics gc;
     __out struct gpu_characteristics gc;
  };
[S2] Uses [[#Ioctl3|Ioctl3]].
  struct gpu_characteristics {
    u32 arch;                        // 0x170
    u32 impl;                        // 0xE
    u32 rev;                          // 0xA1 (Revision A1)
    u32 num_gpc;                      // 0x1
    u64 l2_cache_size;                // 0x100000
    u64 on_board_video_memory_size;  // 0x0 (not used)
    u32 num_tpc_per_gpc;              // 0x6
    u32 bus_type;                    // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
    u32 big_page_size;                // 0x0
    u32 compression_page_size;        // 0x10000
    u32 pde_coverage_bit_count;      // 0x15
    u32 available_big_page_sizes;    // 0x0
    u32 gpc_mask;                    // 0x1
    u32 sm_arch_sm_version;          // 0x808
    u32 sm_arch_spa_version;          // 0x806
    u32 sm_arch_warp_count;          // 0x60
    u32 gpu_va_bit_count;            // 0x28
    u32 reserved;                    // 0x0
    u64 flags;                        // 0x935FAF1EDC0155
    u32 twod_class;                  // 0x902D (FERMI_TWOD_A)
    u32 threed_class;                // 0xC797 (AMPERE_B)
    u32 compute_class;                // 0xC7C0 (AMPERE_COMPUTE_B)
    u32 gpfifo_class;                // 0xC76F (AMPERE_CHANNEL_GPFIFO_B)
    u32 inline_to_memory_class;      // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
    u32 dma_copy_class;              // 0xC7B5 (AMPERE_DMA_COPY_B)
    s16 gpu_ioctl_nr_last;            // 0x1F
    s16 tsg_ioctl_nr_last;            // 0xF
    s16 dbg_gpu_ioctl_nr_last;        // 0x2B
    s16 ioctl_channel_nr_last;        // 0x21
    s16 as_ioctl_nr_last;            // 0xD
    s16 unk0_ioctl_nr_last;          // 0xFFFF
    s16 unk1_ioctl_nr_last;          // 0xFFFF
    s16 unk2_ioctl_nr_last;          // 0xFFFF
    u32 max_fbps_count;              // 0x0
    u32 fbp_en_mask;                  // 0x1
    u32 emc_en_mask;                  // 0x1
    u32 max_ltc_per_fbp;              // 0x1
    u32 max_lts_per_ltc;              // 0x4
    u32 max_tex_per_tpc;              // 0x0
    u32 max_gpc_count;                // 0x1
    u32 rop_l2_en_mask_DEPRECATED_0;  // 0x0
    u32 rop_l2_en_mask_DEPRECATED_1;  // 0x0
    u64 chipname;                    // 0x6761313066 ("ga10f")
    u32 unk0;                        // 0x0
    u32 unk1;                        // 0x2
    u32 unk2;                        // 0x40
    u32 unk3;                        // 0x3
    u32 unk4;                        // 0x7
    u32 unk5;                        // 0x1
    u32 unk6;                        // 0x1
    u32 unk7;                        // 0x0
    u32 unk8;                        // 0x0
  };
 
  struct in_buf {
    __in    u64 gpu_characteristics_buf_size;  // must not be NULL, but gets overwritten with 0xD0=max_size
    __in    u8 reserved[0xD8];
  };
 
  struct out_buf {
    __out  u8 reserved[0xE0];
  };
 
  struct out_buf2 {
    __out struct gpu_characteristics gc;
   };
   };


Line 1,889: Line 2,016:
  };
  };


= Channels =
== (Switch 2) /dev/nvhost-prof-dev-gpu ==                                                                                                         
Channels are a concept for NVIDIA hardware blocks that share a common interface.
{| class="wikitable" border="1"
 
! Value || Direction || Size || Description
|-
| 0x40085001 || In || 8 || NVGPU_PROFILER_IOCTL_BIND_CONTEXT
|-
| 0x40105002 || In || 16 || NVGPU_PROFILER_IOCTL_RESERVE_PM_RESOURCE
|-
| 0x40085003 || In || 8 || NVGPU_PROFILER_IOCTL_RELEASE_PM_RESOURCE
|-
| 0xC0305004 || Inout || 48 || NVGPU_PROFILER_IOCTL_ALLOC_PMA_STREAM
|-
| 0x00005005 || None || 0 || NVGPU_PROFILER_IOCTL_FREE_PMA_STREAM
|-
| 0x00005006 || None || 0 || NVGPU_PROFILER_IOCTL_BIND_PM_RESOURCES
|-
| 0x00005007 || None || 0 || NVGPU_PROFILER_IOCTL_UNBIND_PM_RESOURCES
|-
| 0xC0285008 || Inout || 40 || NVGPU_PROFILER_IOCTL_PMA_STREAM_UPDATE_GET_PUT
|-
| 0xC0205009 || Inout || 32 || NVGPU_PROFILER_IOCTL_EXEC_REG_OPS
|-
| 0x0000500A || None || 0 || NVGPU_PROFILER_IOCTL_UNBIND_CONTEXT
|-
| 0x4010500B || In || 16 || NVGPU_PROFILER_IOCTL_VAB_RESERVE
|-
| 0x0000500C || None || 0 || NVGPU_PROFILER_IOCTL_VAB_RELEASE
|-
| 0x4010500D || In || 16 || NVGPU_PROFILER_IOCTL_VAB_FLUSH_STATE
|}
 
== (Switch 2) /dev/nvhost-tsg-gpu ==                                                                                   
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0xC0045401 || Inout || 4 || NVGPU_TSG_IOCTL_BIND_CHANNEL
|-
| 0xC0045402 || Inout || 4 || NVGPU_TSG_IOCTL_UNBIND_CHANNEL
|-
| 0x00005403 || None || 0 || NVGPU_IOCTL_TSG_ENABLE
|-
| 0x00005404 || None || 0 || NVGPU_IOCTL_TSG_DISABLE
|-
| 0x00005405 || None || 0 || NVGPU_IOCTL_TSG_PREEMPT
|-
| 0xC0085407 || Inout || 8 || NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE
|-
| 0xC0045408 || Inout || 4 || NVGPU_IOCTL_TSG_SET_TIMESLICE
|-
| 0xC0105409 || Inout || 16 ||
|-
| 0x8004540A || Out || 4 ||
|-
| 0xC018540B || Inout || 24 ||
|-
| 0xC018540C || Inout || 24 ||
|-
| 0xC008540D || Inout || 8 || NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION
|}
 
= Channels =
Channels are a concept for NVIDIA hardware blocks that share a common interface.
 
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Path || Name
! Path || Name
Line 1,912: Line 2,099:
== Ioctls ==
== Ioctls ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
! Value || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
| 0xC0??0001 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
|-
|-
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
| 0xC0080002 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
|-
|-
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
| 0xC0080003 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
|-
|-
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
| 0xC0080004 || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
|-
|-
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
| 0x40040007 || In || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
|-
|-
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
| 0x40080008 || In || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
|-
|-
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
| 0xC0??0009 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
|-
|-
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
| 0xC0??000A || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
|-
|-
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
| 0x00000013 || None || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
|-
|-
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || Inout || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
|-
|-
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
| 0xC0??0024 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
|-
|-
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
| 0xC0??0025 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
|-
|-
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
| 0xC0??0026 || Inout || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
|- style="border-top: double"
|- style="border-top: double"
| 0x40044801 [S2] 0x40044101 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
| 0x40044801 || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
|-
| 0x40044803 || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
|-
|-
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
| 0x40084805 || In || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
|-
|-
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
| 0x40184806 || In || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
|-
|-
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
| 0xC0044807 || Inout || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
|-
|-
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
| 0xC0??4808 || Inout || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
|-
|-
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
| 0xC0104809 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
|-
|-
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
| 0x4008480A || In || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
|-
|-
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
| 0xC010480B || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
|-
|-
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
| 0xC018480C || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
|-
|-
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
| 0x4004480D || In || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
|-
|-
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
| 0x0000480E || None || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
|-
|-
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
| 0x0000480F || None || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
|-
|-
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
| 0x00004810 || None || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
|-
|-
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
| 0x00004811 || None ||  0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
|-
|-
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
| 0x40084812</br>[S2] 0x40104812 || In || 8</br>[S2] 16 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
|-
|-
| 0x40084812 [S2] 0x40104812 || 8 [S2] 16 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
| 0xC0104813 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
|-
|-
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
| 0x40084714 || In || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
|-
|-
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
| 0x80084715 || Out || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
|-
|-
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
| 0x80804816 || Out || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
|-
|-
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
| 0xC0104817 || Inout || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
|-
|-
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
| 0x40204818 || In || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
|-
|-
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
| 0xC0??4819 || Inout || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
|-
|-
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
| 0xC020481A || Inout || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
|-
|-
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
| 0xC018481B || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
|-
|-
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
| 0xC018481C || Inout || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
|-
|-
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
| 0xC004481D || Inout || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
|-
|-
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
| 0xC010481E || Inout || 16 || [S2]  
|- style="border-top: double"
| [S2] 0xC010481E || 16 ||
|-
|-
| [S2] 0xC008481F || 8 ||
| 0xC008481F || Inout || 8 || [S2]
|-
|-
| [S2] 0x40044820 || 4 ||  
| 0x40044820 || In || 4 || [S2]
|-
|-
| [S2] 0xC0504821 || 80 ||  
| 0xC0504821 || Inout || 80 || [S2]
|}
|}


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