NV services: Difference between revisions
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! Value || Direction || Size || Description | ! Value || Direction || Size || Description | ||
|- | |- | ||
| 0x80040212 || Out || 4 || NVDISP_CTRL_NUM_OUTPUTS | | 0x80040212 || Out || 4 || [[#NVDISP_CTRL_NUM_OUTPUTS]] | ||
|- | |- | ||
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES | | 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES | ||
|- | |- | ||
| 0xC1100214 || Inout || 272 || NVDISP_CTRL_QUERY_EDID | | 0xC2100214</br>([1.0.0-11.0.1] 0xC1100214) || Inout || 528</br>([1.0.0-11.0.1] 272) || NVDISP_CTRL_QUERY_EDID | ||
|- | |- | ||
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT) | | 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT) | ||
| Line 609: | Line 609: | ||
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND | | 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND | ||
|- | |- | ||
| 0x80010224 || Out || 1 || [11.0.0+] NVDISP_CTRL_IS_DISPLAY_OLED | | 0x80010224 || Out || 1 || [11.0.0+] [[#NVDISP_CTRL_IS_DISPLAY_OLED]] | ||
|} | |} | ||
=== NVDISP_CTRL_NUM_OUTPUTS === | |||
struct { | |||
__out u32 num_outputs; | |||
}; | |||
=== NVDISP_CTRL_IS_DISPLAY_OLED === | |||
This sets a boolean value based on the values of the system configuration. | |||
Returns true if "nvservices!internal_display_vddpn_control" is set to false and "nvservices!external_display_full_dp_lanes" is set to true. | |||
struct { | |||
__out u8 is_display_oled; | |||
}; | |||
== /dev/nvdisp-disp0, /dev/nvdisp-disp1 == | == /dev/nvdisp-disp0, /dev/nvdisp-disp1 == | ||
| Line 1,278: | Line 1,294: | ||
|- | |- | ||
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]] | | 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]] | ||
|- | |||
| 0x8010410B || Out || 16 || [S2] | |||
|- | |||
| 0xC020410C || Inout || 32 || [S2] | |||
|- | |||
| 0xC???410D || Inout || Variable || [S2] | |||
|- | |- | ||
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]] | | 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]] | ||
| Line 1,502: | Line 1,524: | ||
|- | |- | ||
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES | | 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES | ||
|- | |||
| [S2] 0xC0184421 || || || | |||
|- | |||
| [S2] 0x40084422 || || || | |||
|- | |||
| [S2] 0xC0084423 || || || | |||
|- | |||
| [S2] 0x40084424 || || || | |||
|- | |||
| [S2] 0xC0104425 || || || | |||
|- | |||
| [S2] 0x40084427 || || || | |||
|- | |||
| [S2] 0x40044428 || || || | |||
|- | |||
| [S2] 0xC0184429 || || || | |||
|- | |||
| [S2] 0x4010442A || || || | |||
|- | |||
| [S2] 0x4010442B || || || | |||
|} | |} | ||
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| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]] | | 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]] | ||
|- style="border-top: double" | |- style="border-top: double" | ||
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]] | | 0x40044801 [S2] 0x40044101 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]] | ||
|- | |- | ||
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]] | | 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]] | ||
| Line 1,928: | Line 1,970: | ||
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]] | | 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]] | ||
|- | |- | ||
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]] | | 0x40084812 [S2] 0x40104812 || 8 [S2] 16 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]] | ||
|- | |- | ||
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]] | | 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]] | ||
|- | |||
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]] | |||
|- | |||
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]] | |||
|- | |- | ||
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]] | | 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]] | ||
| Line 1,948: | Line 1,994: | ||
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]] | | 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]] | ||
|- style="border-top: double" | |- style="border-top: double" | ||
| | | [S2] 0xC010481E || 16 || | ||
|- | |||
| [S2] 0xC008481F || 8 || | |||
|- | |||
| [S2] 0x40044820 || 4 || | |||
|- | |- | ||
| | | [S2] 0xC0504821 || 80 || | ||
|} | |} | ||