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NV services: Difference between revisions

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m Fix NVMAP_IOC_ALLOC align param to be __inout
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Line 66: Line 66:
QueryEvent is only supported on (and implemented differently on):
QueryEvent is only supported on (and implemented differently on):
* /dev/nvhost-gpu
* /dev/nvhost-gpu
** 1: SmException_BptIntReport
** EvtId=1: SmException_BptIntReport
** 2: SmException_BptPauseReport
** EvtId=2: SmException_BptPauseReport
** 3: ErrorNotifierEvent
** EvtId=3: ErrorNotifierEvent
* /dev/nvhost-ctrl: Used to get events for SyncPts.
* /dev/nvhost-ctrl: Used to get events for syncpts.
** If bit31-28 is 1, then lower 16-bits contain event_slot, bit27-16 contain syncpt_number.  
** EvtId=(event_slot | ((syncpt_id & 0xFFF) << 16) | (is_valid << 28)): New format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]/[[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]].
** If bit31-28 is 0, then lower 4-bits contain event_slot, bit31-4 contains syncpt_number.
** EvtId=(event_slot | (syncpt_id << 4)): Old format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]].
* /dev/nvhost-ctrl-gpu
* /dev/nvhost-ctrl-gpu
** 1: Returns error_event_handle.
** EvtId=1: Returns error_event_handle.
** 2: Returns unknown event.
** EvtId=2: Returns unknown event.
* /dev/nvhost-dbg-gpu
* /dev/nvhost-dbg-gpu
** Ignores event_id.
** Ignores EvtId.


== MapSharedMem ==
== MapSharedMem ==
Line 187: Line 187:
| 6 || [[#Reset|Reset]]
| 6 || [[#Reset|Reset]]
|-
|-
| 7 || [3.0.0+]
| 7 || [3.0.0+] [[#GetAruid2|GetAruid2]]
|}
|}


Line 210: Line 210:
== Reset ==
== Reset ==
No input. Returns an output u32 '''Err'''.
No input. Returns an output u32 '''Err'''.
== GetAruid2 ==
Unofficial name.
No input. Returns an output u64 '''Aruid''', an output bool '''IsCoreDumpEnabled''' and an output u32 '''Err'''.


= nvgem:cd =
= nvgem:cd =
Line 224: Line 229:
| 2 || [1.0.0-8.1.0] [[#ReadNextBlock|ReadNextBlock]]
| 2 || [1.0.0-8.1.0] [[#ReadNextBlock|ReadNextBlock]]
|-
|-
| 3 || [8.0.0+]
| 3 || [8.0.0+] [[#GetNextBlockSize|GetNextBlockSize]]
|-
|-
| 4 || [8.0.0+]
| 4 || [8.0.0+] [[#ReadNextBlock2|ReadNextBlock2]]
|}
|}


Line 237: Line 242:
== ReadNextBlock ==
== ReadNextBlock ==
Takes a type-0x6 output buffer. Returns an output u32 '''Err'''.
Takes a type-0x6 output buffer. Returns an output u32 '''Err'''.
== GetNextBlockSize ==
Unofficial name.
No input. Returns an output u64 '''Size''' and an output u32 '''Err'''.
== ReadNextBlock2 ==
Unofficial name.
Takes a type-0x6 output buffer and two input u64s '''Size''' and '''Offset'''. Returns an output u64 '''OutSize''' and an output u32 '''Err'''.


= nvdbg:d =
= nvdbg:d =
Line 273: Line 288:
| 0xC004001C || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT]]
| 0xC004001C || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT]]
|-
|-
| 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT]]
| 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]
|-
|-
| 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT_ASYNC]]
| 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]]
|-
|-
| 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_REGISTER_EVENT]]
| 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT]]
|-
|-
| 0xC0040020 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_UNREGISTER_EVENT]]
| 0xC0040020 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT]]
|-
|-
| 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENTS]]
| 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH]]
|-
|-
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_GET_MAX_EVENT_FIFO_CHANNEL]]
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]
|}
|}


Line 315: Line 330:
   struct {
   struct {
     __in u32 id;
     __in u32 id;
     __in u32 lock;        // (0==unlock; 1==lock)
     __in u32 lock;        // 0=unlock, 1=lock
   };
   };


Line 352: Line 367:


   struct {
   struct {
     __in char domain_str[0x41];      // "nv"
     __in char name[0x41];      // "nv"
     __in char param_str[0x41];
     __in char key[0x41];
     __out char config_str[0x101];
     __out char value[0x101];
   };
   };


=== NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT ===
=== NVHOST_IOCTL_CTRL_SYNCPT_CLEAR_EVENT_WAIT ===
Clears the wait signal of an event. Exclusive to the Switch.
Clears the wait signal of a syncpt event.


   struct {
   struct {
     __in u32 event_slot;         // ranges from 0x00 to 0x3F
     __in u32 event_slot;       // 0x00 to 0x3F
   };
   };


=== NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT ===
=== NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT ===
Waits on an event. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to (('''syncpt_id''' << 0x10) | 0x10000000).
Waits on a syncpt using events. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to ('''event_slot''' | (('''syncpt_id''' & 0xFFF) << 16) | ('''is_valid''' << 28)).
 
Depending on '''threshold''', an '''event_slot''' may be returned for using with other event ioctls.


   struct {
   struct {
     __in   u32 syncpt_id;
     __in u32 id;
     __in   u32 threshold;
     __in u32 thresh;
     __in   s32 timeout;
     __in s32 timeout;
     __inout u32 value;           // in=event_slot (ignored); out=syncpt_value or event_slot
     __out u32 value;
   };
   };


=== NVHOST_IOCTL_CTRL_SYNCPT_EVENT_WAIT_ASYNC ===
=== NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX ===
Waits on an event (async version). If waiting fails, returns error code 0x0B (BadValue).
Waits on a syncpt using a specific event. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to ('''event_slot''' | ('''syncpt_id''' << 4)).
 
Depending on '''threshold''', an '''event_slot''' may be returned for using with other event ioctls.


   struct {
   struct {
     __in    u32 syncpt_id;
     __in    u32 id;
     __in    u32 threshold;
     __in    u32 thresh;
     __in    u32 timeout;
     __in    s32 timeout;
     __inout u32 value;          // in=event_slot (ignored); out=syncpt_value or event_slot
     __inout u32 value;          // in=event_slot; out=syncpt_value
   };
   };


=== NVHOST_IOCTL_CTRL_SYNCPT_REGISTER_EVENT ===
=== NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT ===
Registers an event. Exclusive to the Switch.  
Allocates a new syncpt event.


   struct {
   struct {
     __in u32 event_slot;        // ranges from 0x00 to 0x3F
     __in u32 event_slot;        // 0x00 to 0x3F
   };
   };


=== NVHOST_IOCTL_CTRL_SYNCPT_UNREGISTER_EVENT ===
=== NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT ===
Unregisters an event. Exclusive to the Switch.  
Frees an existing syncpt event.


   struct {
   struct {
     __in u32 event_slot;        // ranges from 0x00 to 0x3F
     __in u32 event_slot;        // 0x00 to 0x3F
   };
   };


=== NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENTS ===
=== NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH ===
Frees events. Exclusive to the Switch.  
Frees multiple syncpt events.  


   struct {
   struct {
     __in u64 events;             // 64-bit bitfield where each bit represents one event
     __in u64 event_slot_mask;   // 64-bit bitfield where each bit represents one event
   };
   };


=== NVHOST_IOCTL_CTRL_GET_MAX_EVENT_FIFO_CHANNEL ===
=== NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT ===
If event FIFO is enabled, returns the maximum channel number. Exclusive to the Switch.
Returns the syncpt shift value.


   struct {
   struct {
     __out u32 max_channel;       // 0x00 (FIFO disabled) or 0x60 (FIFO enabled)
     __out u32 syncpt_shift;     // 0x00 (FIFO disabled) or 0x60 (FIFO enabled)
   };
   };


Line 499: Line 510:
     __in  u32 handle;
     __in  u32 handle;
     u32      pad;
     u32      pad;
     __out u64 address;
     __out u64 address; // 0 if the handle wasn't yet freed
     __out u32 size;
     __out u32 size;
     __out u32 flags;    // 1=NOT_FREED_YET
     __out u32 flags;    // 1=WAS_UNCACHED (if flags bit 1 was set when NVMAP_IOC_ALLOC was called)
   };
   };


Line 582: Line 593:
! Value || Direction || Size || Description
! Value || Direction || Size || Description
|-
|-
| 0x80040212 || Out || 4 || NVDISP_CTRL_NUM_OUTPUTS
| 0x80040212 || Out || 4 || [[#NVDISP_CTRL_NUM_OUTPUTS]]
|-
|-
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES
| 0xC0140213 || Inout || 20 || NVDISP_CTRL_GET_DISPLAY_PROPERTIES
|-
|-
| 0xC1100214 || Inout || 272 || NVDISP_CTRL_QUERY_EDID
| 0xC2100214</br>([1.0.0-11.0.1] 0xC1100214) || Inout || 528</br>([1.0.0-11.0.1] 272) || NVDISP_CTRL_QUERY_EDID
|-
|-
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
| 0xC0080216</br>([1.0.0-3.0.0] 0xC0040216) || Inout || 8</br>([1.0.0-3.0.0] 4) || NVDISP_CTRL_GET_EXT_HPD_IN_OUT_EVENTS</br>([1.0.0-3.0.0] NVDISP_CTRL_GET_EXT_HPD_IN_EVENT)
Line 598: Line 609:
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND
|-
|-
| 0x80010224 || Out || 1 || [11.0.0+]
| 0x80010224 || Out || 1 || [11.0.0+] NVDISP_CTRL_IS_DISPLAY_OLED
|}
|}
=== NVDISP_CTRL_NUM_OUTPUTS ===
  struct {
    __out u32 num_outputs;
  };


== /dev/nvdisp-disp0, /dev/nvdisp-disp1 ==
== /dev/nvdisp-disp0, /dev/nvdisp-disp1 ==
Line 611: Line 628:
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
|-
|-
| 0x80380204 || Out || 56 || NVDISP_GET_MODE
| 0x80380204 || Out || 56 || [[#NVDISP_GET_MODE]]
|-
|-
| 0x40380205 || Out || 56 || NVDISP_SET_MODE
| 0x40380205 || In || 56 || [[#NVDISP_SET_MODE]]
|-
|-
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
Line 623: Line 640:
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
|-
|-
| 0xC038020A || Inout || 56 || NVDISP_VALIDATE_MODE
| 0xC038020A || Inout || 56 || [[#NVDISP_VALIDATE_MODE]]
|-
|-
| 0x4018020B || In || 24 || NVDISP_SET_CSC
| 0x4018020B || In || 24 || NVDISP_SET_CSC
Line 635: Line 652:
| 0xC004020F || Inout || 4 || NVDISP_DPMS
| 0xC004020F || Inout || 4 || NVDISP_DPMS
|-
|-
| 0x80600210 || Out || 96 || NVDISP_GET_AVI_INFOFRAME
| 0x80600210 || Out || 96 || [[#NVDISP_GET_AVI_INFOFRAME]]
|-
|-
| 0x40600211 || In || 96 || NVDISP_SET_AVI_INFOFRAME
| 0x40600211 || In || 96 || [[#NVDISP_SET_AVI_INFOFRAME]]
|-
|-
| 0xEBFC0215 || Inout || 11260 || NVDISP_GET_MODE_DB
| 0xEBFC0215 || Inout || 11260 || [[#NVDISP_GET_MODE_DB]]
|-
|-
| 0xC003021A || Inout || 3 || NVDISP_PANEL_GET_VENDOR_ID
| 0xC003021A || Inout || 3 || [[#NVDISP_PANEL_GET_VENDOR_ID]]
|-
|-
| 0x803C021B || Out || 60 || NVDISP_GET_MODE2
| 0x803C021B || Out || 60 || [[#NVDISP_GET_MODE2]]
|-
|-
| 0x403C021C || In || 60 || NVDISP_SET_MODE2
| 0x403C021C || In || 60 || [[#NVDISP_SET_MODE2]]
|-
|-
| 0xC03C021D || Inout || 60 || NVDISP_VALIDATE_MODE2
| 0xC03C021D || Inout || 60 || [[#NVDISP_VALIDATE_MODE2]]
|-
|-
| 0xEF20021E || Inout || 12064 || NVDISP_GET_MODE_DB2
| 0xEF20021E || Inout || 12064 || [[#NVDISP_GET_MODE_DB2]]
|-
|-
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
| 0xC004021F || Inout || 4 || NVDISP_GET_WINMASK
Line 655: Line 672:
| 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE]]
| 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE]]
|-
|-
| 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT]]
| 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MAX]]
|-
|-
| 0x40040223 || In || 4 || [11.0.0+]  
| 0x40040223 || In || 4 || [11.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MIN]]
|-
|-
| 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG]]
| 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG]]
Line 664: Line 681:
|}
|}


=== NVDISP_GET_BACKLIGHT_RANGE ===
=== NVDISP_GET_MODE ===
Returns the minimum and maximum values for the intensity of the display's backlight.
Almost identical to Linux driver.


   struct {
   struct {
     __out u32 min;
     __out u32 hActive;
     __out u32 max;
     __out u32 vActive;
    __out u32 hSyncWidth;
    __out u32 vSyncWidth;
    __out u32 hFrontPorch;
    __out u32 vFrontPorch;
    __out u32 hBackPorch;
    __out u32 vBackPorch;
    __out u32 hRefToSync;
    __out u32 vRefToSync;
    __out u32 pclkKHz;
    __out u32 bitsPerPixel;      // Always 0
    __out u32 vmode;            // Always 0
    __out u32 sync;
   };
   };


=== NVDISP_SET_BACKLIGHT ===
=== NVDISP_SET_MODE ===
Sets the value for the intensity of the display's backlight.
Almost identical to Linux driver.


   struct {
   struct {
     __in u32 val;
     __in u32 hActive;
    __in u32 vActive;
    __in u32 hSyncWidth;
    __in u32 vSyncWidth;
    __in u32 hFrontPorch;
    __in u32 vFrontPorch;
    __in u32 hBackPorch;
    __in u32 vBackPorch;
    __in u32 hRefToSync;
    __in u32 vRefToSync;
    __in u32 pclkKHz;
    __in u32 bitsPerPixel;
    __in u32 vmode;
    __in u32 sync;
   };
   };


=== NVDISP_SEND_PANEL_MSG ===
=== NVDISP_VALIDATE_MODE ===
Sends raw data to the display panel over DPAUX.
Almost identical to Linux driver.


   struct {
   struct {
     __in u32 cmd;         // DPAUX AUXCTL command (1=unk, 2=I2CWR, 4=MOTWR, 7=AUXWR)
     __inout u32 hActive;
     __in u32 addr;         // DPAUX AUXADDR
     __inout u32 vActive;
     __in u32 size;         // message size
     __inout u32 hSyncWidth;
     __in u32 msg[4];       // raw AUXDATA message
     __inout u32 vSyncWidth;
    __inout u32 hFrontPorch;
    __inout u32 vFrontPorch;
    __inout u32 hBackPorch;
    __inout u32 vBackPorch;
    __inout u32 hRefToSync;
    __inout u32 vRefToSync;
    __inout u32 pclkKHz;
    __inout u32 bitsPerPixel;
    __inout u32 vmode;
    __inout u32 sync;
   };
   };


=== NVDISP_GET_PANEL_DATA ===
=== NVDISP_GET_AVI_INFOFRAME ===
Receives raw data from the display panel over DPAUX.
Unpacked standard AVI infoframe struct (HDMI v1.4b/2.0)


   struct {
   struct {
     __in u32 cmd;         // DPAUX AUXCTL command (3=I2CRD, 5=MOTRD, 6=AUXRD)
     __out u32 csum;
     __in u32 addr;         // DPAUX AUXADDR
    __out u32 scan;
     __in u32 size;         // message size
    __out u32 bar_valid;
     __out u32 msg[4];     // raw AUXDATA message
    __out u32 act_fmt_valid;
    __out u32 rgb_ycc;
    __out u32 act_format;
    __out u32 aspect_ratio;
    __out u32 colorimetry;
    __out u32 scaling;
    __out u32 rgb_quant;
    __out u32 ext_colorimetry;
    __out u32 it_content;
    __out u32 video_format;
    __out u32 pix_rep;
    __out u32 it_content_type;
    __out u32 ycc_quant;
    __out u32 top_bar_end_line_lsb;
    __out u32 top_bar_end_line_msb;
    __out u32 bot_bar_start_line_lsb;
    __out u32 bot_bar_start_line_msb;
    __out u32 left_bar_end_pixel_lsb;
    __out u32 left_bar_end_pixel_msb;
    __out u32 right_bar_start_pixel_lsb;
    __out u32 right_bar_start_pixel_msb;
  };
 
=== NVDISP_SET_AVI_INFOFRAME ===
Unpacked standard AVI infoframe struct (HDMI v1.4b/2.0)
 
  struct {
    __in u32 csum;
    __in u32 scan;
    __in u32 bar_valid;
    __in u32 act_fmt_valid;
    __in u32 rgb_ycc;
    __in u32 act_format;
    __in u32 aspect_ratio;
    __in u32 colorimetry;
    __in u32 scaling;
    __in u32 rgb_quant;
    __in u32 ext_colorimetry;
    __in u32 it_content;
    __in u32 video_format;
     __in u32 pix_rep;
    __in u32 it_content_type;
    __in u32 ycc_quant;
    __in u32 top_bar_end_line_lsb;
    __in u32 top_bar_end_line_msb;
    __in u32 bot_bar_start_line_lsb;
    __in u32 bot_bar_start_line_msb;
    __in u32 left_bar_end_pixel_lsb;
    __in u32 left_bar_end_pixel_msb;
     __in u32 right_bar_start_pixel_lsb;
     __in u32 right_bar_start_pixel_msb;
   };
   };


== /dev/nvcec-ctrl ==
=== NVDISP_GET_MODE_DB ===
{| class="wikitable" border="1"
Almost identical to Linux driver.
! Value || Direction || Size || Description
|-
| 0x40010301 || In || 1 || NVCEC_CTRL_ENABLE
|-
| 0x804C0302 || Out || 76 || NVCEC_CTRL_GET_PADDR
|-
| 0x40040303 || In || 4 || NVCEC_CTRL_SET_LADDR
|-
| 0xC04C0304 || Inout || 76 || NVCEC_CTRL_WRITE
|-
| 0xC04C0305 || Inout || 76 || NVCEC_CTRL_READ
|-
| 0x804C0306 || Out || 76 || NVCEC_CTRL_GET_CONNECTION_STATUS
|-
| 0x804C0307 || Out || 76 || NVCEC_CTRL_GET_WRITE_STATUS
|}


== /dev/nvhdcp_up-ctrl ==
  struct mode {
{| class="wikitable" border="1"
    u32 hActive;
! Value || Direction || Size || Description
    u32 vActive;
|-
    u32 hSyncWidth;
| 0xC4880401 || Inout || 1160 || NVHDCP_READ_STATUS
    u32 vSyncWidth;
|-
    u32 hFrontPorch;
| 0xC4880402 || Inout || 1160 || NVHDCP_READ_M
    u32 vFrontPorch;
|-
    u32 hBackPorch;
| 0x40010403 || In || 1 || NVHDCP_ENABLE
    u32 vBackPorch;
|-
    u32 hRefToSync;
| 0xC0080404 || Inout || 8 || NVHDCP_CTRL_STATE_TRANSIT_EVENT_DATA
    u32 vRefToSync;
|-
    u32 pclkKHz;
| 0xC0010405 || Inout || 1 || NVHDCP_CTRL_STATE_CB
    u32 bitsPerPixel;
|}
    u32 vmode;
    u32 sync;
  };
  struct {
    __out struct mode modes[201];
    __out u32 num_modes;
  };
 
=== NVDISP_PANEL_GET_VENDOR_ID ===
 
Returns display panel's informations.
 
  struct {
    __out u8 vendor; //0x10 - JDI, 0x20 - InnoLux, 0x30 - AUO, 0x40 - Sharp, 0x50 - Samsung
    __out u8 model;
    __out u8 board; //0xF - 6.2", 0x10 - 5.5", 0x20 - 7.0". JDI panels have nonstandard values
  };
 
=== NVDISP_GET_MODE2 ===


== /dev/nvdcutil-disp0, /dev/nvdcutil-disp1 ==
  struct {
{| class="wikitable" border="1"
    __out u32 unk0;              //Always 0
! Value || Direction || Size || Description
    __out u32 hActive;
|-
    __out u32 vActive;
| 0x40010501 || In || 1 || NVDCUTIL_ENABLE_CRC
    __out u32 hSyncWidth;
|-
    __out u32 vSyncWidth;
| 0x40010502 || In || 1 || NVDCUTIL_VIRTUAL_EDID_ENABLE
    __out u32 hFrontPorch;
|-
    __out u32 vFrontPorch;
| 0x42040503 || In || 1056 || NVDCUTIL_VIRTUAL_EDID_SET_DATA
    __out u32 hBackPorch;
|-
    __out u32 vBackPorch;
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
    __out u32 pclkKHz;
|-
    __out u32 bitsPerPixel;      // Always 0
| 0x40010505 || In || 1 || NVDCUTIL_BEGIN_TELEMETRY_TEST
    __out u32 vmode;            // Always 0
|-
    __out u32 sync;
| 0x400C0506 || In || 12 || NVDCUTIL_DSI_PACKET_TEST_SHORT_WRITE
    __out u32 unk1;
|-
    __out u32 reserved;
| 0x40F80507 || In || 248 || NVDCUTIL_DSI_PACKET_TEST_LONG_WRITE
  };
|-
 
| 0xC0F40508 || Inout || 244 || NVDCUTIL_DSI_PACKET_TEST_READ
=== NVDISP_SET_MODE2 ===
|-
 
| 0x40010509 || In || 1 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_EN
  struct {
|-
    __in u32 unk0;
| 0xC020050A || Inout || 32 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_SETTINGS
    __in u32 hActive;
|-
    __in u32 vActive;
| 0x8070050B || Out || 112 || [11.0.0+] NVDCUTIL_DP_CONF_READ
    __in u32 hSyncWidth;
|}
    __in u32 vSyncWidth;
    __in u32 hFrontPorch;
    __in u32 vFrontPorch;
    __in u32 hBackPorch;
    __in u32 vBackPorch;
    __in u32 pclkKHz;
    __in u32 bitsPerPixel;
    __in u32 vmode;
    __in u32 sync;
    __in u32 unk1;
    __in u32 reserved;
  };
 
=== NVDISP_VALIDATE_MODE2 ===


== /dev/nvsched-ctrl ==
  struct {
This is a customized scheduler device.
    __inout u32 unk0;
    __inout u32 hActive;
    __inout u32 vActive;
    __inout u32 hSyncWidth;
    __inout u32 vSyncWidth;
    __inout u32 hFrontPorch;
    __inout u32 vFrontPorch;
    __inout u32 hBackPorch;
    __inout u32 vBackPorch;
    __inout u32 pclkKHz;
    __inout u32 bitsPerPixel;
    __inout u32 vmode;
    __inout u32 sync;
    __inout u32 unk1;
    __inout u32 reserved;
  };


The way this device is exposed and configured is exclusive to the Switch, since other sources don't have an actual interface for the scheduler.
=== NVDISP_GET_MODE_DB2 ===


{| class="wikitable" border="1"
  struct mode2 {
! Value || Direction || Size || Description
    u32 unk0;
|-
    u32 hActive;
| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE]]
    u32 vActive;
|-
    u32 hSyncWidth;
| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE]]
    u32 vSyncWidth;
|-
    u32 hFrontPorch;
| 0x40180603 || In || 24 || [[#NVSCHED_CTRL_ADD_APPLICATION]]
    u32 vFrontPorch;
|-
    u32 hBackPorch;
| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION]]
    u32 vBackPorch;
|-
    u32 pclkKHz;
| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION]]
    u32 bitsPerPixel;
|-
    u32 vmode;
| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID]]
    u32 sync;
|-
    u32 unk1;
| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST]]
    u32 reserved;
|-
  };
| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST]]
|-
  struct {
| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST]]
    __out struct mode2 modes[201];
|-
    __out u32 num_modes;
| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST]]
  };
|-
 
| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST]]
=== NVDISP_GET_BACKLIGHT_RANGE ===
|-
Returns the minimum and maximum values for the intensity of the display's backlight.
| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]]
 
|-
  struct {
| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]
    __out u32 min;
|-
    __out u32 max;
| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]
  };
|-
 
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]
=== NVDISP_SET_BACKLIGHT_RANGE_MAX ===
|-
Sets the maximum value for the intensity of the display's backlight.
| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT
 
|-
  struct {
| 0x40100611 || In || 16 || NVSCHED_CTRL_SET_RUNLIST_MAX_DEBT
    __in u32 max;
|-
  };
| 0x40010612 || In || 1 || NVSCHED_CTRL_OVERRUN_EVENTS_ENABLE
|}


=== NVSCHED_CTRL_ENABLE ===
=== NVDISP_SET_BACKLIGHT_RANGE_MIN ===
Enables the scheduler.
Sets the minimum value for the intensity of the display's backlight.


=== NVSCHED_CTRL_DISABLE ===
  struct {
Disables the scheduler.
    __in u32 min;
  };


=== NVSCHED_CTRL_ADD_APPLICATION ===
=== NVDISP_SEND_PANEL_MSG ===
Adds a new application to the scheduler.
Sends raw data to the display panel over DPAUX.


   struct {
   struct {
     __in u64 application_id;
     __in u32 cmd;         // DPAUX AUXCTL command (1=unk, 2=I2CWR, 4=MOTWR, 7=AUXWR)
     __in u64 priority;
     __in u32 addr;         // DPAUX AUXADDR
     __in u64 timeslice;
     __in u32 size;         // message size
    __in u32 msg[4];      // raw AUXDATA message
   };
   };


=== NVSCHED_CTRL_UPDATE_APPLICATION ===
=== NVDISP_GET_PANEL_DATA ===
Updates the application parameters in the scheduler.
Receives raw data from the display panel over DPAUX.


   struct {
   struct {
     __in u64 application_id;
     __in u32 cmd;         // DPAUX AUXCTL command (3=I2CRD, 5=MOTRD, 6=AUXRD)
     __in u64 priority;
     __in u32 addr;         // DPAUX AUXADDR
     __in u64 timeslice;
     __in u32 size;         // message size
    __out u32 msg[4];      // raw AUXDATA message
   };
   };


=== NVSCHED_CTRL_REMOVE_APPLICATION ===
== /dev/nvcec-ctrl ==
Removes the application from the scheduler.
{| class="wikitable" border="1"
 
! Value || Direction || Size || Description
  struct {
|-
    __in u64 application_id;
| 0x40010301 || In || 1 || NVCEC_CTRL_ENABLE
  };
|-
 
| 0x804C0302 || Out || 76 || NVCEC_CTRL_GET_PADDR
=== NVSCHED_CTRL_GET_ID ===
|-
Returns the ID of the last scheduled object.
| 0x40040303 || In || 4 || NVCEC_CTRL_SET_LADDR
|-
| 0xC04C0304 || Inout || 76 || NVCEC_CTRL_WRITE
|-
| 0xC04C0305 || Inout || 76 || NVCEC_CTRL_READ
|-
| 0x804C0306 || Out || 76 || NVCEC_CTRL_GET_CONNECTION_STATUS
|-
| 0x804C0307 || Out || 76 || NVCEC_CTRL_GET_WRITE_STATUS
|}


  struct {
== /dev/nvhdcp_up-ctrl ==
    __out u64 id;
{| class="wikitable" border="1"
  };
! Value || Direction || Size || Description
|-
| 0xC4880401 || Inout || 1160 || NVHDCP_READ_STATUS
|-
| 0xC4880402 || Inout || 1160 || NVHDCP_READ_M
|-
| 0x40010403 || In || 1 || NVHDCP_ENABLE
|-
| 0xC0080404 || Inout || 8 || NVHDCP_CTRL_STATE_TRANSIT_EVENT_DATA
|-
| 0xC0010405 || Inout || 1 || NVHDCP_CTRL_STATE_CB
|}


=== NVSCHED_CTRL_ADD_RUNLIST ===
== /dev/nvdcutil-disp0, /dev/nvdcutil-disp1 ==
Creates a new runlist and returns it's ID.
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0x40010501 || In || 1 || NVDCUTIL_ENABLE_CRC
|-
| 0x40010502 || In || 1 || [[#NVDCUTIL_VIRTUAL_EDID_ENABLE]]
|-
| 0x42040503 || In || 516 || [[#NVDCUTIL_VIRTUAL_EDID_SET_DATA]]
|-
| 0x803C0504 || Out || 60 || NVDCUTIL_GET_MODE
|-
| 0x40010505 || In || 1 || NVDCUTIL_BEGIN_TELEMETRY_TEST
|-
| 0x400C0506 || In || 12 || NVDCUTIL_DSI_PACKET_TEST_SHORT_WRITE
|-
| 0x40F80507 || In || 248 || NVDCUTIL_DSI_PACKET_TEST_LONG_WRITE
|-
| 0xC0F40508 || Inout || 244 || NVDCUTIL_DSI_PACKET_TEST_READ
|-
| 0x40010509 || In || 1 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_EN
|-
| 0xC020050A || Inout || 32 || [10.0.0+] NVDCUTIL_DP_ELECTRIC_TEST_SETTINGS
|-
| 0x8070050B || Out || 112 || [11.0.0+] NVDCUTIL_DP_CONF_READ
|}
 
=== NVDCUTIL_VIRTUAL_EDID_ENABLE ===


   struct {
   struct {
     __out u64 runlist_id;
     __in u8 enable;
   };
   };


=== NVSCHED_CTRL_UPDATE_RUNLIST ===
=== NVDCUTIL_VIRTUAL_EDID_SET_DATA ===
Updates the runlist parameters in the scheduler.


   struct {
   struct {
     __in u64 runlist_id;
     __in u8 edid[512];
     __in u64 priority;
     __in u32 edid_size;
    __in u64 timeslice;
   };
   };


=== NVSCHED_CTRL_LINK_RUNLIST ===
== /dev/nvsched-ctrl ==
Links a runlist to a given application in the scheduler.
This is a customized scheduler device.


  struct {
The way this device is exposed and configured is exclusive to the Switch, since other sources don't have an actual interface for the scheduler.
    __in u64 runlist_id;
    __in u64 application_id;
  };


=== NVSCHED_CTRL_UNLINK_RUNLIST ===
{| class="wikitable" border="1"
Unlinks a runlist from a given application in the scheduler.
! Value || Direction || Size || Description
 
|-
  struct {
| 0x00000601 || - || 0 || [[#NVSCHED_CTRL_ENABLE]]
    __in u64 runlist_id;
|-
    __in u64 application_id;
| 0x00000602 || - || 0 || [[#NVSCHED_CTRL_DISABLE]]
  };
|-
 
| 0x40180603 || In || 24 || [[#NVSCHED_CTRL_ADD_APPLICATION]]
=== NVSCHED_CTRL_REMOVE_RUNLIST ===
|-
Removes the runlist from the scheduler.
| 0x40180604 || In || 24 || [[#NVSCHED_CTRL_UPDATE_APPLICATION]]
|-
| 0x40080605 || In || 8 || [[#NVSCHED_CTRL_REMOVE_APPLICATION]]
|-
| 0x80080606 || Out || 8 || [[#NVSCHED_CTRL_GET_ID]]
|-
| 0x80080607 || Out || 8 || [[#NVSCHED_CTRL_ADD_RUNLIST]]
|-
| 0x40180608 || In || 24 || [[#NVSCHED_CTRL_UPDATE_RUNLIST]]
|-
| 0x40100609 || In || 16 || [[#NVSCHED_CTRL_LINK_RUNLIST]]
|-
| 0x4010060A || In || 16 || [[#NVSCHED_CTRL_UNLINK_RUNLIST]]
|-
| 0x4008060B || In || 8 || [[#NVSCHED_CTRL_REMOVE_RUNLIST]]
|-
| 0x8001060C || Out || 1 || [[#NVSCHED_CTRL_HAS_OVERRUN_EVENT]]
|-
| 0x8020060D</br>([1.0.0-3.0.0] 0x8010060D) || Out || 32</br>([1.0.0-3.0.0] 16) || [[#NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT]]
|-
| 0x400C060E || In || 12 || [[#NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE]]
|-
| 0x4008060F || In || 8 || [[#NVSCHED_CTRL_DETACH_APPLICATION]]
|-
| 0x40100610 || In || 16 || NVSCHED_CTRL_SET_APPLICATION_MAX_DEBT
|-
| 0x40100611 || In || 16 || NVSCHED_CTRL_SET_RUNLIST_MAX_DEBT
|-
| 0x40010612 || In || 1 || NVSCHED_CTRL_OVERRUN_EVENTS_ENABLE
|}
 
=== NVSCHED_CTRL_ENABLE ===
Enables the scheduler.
 
=== NVSCHED_CTRL_DISABLE ===
Disables the scheduler.
 
=== NVSCHED_CTRL_ADD_APPLICATION ===
Adds a new application to the scheduler.


   struct {
   struct {
     __in u64 runlist_id;
     __in u64 application_id;
    __in u64 priority;
    __in u64 timeslice;
   };
   };


=== NVSCHED_CTRL_HAS_OVERRUN_EVENT ===
=== NVSCHED_CTRL_UPDATE_APPLICATION ===
Returns a boolean to tell if the scheduler has an overrun event or not.
Updates the application parameters in the scheduler.


   struct {
   struct {
     __out u8 has_overrun;
     __in u64 application_id;
    __in u64 priority;
    __in u64 timeslice;
   };
   };


=== NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT ===
=== NVSCHED_CTRL_REMOVE_APPLICATION ===
Returns the overrun event's data from the scheduler.
Removes the application from the scheduler.


   struct {
   struct {
     __out u64 runlist_id;
     __in u64 application_id;
    __out u64 debt;
    __out u64 unk0;          // 3.0.0+ only
    __out u64 unk1;          // 3.0.0+ only
   };
   };


=== NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE ===
=== NVSCHED_CTRL_GET_ID ===
Installs a fence swap event?
Returns the ID of the last scheduled object.


   struct {
   struct {
     __in u32 fence_id;
     __out u64 id;
    __in u32 fence_thresh;
    __in u32 swap_interval;
   };
   };


=== NVSCHED_CTRL_DETACH_APPLICATION ===
=== NVSCHED_CTRL_ADD_RUNLIST ===
Places the given application in detached state.
Creates a new runlist and returns it's ID.


   struct {
   struct {
     __in u64 application_id;
     __out u64 runlist_id;
   };
   };


== /dev/nverpt-ctrl ==
=== NVSCHED_CTRL_UPDATE_RUNLIST ===
Added in firmware version 3.0.0.
Updates the runlist parameters in the scheduler.


{| class="wikitable" border="1"
  struct {
! Value || Direction || Size || Description
    __in u64 runlist_id;
|-
    __in u64 priority;
| 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA]]
    __in u64 timeslice;
|-
  };
| 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]]
|}


=== NVERPT_TELEMETRY_SUBMIT_DATA ===
=== NVSCHED_CTRL_LINK_RUNLIST ===
Sends test data for creating a new [[Error_Report_services|Error Report]].
Links a runlist to a given application in the scheduler.


   struct {
   struct {
     __in u64 TestU64;
     __in u64 runlist_id;
    __in u32 TestU32;
     __in u64 application_id;
    __in u8  padding0[4];
    __in s64 TestI64;
    __in s32 TestI32;
    __in u8  TestString[32];
    __in u8  TestU8Array[8];
    __in u32 TestU8Array_size;
    __in u32 TestU32Array[8];
    __in u32 TestU32Array_size;
     __in u64 TestU64Array[8];
    __in u32 TestU64Array_size;
    __in s32 TestI32Array[8];
    __in u32 TestI32Array_size;
    __in s64 TestI64Array[8];
    __in u32 TestI64Array_size;
    __in u16 TestU16;
    __in u8  TestU8;
    __in s16 TestI16;
    __in s8  TestI8;
    __in u8  padding1[5];
   };
   };


=== NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA ===
=== NVSCHED_CTRL_UNLINK_RUNLIST ===
Sends display data for creating a new [[Error_Report_services|Error Report]].
Unlinks a runlist from a given application in the scheduler.


   struct {
   struct {
     __in u32 CodecType;
     __in u64 runlist_id;
     __in u32 DecodeBuffers;
     __in u64 application_id;
    __in u32 FrameWidth;
    __in u32 FrameHeight;
    __in u8  ColorPrimaries;
    __in u8  TransferCharacteristics;
    __in u8  MatrixCoefficients;
    __in u8  padding;
    __in u32 DisplayWidth;
    __in u32 DisplayHeight;
    __in u32 DARWidth;
    __in u32 DARHeight;
    __in u32 ColorFormat;
    __in u32 ColorSpace[8];
    __in u32 ColorSpace_size;
    __in u32 SurfaceLayout[8];
    __in u32 SurfaceLayout_size;
    __in u8  ErrorString[64];      // must be "Error detected = 0x1000000"
    __in u32 VideoDecState;
    __in u8  VideoLog[3712];
    __in u32 VideoLog_size;
   };
   };


== /dev/nvhost-as-gpu ==
=== NVSCHED_CTRL_REMOVE_RUNLIST ===
Each fd opened to this device creates an address space. An address space is then later bound with a channel.
Removes the runlist from the scheduler.
 
  struct {
    __in u64 runlist_id;
  };


Once a nvgpu channel has been bound to an address space it cannot be unbound. There is no support for allowing an nvgpu channel to change from one address space to another (or from one to none).
=== NVSCHED_CTRL_HAS_OVERRUN_EVENT ===
                                                                                                                             
Returns a boolean to tell if the scheduler has an overrun event or not.
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL]]
|-
| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE]]
|-
| 0xC0104103 || Inout || 16 || [[#NVGPU_AS_IOCTL_FREE_SPACE]]
|-
| 0xC0184104 || Inout || 24 || [[#NVGPU_AS_IOCTL_MAP_BUFFER]]
|-
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
|-
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
|-
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]
|-
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS]]
|-
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MODIFY]]
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
|}
 
=== NVGPU_AS_IOCTL_BIND_CHANNEL ===
Identical to Linux driver.


   struct {
   struct {
     __in u32 channel_fd;
     __out u8 has_overrun;
   };
   };


=== NVGPU_AS_IOCTL_ALLOC_SPACE ===
=== NVSCHED_CTRL_GET_NEXT_OVERRUN_EVENT ===
Reserves pages in the device address space.
Returns the overrun event's data from the scheduler.


   struct {
   struct {
     __in u32 pages;
     __out u64 runlist_id;
     __in u32 page_size;
     __out u64 debt;
     __in u32 flags;
     __out u64 unk0;           // 3.0.0+ only
    u32      padding;
     __out u64 unk1;           // 3.0.0+ only
     union {
      __out u64 offset;
      __in  u64 align;
    };
   };
   };


=== NVGPU_AS_IOCTL_FREE_SPACE ===
=== NVSCHED_CTRL_PUT_CONDUCTOR_FLIP_FENCE ===
Frees pages from the device address space.
Installs a fence swap event?


   struct {
   struct {
     __in u64 offset;
     __in u32 fence_id;
     __in u32 pages;
     __in u32 fence_value;
     __in u32 page_size;
     __in u32 swap_interval;
   };
   };


=== NVGPU_AS_IOCTL_MAP_BUFFER ===
=== NVSCHED_CTRL_DETACH_APPLICATION ===
Maps a memory region in the device address space. Identical to Linux driver pretty much.
Places the given application in detached state.
 
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.


   struct {
   struct {
     __in   u32 flags;        // bit0: fixed_offset, bit2: cacheable
     __in u64 application_id;
    u32        reserved;
   };
    __in    u32 dmabuf_fd;    // nvmap handle
    __inout u32 page_size;    // 0 means don't care
    union {
      __out u64 offset;
      __in  u64 align;
    };
   };


=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
== /dev/nverpt-ctrl ==
Maps a memory region in the device address space with extra params.
Added in firmware version 3.0.0.


Unaligned size will cause a [[#Panic]].
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
| 0xC1280701 || Inout || 296 || [[#NVERPT_TELEMETRY_SUBMIT_DATA]]
|-
| 0xCF580702 || Inout || 3928 || [[#NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA]]
|}


On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
=== NVERPT_TELEMETRY_SUBMIT_DATA ===
Sends test data for creating a new [[Error_Report_services|Error Report]].


   struct {
   struct {
     __in     u32 flags;         // bit0: fixed_offset, bit2: cacheable
     __in u64 TestU64;
     __in     u32 kind;           // -1 is default
    __in u32 TestU32;
     __in     u32 dmabuf_fd;     // nvmap handle
    __in u8  padding0[4];
     __inout  u32 page_size;     // 0 means don't care
    __in s64 TestI64;
     __in     u64 buffer_offset;
    __in s32 TestI32;
     __in     u64 mapping_size;
    __in u8  TestString[32];
     __inout  u64 offset;
    __in u8  TestU8Array[8];
  };
     __in u32 TestU8Array_size;
 
     __in u32 TestU32Array[8];
=== NVGPU_AS_IOCTL_UNMAP_BUFFER ===
     __in u32 TestU32Array_size;
Unmaps a memory region from the device address space.
     __in u64 TestU64Array[8];
 
     __in u32 TestU64Array_size;
  struct {
     __in s32 TestI32Array[8];
     __in u64 offset;
    __in u32 TestI32Array_size;
    __in s64 TestI64Array[8];
    __in u32 TestI64Array_size;
    __in u16 TestU16;
    __in u8  TestU8;
    __in s16 TestI16;
    __in s8 TestI8;
     __in u8  padding1[5];
   };
   };


=== NVGPU_AS_IOCTL_ALLOC_AS ===
=== NVERPT_TELEMETRY_SUBMIT_DISPLAY_DATA ===
Nintendo's custom implementation for allocating an address space.
Sends display data for creating a new [[Error_Report_services|Error Report]].


   struct {
   struct {
     __in u32 big_page_size;   // depends on GPU's available_big_page_sizes; 0=default
     __in u32 CodecType;
     __in s32 as_fd;           // ignored; passes 0
    __in u32 DecodeBuffers;
     __in u64 reserved;       // ignored; passes 0
    __in u32 FrameWidth;
    __in u32 FrameHeight;
    __in u8  ColorPrimaries;
    __in u8  TransferCharacteristics;
    __in u8  MatrixCoefficients;
    __in u8  padding;
    __in u32 DisplayWidth;
    __in u32 DisplayHeight;
    __in u32 DARWidth;
    __in u32 DARHeight;
    __in u32 ColorFormat;
    __in u32 ColorSpace[8];
    __in u32 ColorSpace_size;
    __in u32 SurfaceLayout[8];
    __in u32 SurfaceLayout_size;
     __in u8  ErrorString[64];       // must be "Error detected = 0x1000000"
    __in u32 VideoDecState;
     __in u8  VideoLog[3712];
    __in u32 VideoLog_size;
   };
   };


=== NVGPU_AS_IOCTL_GET_VA_REGIONS ===
== /dev/nvhost-as-gpu ==
Nintendo's custom implementation to get rid of pointer in struct.
Each fd opened to this device creates an address space. An address space is then later bound with a channel.


   struct va_region {
Once a nvgpu channel has been bound to an address space it cannot be unbound. There is no support for allowing an nvgpu channel to change from one address space to another (or from one to none).
     u64 offset;
                                                                                                                             
    u32 page_size;
{| class="wikitable" border="1"
    u32 reserved;
! Value || Direction || Size || Description
    u64 pages;
|-
| 0x40044101 || In || 4 || [[#NVGPU_AS_IOCTL_BIND_CHANNEL]]
|-
| 0xC0184102 || Inout || 24 || [[#NVGPU_AS_IOCTL_ALLOC_SPACE]]
|-
| 0xC0104103 || Inout || 16 || [[#NVGPU_AS_IOCTL_FREE_SPACE]]
|-
| 0xC0184104 || Inout || 24 || [[#NVGPU_AS_IOCTL_MAP_BUFFER]]
|-
| 0xC0084105 || Inout || 8 || [[#NVGPU_AS_IOCTL_UNMAP_BUFFER]]
|-
| 0xC0284106 || Inout || 40 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX]]
|-
| 0x40104107 || In || 16 || [[#NVGPU_AS_IOCTL_ALLOC_AS]]
|-
| 0xC0404108 || Inout || 64 || [[#NVGPU_AS_IOCTL_GET_VA_REGIONS]]
|-
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
|-
| 0x8010410B || Out || 16 || [S2]
|-
| 0xC020410C || Inout || 32 || [S2]
|-
| 0xC???410D || Inout || Variable || [S2]
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
|}
 
=== NVGPU_AS_IOCTL_BIND_CHANNEL ===
Identical to Linux driver.
 
   struct {
     __in u32 channel_fd;
   };
   };
 
 
=== NVGPU_AS_IOCTL_ALLOC_SPACE ===
Reserves pages in the device address space.
 
   struct {
   struct {
     u64          buf_addr;   // (contained output user ptr on linux, ignored)
     __in u32 pages;
     __inout u32   buf_size;   // forced to 2*sizeof(struct va_region)
    __in u32 page_size;
     u32           reserved;
     __in u32 flags;
     __out struct va_region regions[2];
     u32     padding;
     union {
      __out u64 offset;
      __in u64 align;
    };
   };
   };


=== NVGPU_AS_IOCTL_ALLOC_AS_EX ===
=== NVGPU_AS_IOCTL_FREE_SPACE ===
Nintendo's custom implementation for allocating an address space with extra params.
Frees pages from the device address space.


   struct {
   struct {
     __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
     __in u64 offset;
    __in s32 as_fd;           // ignored; passes 0
     __in u32 pages;
     __in u32 flags;           // passes 0
     __in u32 page_size;
     __in u32 reserved;        // ignored; passes 0
    __in u64 va_range_start;
    __in u64 va_range_end;
    __in u64 va_range_split;
   };
   };


=== NVGPU_AS_IOCTL_MODIFY ===
=== NVGPU_AS_IOCTL_MAP_BUFFER ===
Modifies a memory region in the device address space.
Maps a memory region in the device address space.


     struct {
Unaligned size will cause a [[#Panic]].
 
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
 
  struct {
     __in    u32 flags;        // bit0: fixed_offset, bit2: cacheable
    u32        reserved0;
    __in    u32 mem_id;      // nvmap handle
    u32        reserved1;
    union {
      __out u64 offset;
      __in  u64 align;
    };
  };
 
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX ===
Maps a memory region in the device address space with extra params.
 
Unaligned size will cause a [[#Panic]].
 
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
 
  struct {
     __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
     __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
     __in      u32 kind;          // -1 is default
     __inout  u32 kind;          // -1 is default
     __in      u32 dmabuf_fd;     // nvmap handle
     __in      u32 mem_id;         // nvmap handle
     __inout  u32 page_size;     // 0 means don't care
     u32           reserved;
     __in      u64 buffer_offset;
     __in      u64 buffer_offset;
     __in      u64 mapping_size;
     __in      u64 mapping_size;
     __inout   u64 offset;
     union {
    __in     u64 unk0;
      __out   u64 offset;
    __in      u32 unk1;
      __in   u64 align;
     u32          reserved;
     };
   };
   };


=== NVGPU_AS_IOCTL_REMAP ===
=== NVGPU_AS_IOCTL_UNMAP_BUFFER ===
Nintendo's custom implementation of address space remapping for sparse pages.
Unmaps a memory region from the device address space.


  struct remap_op {
struct {
     __in u16 flags;                   // bit2: cacheable
     __in u64 offset;
    __in u16 kind;          
  };
     __in u32 mem_handle;
 
    __in u32 mem_offset_in_big_pages;
=== NVGPU_AS_IOCTL_ALLOC_AS ===
     __in u32 virt_offset_in_big_pages;   // (alloc_space_offset >> 0x10)
Nintendo's custom implementation for allocating an address space.
     __in u32 num_pages;               // alloc_space_pages
 
  struct {
     __in u32 big_page_size;   // depends on GPU's available_big_page_sizes; 0=default
     __in s32 as_fd;           // ignored; passes 0
     __in u64 reserved;       // ignored; passes 0
   };
   };
struct {
    __in struct remap_op entries[];
};


== /dev/nvhost-dbg-gpu ==
=== NVGPU_AS_IOCTL_GET_VA_REGIONS ===
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.
Nintendo's custom implementation to get rid of pointer in struct.
 
Uses [[#Ioctl3|Ioctl3]].


{| class="wikitable" border="1"
  struct va_region {
! Value || Direction || Size || Description
    u64 offset;
|-
    u32 page_size;
| 0x40084401 || In || 8 || NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL
    u32 reserved;
|-
    u64 pages;
| 0xC0??4402 || Inout || Variable || NVGPU_DBG_GPU_IOCTL_REG_OPS
  };
|-
 
| 0x40084403 || In || 8 || NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL
  struct {
|-
    u64          buf_addr;    // (contained output user ptr on linux, ignored)
| 0x40044404 || In || 4 || NVGPU_DBG_GPU_IOCTL_POWERGATE
    __inout u32  buf_size;    // forced to 2*sizeof(struct va_region)
|-
    u32          reserved;
| 0x40044405 || In || 4 || NVGPU_DBG_GPU_IOCTL_SMPC_CTXSW_MODE
    __out struct  va_region regions[2];
|-
  };
| 0x40044406 || In || 4 || NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_ALL_SMS
 
|-
=== NVGPU_AS_IOCTL_ALLOC_AS_EX ===
| 0xC0184407 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_PERFBUF_MAP
Nintendo's custom implementation for allocating an address space with extra params.
|-
 
| 0x40084408 || In || 8 || NVGPU_DBG_GPU_IOCTL_PERFBUF_UNMAP
  struct {
|-
    __in u32 big_page_size;  // depends on GPU's available_big_page_sizes; 0=default
| 0x40084409 || In || 8 || NVGPU_DBG_GPU_IOCTL_PC_SAMPLING
    __in s32 as_fd;          // ignored; passes 0
|-
    __in u32 flags;          // passes 0
| 0x4008440A || In || 8 || NVGPU_DBG_GPU_IOCTL_TIMEOUT
    __in u32 reserved;        // ignored; passes 0
|-
    __in u64 va_range_start;
| 0x8008440B || Out || 8 || NVGPU_DBG_GPU_IOCTL_GET_TIMEOUT
    __in u64 va_range_end;
|-
    __in u64 va_range_split;
| 0x8004440C || Out || 4 || NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT_SIZE
  };
|-
 
| 0x0000440D || None || 0 || [[#NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT]]
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX2 ===
|-
Maps a memory region in the device address space with extra params.
| 0xC018440E || Inout || 24 || NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
 
|-
Unaligned size will cause a [[#Panic]].
| 0xC018440F || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PDES
 
|-
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
| 0xC0104410 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES]]
 
|-
  struct {
| 0xC0184411 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PTES
    __in      u32 flags;          // bit0: fixed_offset, bit2: cacheable
|-
    __inout  u32 kind;          // -1 is default
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
    __in      u32 mem_id;        // nvmap handle
|-
    u32          reserved0;
| 0xC0684413 || Inout || 104 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
    __in      u64 buffer_offset;
    __in      u64 mapping_size;
    union {
      __out  u64 offset;
      __in    u64 align;
    };
    __in      u64 vma_addr;
    __in      u32 pages;
    u32          reserved1;
  };
 
=== NVGPU_AS_IOCTL_REMAP ===
Nintendo's custom implementation of address space remapping for sparse pages.
 
  struct remap_op {
    __in u16 flags;                      // bit2: cacheable
    __in u16 kind;         
    __in u32 mem_handle;
    __in u32 mem_offset_in_pages;
    __in u32 virt_offset_in_pages;      // (alloc_space_offset >> 0x10)
    __in u32 num_pages;                  // alloc_space_pages
  };
struct {
    __in struct remap_op entries[];
};
 
== /dev/nvhost-dbg-gpu ==
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.
 
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
|-
| 0xC0184414 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
| 0x40084401 || In || 8 || NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL
|-
|-
| 0xC0184415 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
| 0xC0??4402 || Inout || Variable || NVGPU_DBG_GPU_IOCTL_REG_OPS
|-
|-
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
| 0x40084403 || In || 8 || NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL
|-
| 0x40044404 || In || 4 || NVGPU_DBG_GPU_IOCTL_POWERGATE
|-
| 0x40044405 || In || 4 || NVGPU_DBG_GPU_IOCTL_SMPC_CTXSW_MODE
|-
| 0x40044406 || In || 4 || NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_ALL_SMS
|-
| 0xC0184407 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_PERFBUF_MAP
|-
| 0x40084408 || In || 8 || NVGPU_DBG_GPU_IOCTL_PERFBUF_UNMAP
|-
|-
| 0xC0104417 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_COMPTAGS
| 0x40084409 || In || 8 || NVGPU_DBG_GPU_IOCTL_PC_SAMPLING
|-
|-
| 0xC0104418 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_PA
| 0x4008440A || In || 8 || NVGPU_DBG_GPU_IOCTL_TIMEOUT
|-
|-
| 0xC0104419 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_PA
| 0x8008440B || Out || 8 || NVGPU_DBG_GPU_IOCTL_GET_TIMEOUT
|-
|-
| 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA
| 0x8004440C || Out || 4 || NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT_SIZE
|-
|-
| 0xC020441B || Inout || 32 || [11.0.0+]
| 0x0000440D || None || 0 || [[#NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT]]
|-
|-
| 0xC020441E || Inout || 32 || [11.0.0+]
| 0xC018440E || Inout || 24 || NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY
|}
 
=== NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT ===
Uses [[#Ioctl3|Ioctl3]].
 
=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES ===
Uses [[#Ioctl3|Ioctl3]].
 
=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES ===
Uses [[#Ioctl3|Ioctl3]].
 
=== NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS ===
Uses [[#Ioctl3|Ioctl3]].
 
=== NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS ===
Uses [[#Ioctl2|Ioctl2]].
 
== /dev/nvhost-prof-gpu ==
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.
 
This device is identical to [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]].
 
== /dev/nvhost-ctrl-gpu ==
This device is for global (context independent) operations on the gpu. 
                                                                                                                                             
{| class="wikitable" border="1"
! Value || Direction || Size || Description
|-
|-
| 0x80044701 || Out || 4 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE]]
| 0xC018440F || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PDES
|-
|-
| 0x80284702 || Out || 40 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_INFO]]
| 0xC0104410 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES]]
|-
|-
| 0x402C4703 || In || 44 || [[#NVGPU_GPU_IOCTL_ZBC_SET_TABLE]]
| 0xC0184411 || Inout || 24 || NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_NUM_PTES
|-
|-
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
| 0xC0104412 || Inout || 16 || [[#NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES]]
|-
|-
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
| 0xC0684413 || Inout || 104 || NVGPU_DBG_GPU_IOCTL_GET_COMPTAG_INFO
|-
|-
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
| 0xC0184414 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS]]
|-
|-
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
| 0xC0184415 || Inout || 24 || [[#NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS]]
|-
|-
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]
| 0xC0104416 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_COMPTAGS
|-
| 0xC0104417 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_COMPTAGS
|-
| 0xC0104418 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_RESERVE_PA
|-
|-
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
| 0xC0104419 || Inout || 16 || NVGPU_DBG_GPU_IOCTL_FREE_RESERVED_PA
|-
|-
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
| 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA
|-
|-
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
| 0xC020441B || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA_EX
|-
|-
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
| 0xC084441C || Inout || 132 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SETTINGS
|-
|-
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
| 0xC018441D || Inout || 24 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SERIAL_NUMBER
|-
|-
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
|-
|-
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
| [S2] 0xC0184421 || || ||
|-
|-
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
| [S2] 0x40084422 || || ||
|-
|-
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
| [S2] 0xC0084423 || || ||
|-
|-
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
| [S2] 0x40084424 || || ||
|-
|-
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
| [S2] 0xC0104425 || || ||
|-
|-
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
| [S2] 0x40084427 || || ||
|-
|-
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
| [S2] 0x40044428 || || ||
|-
|-
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
| [S2] 0xC0184429 || || ||
|-
|-
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
| [S2] 0x4010442A || || ||
|-
|-
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
| [S2] 0x4010442B || || ||
|}
|}


=== NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE ===
=== NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT ===
Returns the GPU's ZCULL context size. Identical to Linux driver.
Uses [[#Ioctl3|Ioctl3]].


struct {
=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PDES ===
    __out u32 size;
Uses [[#Ioctl3|Ioctl3]].
  };
 
=== NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PTES ===
Uses [[#Ioctl3|Ioctl3]].


=== NVGPU_GPU_IOCTL_ZCULL_GET_INFO ===
=== NVGPU_DBG_GPU_IOCTL_READ_COMPTAGS ===
Returns GPU's ZCULL information. Identical to Linux driver.
Uses [[#Ioctl3|Ioctl3]].


struct {
=== NVGPU_DBG_GPU_IOCTL_WRITE_COMPTAGS ===
    __out u32 width_align_pixels;
Uses [[#Ioctl2|Ioctl2]].
    __out u32 height_align_pixels;
    __out u32 pixel_squares_by_aliquots;
    __out u32 aliquot_total;
    __out u32 region_byte_multiplier;
    __out u32 region_header_size;
    __out u32 subregion_header_size;
    __out u32 subregion_width_align_pixels;
    __out u32 subregion_height_align_pixels;
    __out u32 subregion_count;
  };


=== NVGPU_GPU_IOCTL_ZBC_SET_TABLE ===
== /dev/nvhost-prof-gpu ==
Sets the active ZBC table. Identical to Linux driver.
Returns [[#Errors|NotSupported]] on Open unless nn::settings::detail::GetDebugModeFlag is set.


struct {
This device is identical to [[#/dev/nvhost-dbg-gpu|/dev/nvhost-dbg-gpu]].
    __in u32 color_ds[4];
    __in u32 color_l2[4];
    __in u32 depth;
    __in u32 format;
    __in u32 type;        // 1=color, 2=depth
  };


=== NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE ===
== /dev/nvhost-ctrl-gpu ==
Queries the active ZBC table. Identical to Linux driver.
This device is for global (context independent) operations on the gpu.
 
                                                                                                                                             
struct {
{| class="wikitable" border="1"
    __out u32 color_ds[4];
! Value || Direction || Size || Description
    __out u32 color_l2[4];
|-
    __out u32 depth;
| 0x80044701 || Out || 4 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE]]
    __out u32 ref_cnt;
|-
    __out u32 format;
| 0x80284702 || Out || 40 || [[#NVGPU_GPU_IOCTL_ZCULL_GET_INFO]]
    __out u32 type;
|-
    __inout u32 index_size;
| 0x402C4703 || In || 44 || [[#NVGPU_GPU_IOCTL_ZBC_SET_TABLE]]
  };
|-
 
| 0xC0344704 || Inout || 52 || [[#NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE]]
=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
|-
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.
| 0xC0B04705 || Inout || 176 || [[#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS]]
 
|-
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
| 0xC0184706 || Inout || 24 || [[#NVGPU_GPU_IOCTL_GET_TPC_MASKS]]
 
|-
  struct gpu_characteristics {
| 0x40084707 || In || 8 || [[#NVGPU_GPU_IOCTL_FLUSH_L2]]
    u32 arch;                      // 0x120 (NVGPU_GPU_ARCH_GM200)
|-
    u32 impl;                      // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
| 0x4008470D || In || 8 || [[#NVGPU_GPU_IOCTL_INVAL_ICACHE]]
    u32 rev;                        // 0xA1 (Revision A1)
|-
    u32 num_gpc;                    // 0x1
| 0x4008470E || In || 8 || [[#NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE]]
    u64 l2_cache_size;              // 0x40000
|-
    u64 on_board_video_memory_size; // 0x0 (not used)
| 0x4010470F || In || 16 || [[#NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE]]
    u32 num_tpc_per_gpc;            // 0x2
|-
    u32 bus_type;                  // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
| 0xC0304710</br>([1.0.0-6.1.0] 0xC0084710) || Inout || 48</br>([1.0.0-6.1.0] 8) || [[#NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE]]
    u32 big_page_size;              // 0x20000
|-
    u32 compression_page_size;      // 0x20000
| 0x80084711 || Out || 8 || [[#NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS]]
    u32 pde_coverage_bit_count;    // 0x1B
|-
    u32 available_big_page_sizes;  // 0x30000
| 0x80084712 || Out || 8 || [[#NVGPU_GPU_IOCTL_NUM_VSMS]]
    u32 gpc_mask;                  // 0x1
|-
    u32 sm_arch_sm_version;        // 0x503 (Maxwell Generation 5.0.3)
| 0xC0044713 || Inout || 4 || [[#NVGPU_GPU_IOCTL_VSMS_MAPPING]]
    u32 sm_arch_spa_version;        // 0x503 (Maxwell Generation 5.0.3)
|-
    u32 sm_arch_warp_count;        // 0x80
| 0x80084714 || Out || 8 || [[#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK]]
    u32 gpu_va_bit_count;          // 0x28
|-
    u32 reserved;                  // NULL
| 0x80044715 || Out || 4 || [[#NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD]]
    u64 flags;                      // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
|-
    u32 twod_class;                // 0x902D (FERMI_TWOD_A)
| 0x40084716 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_CG_CONTROLS]]
    u32 threed_class;              // 0xB197 (MAXWELL_B)
|-
    u32 compute_class;              // 0xB1C0 (MAXWELL_COMPUTE_B)
| 0xC0084717 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_CG_CONTROLS]]
    u32 gpfifo_class;              // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
|-
    u32 inline_to_memory_class;    // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
| 0x40084718 || In || 8 || [[#NVGPU_GPU_IOCTL_SET_PG_CONTROLS]]
    u32 dma_copy_class;            // 0xB0B5 (MAXWELL_DMA_COPY_A)
|-
    u32 max_fbps_count;            // 0x1
| 0xC0084719 || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_PG_CONTROLS]]
    u32 fbp_en_mask;                // 0x0 (disabled)
|-
    u32 max_ltc_per_fbp;            // 0x2
| 0x8018471A || Out || 24 || [[#NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING]]
    u32 max_lts_per_ltc;            // 0x1
|-
    u32 max_tex_per_tpc;            // 0x0 (not supported)
| 0xC008471B || Inout || 8 || [[#NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA]]
    u32 max_gpc_count;              // 0x1
|-
    u32 rop_l2_en_mask_0;          // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
| 0xC010471C || Inout || 16 || [[#NVGPU_GPU_IOCTL_GET_GPU_TIME]]
    u32 rop_l2_en_mask_1;          // 0x0
|-
    u64 chipname;                  // 0x6230326D67 ("gm20b")
| 0xC108471D || Inout || 264 || [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
    u64 gr_compbit_store_base_hw;  // 0x0 (not supported)
|}
  };
  struct {
    __inout u64 gpu_characteristics_buf_size;  // must not be NULL, but gets overwritten with 0xA0=max_size
    __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
    __out struct gpu_characteristics gc;
  };


=== NVGPU_GPU_IOCTL_GET_TPC_MASKS ===
=== NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE ===
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer.
Returns the GPU's ZCULL context size. Identical to Linux driver.


[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].
struct {
 
     __out u32 size;
  struct {
     __in u32 mask_buf_size;      // ignored, but must not be NULL
    __in u32 reserved[3];
    __out u64 mask_buf;           // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
   };
   };


=== NVGPU_GPU_IOCTL_FLUSH_L2 ===
=== NVGPU_GPU_IOCTL_ZCULL_GET_INFO ===
Flushes the GPU L2 cache.
Returns GPU's ZCULL information. Identical to Linux driver.


  struct {
struct {
     __in u32 flush;         // l2_flush | l2_invalidate << 1 | fb_flush << 2
     __out u32 width_align_pixels;
     __in u32 reserved;
     __out u32 height_align_pixels;
    __out u32 pixel_squares_by_aliquots;
    __out u32 aliquot_total;
    __out u32 region_byte_multiplier;
    __out u32 region_header_size;
    __out u32 subregion_header_size;
    __out u32 subregion_width_align_pixels;
    __out u32 subregion_height_align_pixels;
    __out u32 subregion_count;
   };
   };


=== NVGPU_GPU_IOCTL_INVAL_ICACHE ===
=== NVGPU_GPU_IOCTL_ZBC_SET_TABLE ===
Invalidates the GPU instruction cache. Identical to Linux driver.
Sets the active ZBC table. Identical to Linux driver.


  struct {
struct {
     __in s32 channel_fd;
     __in u32 color_ds[4];
     __in u32 reserved;
    __in u32 color_l2[4];
    __in u32 depth;
    __in u32 format;
     __in u32 type;         // 1=color, 2=depth
   };
   };


=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE ===
=== NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE ===
Sets the GPU MMU debug mode. Identical to Linux driver.
Queries the active ZBC table. Identical to Linux driver.


  struct {
struct {
     __in u32 state;
     __out u32 color_ds[4];
     __in u32 reserved;
     __out u32 color_l2[4];
    __out u32 depth;
    __out u32 ref_cnt;
    __out u32 format;
    __out u32 type;
    __inout u32 index_size;
   };
   };


=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE ===
=== NVGPU_GPU_IOCTL_GET_CHARACTERISTICS ===
Sets the GPU SM debug mode. Identical to Linux driver.
Returns the GPU characteristics. Modified to return inline data instead of using a pointer.
 
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].


   struct {
   struct gpu_characteristics {
     __in s32 channel_fd;
     u32 arch;                      // 0x120 (NVGPU_GPU_ARCH_GM200)
     __in u32 enable;
    u32 impl;                      // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
     __in u64 sms;
    u32 rev;                       // 0xA1 (Revision A1)
  };
     u32 num_gpc;                   // 0x1
 
     u64 l2_cache_size;             // 0x40000
=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
    u64 on_board_video_memory_size; // 0x0 (not used)
Waits until all valid warps on the GPU SM are paused and returns their current state.
    u32 num_tpc_per_gpc;           // 0x2
 
    u32 bus_type;                  // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
   struct {
    u32 big_page_size;              // 0x20000
     __in u64 pwarpstate;
    u32 compression_page_size;      // 0x20000
  };
    u32 pde_coverage_bit_count;    // 0x1B
 
    u32 available_big_page_sizes;   // 0x30000
[6.1.0+] This command was modified to return inline data instead of using a pointer.
     u32 gpc_mask;                   // 0x1
 
    u32 sm_arch_sm_version;         // 0x503 (Maxwell Generation 5.0.3)
  struct {
    u32 sm_arch_spa_version;        // 0x503 (Maxwell Generation 5.0.3)
     __out u64 sm0_valid_warps;
    u32 sm_arch_warp_count;        // 0x80
     __out u64 sm0_trapped_warps;
    u32 gpu_va_bit_count;          // 0x28
     __out u64 sm0_paused_warps;
    u32 reserved;                  // NULL
     __out u64 sm1_valid_warps;
     u64 flags;                      // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
     __out u64 sm1_trapped_warps;
    u32 twod_class;                // 0x902D (FERMI_TWOD_A)
     __out u64 sm1_paused_warps;
    u32 threed_class;              // 0xB197 (MAXWELL_B)
    u32 compute_class;              // 0xB1C0 (MAXWELL_COMPUTE_B)
    u32 gpfifo_class;              // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
    u32 inline_to_memory_class;     // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
     u32 dma_copy_class;            // 0xB0B5 (MAXWELL_DMA_COPY_A)
    u32 max_fbps_count;            // 0x1
    u32 fbp_en_mask;                // 0x0 (disabled)
    u32 max_ltc_per_fbp;            // 0x2
    u32 max_lts_per_ltc;            // 0x1
    u32 max_tex_per_tpc;            // 0x0 (not supported)
    u32 max_gpc_count;             // 0x1
     u32 rop_l2_en_mask_0;           // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
     u32 rop_l2_en_mask_1;           // 0x0
     u64 chipname;                   // 0x6230326D67 ("gm20b")
     u64 gr_compbit_store_base_hw;   // 0x0 (not supported)
   };
   };
 
=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.
 
   struct {
   struct {
     __out u64 tpc_exception_en_sm_mask;
    __inout u64 gpu_characteristics_buf_size;  // must not be NULL, but gets overwritten with 0xA0=max_size
    __in    u64 gpu_characteristics_buf_addr;  // ignored, but must not be NULL
     __out struct gpu_characteristics gc;
   };
   };


=== NVGPU_GPU_IOCTL_NUM_VSMS ===
=== NVGPU_GPU_IOCTL_GET_TPC_MASKS ===
Returns the number of GPU SM units present. Identical to Linux driver.
Returns the TPC mask value for each GPC. Modified to return inline data instead of using a pointer.
 
[3.0.0+] Uses either [[#Ioctl|Ioctl]] or [[#Ioctl3|Ioctl3]].


   struct {
   struct {
     __out u32 num_vsms;
     __in u32 mask_buf_size;       // ignored, but must not be NULL
     __out u32 reserved;
     __in u32 reserved[3];
    __out u64 mask_buf;           // receives one 32-bit TPC mask per GPC (GPC 0 and GPC 1)
   };
   };


=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
=== NVGPU_GPU_IOCTL_FLUSH_L2 ===
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.
Flushes the GPU L2 cache.


   struct {
   struct {
     __out u8 sm0_gpc_index;
     __in u32 flush;         // l2_flush | l2_invalidate << 1 | fb_flush << 2
     __out u8 sm0_tpc_index;
     __in u32 reserved;
    __out u8 sm1_gpc_index;
    __out u8 sm1_tpc_index;
   };
   };


=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
=== NVGPU_GPU_IOCTL_INVAL_ICACHE ===
Returns the mask value for a ZBC slot.
Invalidates the GPU instruction cache. Identical to Linux driver.


   struct {
   struct {
     __out u32 slot;       // always 0x07
     __in s32 channel_fd;
     __out u32 mask;
     __in u32 reserved;
   };
   };


=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
=== NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE ===
Returns the GPU load value from the PMU.
Sets the GPU MMU debug mode. Identical to Linux driver.


   struct {
   struct {
     __out u32 pmu_gpu_load;
     __in u32 state;
    __in u32 reserved;
   };
   };


=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
=== NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE ===
Sets the clock gate control value.
Sets the GPU SM debug mode. Identical to Linux driver.


   struct {
   struct {
     __in u32 cg_mask;
    __in s32 channel_fd;
     __in u32 cg_value;
     __in u32 enable;
     __in u64 sms;
   };
   };


=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
=== NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE ===
Returns the clock gate control value.
Waits until all valid warps on the GPU SM are paused and returns their current state.


   struct {
   struct {
     __in u32 cg_mask;
     __in u64 pwarpstate;
    __out u32 cg_value;
   };
   };


=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
[6.1.0+] This command was modified to return inline data instead of using a pointer.
Sets the power gate control value.


   struct {
   struct {
     __in u32 pg_mask;
     __out u64 sm0_valid_warps;
     __in u32 pg_value;
     __out u64 sm0_trapped_warps;
    __out u64 sm0_paused_warps;
    __out u64 sm1_valid_warps;
    __out u64 sm1_trapped_warps;
    __out u64 sm1_paused_warps;
   };
   };


=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
=== NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS ===
Returns the power gate control value.
Returns a mask value describing all active TPC exceptions. Identical to Linux driver.


   struct {
   struct {
    __in u32 pg_mask;
     __out u64 tpc_exception_en_sm_mask;
     __out u32 pg_value;
   };
   };


=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
=== NVGPU_GPU_IOCTL_NUM_VSMS ===
Returns the GPU PMU ELPG residency gating values.
Returns the number of GPU SM units present. Identical to Linux driver.


   struct {
   struct {
     __out u64 pg_ingating_time_us;
     __out u32 num_vsms;
     __out u64 pg_ungating_time_us;
     __out u32 reserved;
    __out u64 pg_gating_cnt;
   };
   };


=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
=== NVGPU_GPU_IOCTL_VSMS_MAPPING ===
Returns user specific data from the error channel, if one exists.
Returns mapping information on each GPU SM unit. Modified to return inline data instead of using a pointer.


   struct {
   struct {
     __out u64 data;
     __out u8 sm0_gpc_index;
    __out u8 sm0_tpc_index;
    __out u8 sm1_gpc_index;
    __out u8 sm1_tpc_index;
   };
   };


=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
=== NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK ===
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.
Returns the mask value for a ZBC slot.


   struct {
   struct {
     __out u64 gpu_timestamp;     // raw GPU counter (PTIMER) value
     __out u32 slot;       // always 0x07
     __out u64 reserved;
     __out u32 mask;
   };
   };


=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
=== NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD ===
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.
Returns the GPU load value from the PMU.


struct time_correlation_sample {
  struct {
  u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register
    __out u32 pmu_gpu_load;
  u64 gpu_timestamp;                                  // from GPU's PTIMER registers
  };
};
struct {
  __out struct time_correlation_sample samples[16];  // timestamp pairs
  __in u32     count;                                 // number of pairs to read
  __in u32    source_id;                            // cpu clock source id (must be 1)
};


= Channels =
=== NVGPU_GPU_IOCTL_SET_CG_CONTROLS ===
Channels are a concept for NVIDIA hardware blocks that share a common interface.
Sets the clock gate control value.


{| class="wikitable" border="1"
  struct {
! Path || Name
    __in u32 cg_mask;
|-
    __in u32 cg_value;
| /dev/nvhost-gpu || GPU
  };
|-
 
| /dev/nvhost-msenc || Video Encoder
=== NVGPU_GPU_IOCTL_GET_CG_CONTROLS ===
|-
Returns the clock gate control value.
| /dev/nvhost-nvdec || Video Decoder
 
|-
  struct {
| /dev/nvhost-nvjpg || JPEG Decoder
    __in u32 cg_mask;
|-
    __out u32 cg_value;
| /dev/nvhost-vic || Video Image Compositor
  };
|-
| /dev/nvhost-display || Display
|}


== Ioctls ==
=== NVGPU_GPU_IOCTL_SET_PG_CONTROLS ===
{| class="wikitable" border="1"
Sets the power gate control value.
! Value || Size || Description
 
|-
  struct {
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
    __in u32 pg_mask;
|-
    __in u32 pg_value;
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
  };
|-
 
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
=== NVGPU_GPU_IOCTL_GET_PG_CONTROLS ===
|-
Returns the power gate control value.
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
 
|-
  struct {
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
    __in u32 pg_mask;
|-
    __out u32 pg_value;
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
  };
|-
 
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
=== NVGPU_GPU_IOCTL_PMU_GET_ELPG_RESIDENCY_GATING ===
|-
Returns the GPU PMU ELPG residency gating values.
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
 
|-
  struct {
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
    __out u64 pg_ingating_time_us;
|-
    __out u64 pg_ungating_time_us;
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
    __out u64 pg_gating_cnt;
|-
  };
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
 
|-
=== NVGPU_GPU_IOCTL_GET_ERROR_CHANNEL_USER_DATA ===
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
Returns user specific data from the error channel, if one exists.
|-
 
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
  struct {
|- style="border-top: double"
    __out u64 data;
| 0x40044801 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
  };
|-
 
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
=== NVGPU_GPU_IOCTL_GET_GPU_TIME ===
|-
Returns the timestamp from the GPU's nanosecond timer (PTIMER). Identical to Linux driver.
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
 
|-
  struct {
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
    __out u64 gpu_timestamp;      // raw GPU counter (PTIMER) value
|-
    __out u64 reserved;
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
  };
 
=== NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO ===
Returns CPU/GPU timestamp pairs for correlation analysis. Identical to Linux driver.
 
struct time_correlation_sample {
  u64 cpu_timestamp;                                  // from CPU's CNTPCT_EL0 register
  u64 gpu_timestamp;                                  // from GPU's PTIMER registers
};
struct {
  __out struct time_correlation_sample samples[16];  // timestamp pairs
  __in u32    count;                                // number of pairs to read
  __in u32    source_id;                            // cpu clock source id (must be 1)
};
 
= Channels =
Channels are a concept for NVIDIA hardware blocks that share a common interface.
 
{| class="wikitable" border="1"
! Path || Name
|-
|-
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
| /dev/nvhost-gpu || GPU
|-
|-
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
| /dev/nvhost-msenc || Video Encoder
|-
|-
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
| /dev/nvhost-nvdec || Video Decoder
|-
|-
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
| /dev/nvhost-nvjpg || JPEG Decoder
|-
|-
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
| /dev/nvhost-vic || Video Image Compositor
|-
|-
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
| /dev/nvhost-display || Display
|-
|-
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
| /dev/nvhost-tsec || TSEC
|}
 
== Ioctls ==
{| class="wikitable" border="1"
! Value || Size || Description
|-
|-
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
| 0xC0??0001 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT]]
|-
|-
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
| 0xC0080002 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT]]
|-
|-
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
| 0xC0080003 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_WAITBASE]]
|-
|-
| 0x40084812 || 8 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
| 0xC0080004 || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_MODMUTEX]]
|-
|-
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
| 0x40040007 || 4 || [[#NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT]]
|-
|-
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
| 0x40080008 || 8 || [[#NVHOST_IOCTL_CHANNEL_SET_CLK_RATE]]
|-
|-
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
| 0xC0??0009 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER]]
|-
|-
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
| 0xC0??000A || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER]]
|-
|-
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
| 0x00000013 || 0 || [[#NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX]]
|-
|-
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
| 0xC0080023</br>([1.0.0-7.0.1] 0xC0080014) || 8 || [[#NVHOST_IOCTL_CHANNEL_GET_CLK_RATE]]
|-
|-
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
| 0xC0??0024 || Variable || [[#NVHOST_IOCTL_CHANNEL_SUBMIT_EX]]
|-
|-
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
| 0xC0??0025 || Variable || [[#NVHOST_IOCTL_CHANNEL_MAP_CMD_BUFFER_EX]]
|-
|-
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
| 0xC0??0026 || Variable || [[#NVHOST_IOCTL_CHANNEL_UNMAP_CMD_BUFFER_EX]]
|- style="border-top: double"
|- style="border-top: double"
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
| 0x40044801 [S2] 0x40044101 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD]]
|-
| 0x40044803 || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMEOUT]]
|-
| 0x40084805 || 8 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO]]
|-
| 0x40184806 || 24 || [[#NVGPU_IOCTL_CHANNEL_WAIT]]
|-
| 0xC0044807 || 4 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS]]
|-
| 0xC0??4808 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO]]
|-
| 0xC0104809 || 16 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX]]
|-
|-
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
| 0x4008480A || 8 || [[#NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX]]
|}
|-
 
| 0xC010480B || 16 || [[#NVGPU_IOCTL_CHANNEL_ZCULL_BIND]]
=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
|-
Submits data to the channel.
| 0xC018480C || 24 || [[#NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER]]
 
|-
  struct cmdbuf {
| 0x4004480D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_PRIORITY]]
    u32 mem;
|-
    u32 offset;
| 0x0000480E || 0 || [[#NVGPU_IOCTL_CHANNEL_ENABLE]]
    u32 words;
|-
  };
| 0x0000480F || 0 || [[#NVGPU_IOCTL_CHANNEL_DISABLE]]
 
|-
  struct reloc {
| 0x00004810 || 0 || [[#NVGPU_IOCTL_CHANNEL_PREEMPT]]
    u32 cmdbuf_mem;
|-
    u32 cmdbuf_offset;
| 0x00004811 || 0 || [[#NVGPU_IOCTL_CHANNEL_FORCE_RESET]]
    u32 target;
|-
    u32 target_offset;
| 0x40084812 [S2] 0x40104812 || 8 [S2] 16 || [[#NVGPU_IOCTL_CHANNEL_EVENT_ID_CONTROL]]
  };
|-
 
| 0xC0104813 || 16 || [[#NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT]]
  struct reloc_shift {
|-
    u32 shift;
| 0x40084714 || 8 || [[#NVGPU_IOCTL_CHANNEL_SET_USER_DATA]]
  };
|-
 
| 0x80084715 || 8 || [[#NVGPU_IOCTL_CHANNEL_GET_USER_DATA]]
  struct syncpt_incr {
|-
    u32 syncpt_id;
| 0x80804816 || 128 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO]]
    u32 syncpt_incrs;
|-
  };
| 0xC0104817 || 16 || [[#NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION]]
 
|-
  struct fence {
| 0x40204818 || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX]]
    u32 id;
|-
    u32 thresh;
| 0xC0??4819 || Variable || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO_RETRY]]
  };
|-
 
| 0xC020481A || 32 || [[#NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX2]]
  struct {
|-
    __in    u32 num_cmdbufs;
| 0xC018481B || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2]]
    __in    u32 num_relocs;
|-
    __in    u32 num_syncpt_incrs;
| 0xC018481C || 24 || [[#NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO2_RETRY]]
    __in    u32 num_fences;
|-
    __in    struct cmdbuf cmdbufs[];              // depends on num_cmdbufs
| 0xC004481D || 4 || [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
    __in    struct reloc relocs[];                // depends on num_relocs
|- style="border-top: double"
    __in    struct reloc_shift reloc_shifts[];    // depends on num_relocs
| [S2] 0xC010481E || 16 ||
    __in    struct syncpt_incr syncpt_incrs[];    // depends on num_syncpt_incrs
|-
    __out  struct fence fences[];                // depends on num_fences
| [S2] 0xC008481F || 8 ||
  };
|-
| [S2] 0x40044820 || 4 ||
|-
| [S2] 0xC0504821 || 80 ||
|}


=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
=== NVHOST_IOCTL_CHANNEL_SUBMIT ===
Returns the current syncpoint value for a given module. Identical to Linux driver.
Submits data to the channel.


   struct {
   struct cmdbuf {
     __in    u32 module_id;
     u32 mem;
     __out  u32 syncpt_value;
     u32 offset;
    u32 words;
   };
   };
 
 
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
  struct reloc {
Returns the current waitbase value for a given module. Always returns 0.
    u32 cmdbuf_mem;
 
    u32 cmdbuf_offset;
    u32 target;
    u32 target_offset;
  };
 
  struct reloc_shift {
    u32 shift;
  };
 
  struct syncpt_incr {
    u32 syncpt_id;
    u32 syncpt_incrs;
    u32 reserved[3];
  };
 
   struct {
   struct {
     __in    u32 module_id;
     __in    u32 num_cmdbufs;
     __out  u32 waitbase_value;
    __in    u32 num_relocs;
    __in    u32 num_syncpt_incrs;
    __in    u32 num_fences;
    __in    struct cmdbuf cmdbufs[];              // depends on num_cmdbufs
    __in    struct reloc relocs[];                // depends on num_relocs
    __in    struct reloc_shift reloc_shifts[];    // depends on num_relocs
    __in    struct syncpt_incr syncpt_incrs[];    // depends on num_syncpt_incrs
     __out  u32 fence_thresholds[];               // depends on num_fences
   };
   };


=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
=== NVHOST_IOCTL_CHANNEL_GET_SYNCPOINT ===
Stubbed. Does a debug print and returns 0.
Returns the current syncpoint value for a given module. Identical to Linux driver.
 
 
=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
  struct {
Sets the submit timeout value for the channel. Identical to Linux driver.
    __in    u32 module_id;
    __out  u32 syncpt_value;
  };
 
=== NVHOST_IOCTL_CHANNEL_GET_WAITBASE ===
Returns the current waitbase value for a given module. Always returns 0.
 
  struct {
    __in    u32 module_id;
    __out  u32 waitbase_value;
  };
 
=== NVHOST_IOCTL_CHANNEL_GET_MODMUTEX ===
Stubbed. Does a debug print and returns 0.
 
=== NVHOST_IOCTL_CHANNEL_SET_SUBMIT_TIMEOUT ===
Sets the submit timeout value for the channel. Identical to Linux driver.


   struct {
   struct {
Line 1,814: Line 2,141:
   struct {
   struct {
     __in u32 num_entries;
     __in u32 num_entries;
     __in u32 flags;
     __in u32 flags;           // bit0: vpr_enabled
   };
   };


Line 1,841: Line 2,168:
   struct fence {
   struct fence {
     u32 id;
     u32 id;
     u32 thresh;
     u32 value;
   };
   };
    
    
   struct gpfifo_entry {
   struct gpfifo_entry {
     u64 entry;                               // gpu_iova | (unk_2bits << 40) | (size << 42) | (unk_flag << 63)
     u32 entry0;                             // gpu_iova_lo
    u32 entry1;                              // gpu_iova_hi | (allow_flush << 8) | (is_push_buf << 9) | (size << 10) | (sync << 31)
   };
   };
    
    
Line 1,851: Line 2,179:
     __in    u64 gpfifo;                      // (ignored) pointer to gpfifo fence structs
     __in    u64 gpfifo;                      // (ignored) pointer to gpfifo fence structs
     __in    u32 num_entries;                // number of fence objects being submitted
     __in    u32 num_entries;                // number of fence objects being submitted
     __in   u32 flags;
     union {
      __out u32 detailed_error;
      __in u32 flags;                      // bit0: fence_wait, bit1: fence_get, bit2: hw_format, bit3: sync_fence, bit4: suppress_wfi, bit5: skip_buffer_refcounting
    };
     __inout struct fence fence_out;          // returned new fence object for others to wait on
     __inout struct fence fence_out;          // returned new fence object for others to wait on
     __in    struct gpfifo_entry entries[];  // depends on num_entries
     __in    struct gpfifo_entry entries[];  // depends on num_entries
Line 1,934: Line 2,265:


   struct {
   struct {
     __out u32 error_info[32];   // first word is an error code (0=no_error, 1=gr_error, 2=gr_error, 3=invalid, 4=invalid)
     __out u32 type;     // Error type (0=no_error, 1=mmu_error, 2=gr_error, 3=pbdma_error, 4=timeout)
   };
    __out u32 info[31]; // Infor depends on the error type
 
   };  
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
Returns the current error notification caught by the error notifier. Exclusive to the Switch.


==== GR Error Code Format ====
When <code>type == 2</code> (GR Error), the returned data is formatted as follows:
   struct {
   struct {
     __out u64 timestamp;   // fetched straight from armGetSystemTick
     __out u32 type;      // 2=gr_error
     __out u32 info32;      // error code
    __out u32 intr_value; // Interrupt bits
     __out u16 info16;       // additional error info
     __out u32 addr;      // Register address (in bytes)
     __out u16 status;       // always 0xFFFF
     __out u32 data_hi;   // Data high 32 bits
   };
    __out u32 data_lo;    // Data low 32 bits
     __out u32 class_num; // GPU class number (e.g., 0xb197 for MAXWELL_B)
   };  


=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX ===
{| class="wikitable"
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.
|+ GR Error Interrupt Bits
|-
! Bit(s)
! Description
|-
| 0
| GR_INTR_NOTIFY
|-
| 1
| GR_INTR_SEMAPHORE
|-
| 2
| unknown
|-
| 3
| unknown
|-
| 4
| GR_INTR_ILLEGAL_METHOD
|-
| 5
| GR_INTR_ILLEGAL_CLASS
|-
| 6
| GR_INTR_ILLEGAL_NOTIFY
|-
| 7
| unknown
|-
| 8
| GR_INTR_FIRMWARE_METHOD
|-
| 9–18
| unknown
|-
| 19
| GR_INTR_FECS_ERROR
|-
| 20
| GR_INTR_CLASS_ERROR
|-
| 21
| GR_INTR_EXCEPTION
|-
| 22–31
| unknown
|}


  struct fence {
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
Returns the current error notification caught by the error notifier. Exclusive to the Switch.
 
  struct {
    __out u64 timestamp;    // fetched straight from armGetSystemTick
    __out u32 info32;      // error code
    __out u16 info16;      // additional error info
    __out u16 status;      // always 0xFFFF
  };
 
=== NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX ===
Allocates gpfifo entries with additional parameters. Exclusive to the Switch.
 
  struct fence {
     u32 id;
     u32 id;
     u32 thresh;
     u32 value;
  };
  };
   
   
Line 1,958: Line 2,350:
   __in    u32 num_entries;
   __in    u32 num_entries;
   __in    u32 num_jobs;
   __in    u32 num_jobs;
   __in    u32 flags;
   __in    u32 flags;                       // bit0: vpr_enabled
   __out  struct fence fence_out;          // returned new fence object for others to wait on
   __out  struct fence fence_out;          // returned new fence object for others to wait on
   __in    u32 reserved[3];                // ignored
   __in    u32 reserved[3];                // ignored
Line 2,058: Line 2,450:
| 13
| 13
|
|
|  
| Can use the GPU virtual address range 0xC0000 to 0x580000 instead of 0x0 to 0xC0000.
|-
|-
| 14
| 14
Line 2,066: Line 2,458:
| 15
| 15
|
|
|  
| Can use the virtual address ranges 0x0 to 0x100000000 (GPU) and 0x0 to 0xE0000000 (non-GPU) instead of 0x100000000 to 0x11FA50000 (GPU) and 0xE0000000 to 0xFFFE0000 (non-GPU).
|}
|}


Line 2,189: Line 2,581:


{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
! Offset
! Offset
! Size
! Size
! Description
! Description
|-
|-
| 0x0
| 0x0
| 0x4
| 0x4
| FreeSize
| FreeSize
|-
|-
| 0x4
| 0x4
| 0x4
| 0x4
| AllocatableSize
| AllocatableSize
|-
|-
| 0x8
| 0x8
| 0x4
| 0x4
| MinimumFreeSize
| MinimumFreeSize
|-
|-
| 0xC
| 0xC
| 0x4
| 0x4
| MinimumAllocatableSize
| MinimumAllocatableSize
|-
|-
| 0x10
| 0x10
| 0x10
| 0x10
| Reserved
| Reserved
|}
|}
 
= Notes =
In some cases, a panic may occur. NV forces a crash by doing:
(void *)0 = 0xCAFE;
End result is that the system hangs with a white-screen.
 
When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done.


= Notes =
GPU rendering (GPFIFO) is only used by applets/Applications. All sysmodules doing any gfx-display uses software rendering. During system-boot, GPU GPFIFO is not used until the applets are launched.
In some cases, a panic may occur. NV forces a crash by doing:
(void *)0 = 0xCAFE;
End result is that the system hangs with a white-screen.
 
When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done.


[[Category:Services]]
[[Category:Services]]
Retrieved from "https://switchbrew.org/wiki/NV_services"