1
edit
Changes
→NVGPU_IOCTL_CHANNEL_GET_ERROR_INFO
QueryEvent is only supported on (and implemented differently on):
QueryEvent is only supported on (and implemented differently on):
* /dev/nvhost-gpu
* /dev/nvhost-gpu
** 1: SmException_BptIntReport
** EvtId=1: SmException_BptIntReport
** 2: SmException_BptPauseReport
** EvtId=2: SmException_BptPauseReport
** 3: ErrorNotifierEvent
** EvtId=3: ErrorNotifierEvent
* /dev/nvhost-ctrl: Used to get events for SyncPts.
* /dev/nvhost-ctrl: Used to get events for syncpts.
** If bit31-28 is 1, then lower 16-bits contain event_slot, bit27-16 contain syncpt_number.
** EvtId=(event_slot | ((syncpt_id & 0xFFF) << 16) | (is_valid << 28)): New format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]/[[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX|NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]].
** If bit31-28 is 0, then lower 4-bits contain event_slot, bit31-4 contains syncpt_number.
** EvtId=(event_slot | (syncpt_id << 4)): Old format used by [[#NVHOST_IOCTL_CTRL_SYNCPT_WAITEX|NVHOST_IOCTL_CTRL_SYNCPT_WAITEX]].
* /dev/nvhost-ctrl-gpu
* /dev/nvhost-ctrl-gpu
** 1: Returns error_event_handle.
** EvtId=1: Returns error_event_handle.
** 2: Returns unknown event.
** EvtId=2: Returns unknown event.
* /dev/nvhost-dbg-gpu
* /dev/nvhost-dbg-gpu
** Ignores event_id.
** Ignores EvtId.
== MapSharedMem ==
== MapSharedMem ==
| 6 || [[#Reset|Reset]]
| 6 || [[#Reset|Reset]]
|-
|-
| 7 || [3.0.0+]
| 7 || [3.0.0+] [[#GetAruid2|GetAruid2]]
|}
|}
== Reset ==
== Reset ==
No input. Returns an output u32 '''Err'''.
No input. Returns an output u32 '''Err'''.
== GetAruid2 ==
Unofficial name.
No input. Returns an output u64 '''Aruid''', an output bool '''IsCoreDumpEnabled''' and an output u32 '''Err'''.
= nvgem:cd =
= nvgem:cd =
| 2 || [1.0.0-8.1.0] [[#ReadNextBlock|ReadNextBlock]]
| 2 || [1.0.0-8.1.0] [[#ReadNextBlock|ReadNextBlock]]
|-
|-
| 3 || [8.0.0+]
| 3 || [8.0.0+] [[#GetNextBlockSize|GetNextBlockSize]]
|-
|-
| 4 || [8.0.0+]
| 4 || [8.0.0+] [[#ReadNextBlock2|ReadNextBlock2]]
|}
|}
== ReadNextBlock ==
== ReadNextBlock ==
Takes a type-0x6 output buffer. Returns an output u32 '''Err'''.
Takes a type-0x6 output buffer. Returns an output u32 '''Err'''.
== GetNextBlockSize ==
Unofficial name.
No input. Returns an output u64 '''Size''' and an output u32 '''Err'''.
== ReadNextBlock2 ==
Unofficial name.
Takes a type-0x6 output buffer and two input u64s '''Size''' and '''Offset'''. Returns an output u64 '''OutSize''' and an output u32 '''Err'''.
= nvdbg:d =
= nvdbg:d =
| 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]
| 0xC010001D || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT]]
|-
|-
| 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_SINGLE]]
| 0xC010001E || Inout || 16 || [[#NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX]]
|-
|-
| 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT]]
| 0xC004001F || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_ALLOC_EVENT]]
| 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH]]
| 0x40080021 || In || 8 || [[#NVHOST_IOCTL_CTRL_SYNCPT_FREE_EVENT_BATCH]]
|-
|-
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_MAX_EVENT_FIFO_CHANNEL]]
| 0xC0040022 || Inout || 4 || [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]
|}
|}
struct {
struct {
__in u32 id;
__in u32 id;
__in u32 lock; // (0==unlock; 1==lock)
__in u32 lock; // 0=unlock, 1=lock
};
};
struct {
struct {
__in u32 event_id; // 0x00 to 0x3F
__in u32 event_slot; // 0x00 to 0x3F
};
};
=== NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT ===
=== NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT ===
Waits on a syncpt using events. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to (((('''id''' & 0xFFF) << 0x10) | 0x10000000) | '''event_id''').
Waits on a syncpt using events. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to ('''event_slot''' | (('''syncpt_id''' & 0xFFF) << 16) | ('''is_valid''' << 28)).
struct {
struct {
};
};
=== NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_SINGLE ===
=== NVHOST_IOCTL_CTRL_SYNCPT_WAIT_EVENT_EX ===
Waits on a syncpt using a specific event. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to (('''id''' * 0x10) | '''event_id''').
Waits on a syncpt using a specific event. If waiting fails, returns error code 0x05 (Timeout) and sets '''value''' to ('''event_slot''' | ('''syncpt_id''' << 4)).
struct {
struct {
__in u32 thresh;
__in u32 thresh;
__in s32 timeout;
__in s32 timeout;
__inout u32 value; // in=event_id; out=syncpt_value
__inout u32 value; // in=event_slot; out=syncpt_value
};
};
struct {
struct {
__in u32 event_id; // 0x00 to 0x3F
__in u32 event_slot; // 0x00 to 0x3F
};
};
struct {
struct {
__in u32 event_id; // 0x00 to 0x3F
__in u32 event_slot; // 0x00 to 0x3F
};
};
struct {
struct {
__in u64 event_id_mask; // 64-bit bitfield where each bit represents one event
__in u64 event_slot_mask; // 64-bit bitfield where each bit represents one event
};
};
=== NVHOST_IOCTL_CTRL_SYNCPT_GET_MAX_EVENT_FIFO_CHANNEL ===
=== NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT ===
Returns the syncpt shift value.
struct {
struct {
__out u32 max_channel; // 0x00 (FIFO disabled) or 0x60 (FIFO enabled)
__out u32 syncpt_shift; // 0x00 (FIFO disabled) or 0x60 (FIFO enabled)
};
};
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND
| 0xC0040220 || Inout || 4 || NVDISP_CTRL_SUSPEND
|-
|-
| 0x80010224 || Out || 1 || [11.0.0+]
| 0x80010224 || Out || 1 || [11.0.0+] NVDISP_CTRL_IS_DISPLAY_OLED
|}
|}
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
| 0xC4C80203 || In || 1224 || NVDISP_FLIP
|-
|-
| 0x80380204 || Out || 56 || NVDISP_GET_MODE
| 0x80380204 || Out || 56 || [[#NVDISP_GET_MODE]]
|-
|-
| 0x40380205 || Out || 56 || NVDISP_SET_MODE
| 0x40380205 || In || 56 || [[#NVDISP_SET_MODE]]
|-
|-
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
| 0x430C0206 || In || 780 || NVDISP_SET_LUT
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
| 0x80040209 || Out || 4 || NVDISP_GET_HEAD_STATUS
|-
|-
| 0xC038020A || Inout || 56 || NVDISP_VALIDATE_MODE
| 0xC038020A || Inout || 56 || [[#NVDISP_VALIDATE_MODE]]
|-
|-
| 0x4018020B || In || 24 || NVDISP_SET_CSC
| 0x4018020B || In || 24 || NVDISP_SET_CSC
| 0xEBFC0215 || Inout || 11260 || NVDISP_GET_MODE_DB
| 0xEBFC0215 || Inout || 11260 || NVDISP_GET_MODE_DB
|-
|-
| 0xC003021A || Inout || 3 || NVDISP_PANEL_GET_VENDOR_ID
| 0xC003021A || Inout || 3 || [[#NVDISP_PANEL_GET_VENDOR_ID]]
|-
|-
| 0x803C021B || Out || 60 || NVDISP_GET_MODE2
| 0x803C021B || Out || 60 || NVDISP_GET_MODE2
| 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE]]
| 0x80080221 || Out || 8 || [10.0.0+] [[#NVDISP_GET_BACKLIGHT_RANGE]]
|-
|-
| 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT]]
| 0x40040222 || In || 4 || [10.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MAX]]
|-
|-
| 0x40040223 || In || 4 || [11.0.0+]
| 0x40040223 || In || 4 || [11.0.0+] [[#NVDISP_SET_BACKLIGHT_RANGE_MIN]]
|-
|-
| 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG]]
| 0x401C0225 || In || 28 || [11.0.0+] [[#NVDISP_SEND_PANEL_MSG]]
| 0xC01C0226 || Inout || 28 || [11.0.0+] [[#NVDISP_GET_PANEL_DATA]]
| 0xC01C0226 || Inout || 28 || [11.0.0+] [[#NVDISP_GET_PANEL_DATA]]
|}
|}
=== NVDISP_GET_MODE ===
Identical to Linux driver.
struct {
__out u32 hActive;
__out u32 vActive;
__out u32 hSyncWidth;
__out u32 vSyncWidth;
__out u32 hFrontPorch;
__out u32 vFrontPorch;
__out u32 hBackPorch;
__out u32 vBackPorch;
__out u32 hRefToSync;
__out u32 vRefToSync;
__out u32 pclkKHz;
__out u32 bitsPerPixel; // Always 0
__out u32 vmode; // Always 0
};
=== NVDISP_SET_MODE ===
Identical to Linux driver.
struct {
__in u32 hActive;
__in u32 vActive;
__in u32 hSyncWidth;
__in u32 vSyncWidth;
__in u32 hFrontPorch;
__in u32 vFrontPorch;
__in u32 hBackPorch;
__in u32 vBackPorch;
__in u32 hRefToSync;
__in u32 vRefToSync;
__in u32 pclkKHz;
__in u32 bitsPerPixel;
__in u32 vmode;
};
=== NVDISP_VALIDATE_MODE ===
Identical to Linux driver.
struct {
__inout u32 hActive;
__inout u32 vActive;
__inout u32 hSyncWidth;
__inout u32 vSyncWidth;
__inout u32 hFrontPorch;
__inout u32 vFrontPorch;
__inout u32 hBackPorch;
__inout u32 vBackPorch;
__inout u32 hRefToSync;
__inout u32 vRefToSync;
__inout u32 pclkKHz;
__inout u32 bitsPerPixel;
__inout u32 vmode;
};
=== NVDISP_PANEL_GET_VENDOR_ID ===
Returns display panel's informations.
struct {
__out u8 vendor; //0x10 - JDI, 0x20 - InnoLux, 0x30 - AUO, 0x40 - Sharp, 0x50 - Samsung
__out u8 model;
__out u8 board; //0xF - 6.2", 0x10 - 5.5", 0x20 - 7.0". JDI panels have nonstandard values
};
=== NVDISP_GET_BACKLIGHT_RANGE ===
=== NVDISP_GET_BACKLIGHT_RANGE ===
};
};
=== NVDISP_SET_BACKLIGHT ===
=== NVDISP_SET_BACKLIGHT_RANGE_MAX ===
Sets the value for the intensity of the display's backlight.
Sets the maximum value for the intensity of the display's backlight.
struct {
struct {
__in u32 val;
__in u32 max;
};
=== NVDISP_SET_BACKLIGHT_RANGE_MIN ===
Sets the minimum value for the intensity of the display's backlight.
struct {
__in u32 min;
};
};
struct {
struct {
__in u32 fence_id;
__in u32 fence_id;
__in u32 fence_thresh;
__in u32 fence_value;
__in u32 swap_interval;
__in u32 swap_interval;
};
};
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
| 0x40284109 || In || 40 || [[#NVGPU_AS_IOCTL_ALLOC_AS_EX]]
|-
|-
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MODIFY]]
| 0xC038410A || Inout || 56 || [[#NVGPU_AS_IOCTL_MAP_BUFFER_EX2]]
|-
|-
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
| 0xC0??4114 || Inout || Variable || [[#NVGPU_AS_IOCTL_REMAP]]
=== NVGPU_AS_IOCTL_MAP_BUFFER ===
=== NVGPU_AS_IOCTL_MAP_BUFFER ===
Maps a memory region in the device address space. Identical to Linux driver pretty much.
Maps a memory region in the device address space.
Unaligned size will cause a [[#Panic]].
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
struct {
struct {
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
u32 reserved;
u32 reserved0;
__in u32 dmabuf_fd; // nvmap handle
__in u32 mem_id; // nvmap handle
u32 reserved1;
union {
union {
__out u64 offset;
__out u64 offset;
struct {
struct {
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
__inout u32 kind; // -1 is default
__in u32 dmabuf_fd; // nvmap handle
__in u32 mem_id; // nvmap handle
u32 reserved;
__in u64 buffer_offset;
__in u64 buffer_offset;
__in u64 mapping_size;
__in u64 mapping_size;
union {
__out u64 offset;
__in u64 align;
};
};
};
=== NVGPU_AS_IOCTL_GET_VA_REGIONS ===
=== NVGPU_AS_IOCTL_GET_VA_REGIONS ===
Nintendo's custom implementation to get rid of pointer in struct.
Nintendo's custom implementation to get rid of pointer in struct.
Uses [[#Ioctl3|Ioctl3]].
struct va_region {
struct va_region {
};
};
=== NVGPU_AS_IOCTL_MODIFY ===
=== NVGPU_AS_IOCTL_MAP_BUFFER_EX2 ===
Maps a memory region in the device address space with extra params.
Unaligned size will cause a [[#Panic]].
On success, the mapped memory region is granted the [[SVC#MemoryAttribute|DeviceShared]] attribute.
struct {
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
__in u32 flags; // bit0: fixed_offset, bit2: cacheable
__inout u32 kind; // -1 is default
__in u32 dmabuf_fd; // nvmap handle
__in u32 mem_id; // nvmap handle
u32 reserved0;
__in u64 buffer_offset;
__in u64 buffer_offset;
__in u64 mapping_size;
__in u64 mapping_size;
union {
__in u64 unk0;
__out u64 offset;
__in u32 unk1;
__in u64 align;
u32 reserved;
};
__in u64 vma_addr;
__in u32 pages;
u32 reserved1;
};
};
struct remap_op {
struct remap_op {
__in u16 flags; // bit2: cacheable
__in u16 flags; // bit2: cacheable
__in u16 kind;
__in u16 kind;
__in u32 mem_handle;
__in u32 mem_handle;
__in u32 mem_offset_in_big_pages;
__in u32 mem_offset_in_pages;
__in u32 virt_offset_in_big_pages; // (alloc_space_offset >> 0x10)
__in u32 virt_offset_in_pages; // (alloc_space_offset >> 0x10)
__in u32 num_pages; // alloc_space_pages
__in u32 num_pages; // alloc_space_pages
};
};
| 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA
| 0xC018441A || Inout || 24 || NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA
|-
|-
| 0xC020441B || Inout || 32 || [11.0.0+]
| 0xC020441B || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_LAZY_ALLOC_RESERVED_PA_EX
|-
|-
| 0xC084441C || Inout || 132 || [11.0.0+]
| 0xC084441C || Inout || 132 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SETTINGS
|-
|-
| 0xC018441D || Inout || 24 || [11.0.0+]
| 0xC018441D || Inout || 24 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_SERIAL_NUMBER
|-
|-
| 0xC020441E || Inout || 32 || [11.0.0+]
| 0xC020441E || Inout || 32 || [11.0.0+] NVGPU_DBG_GPU_IOCTL_GET_GPU_VA_RANGE_PAGES
|}
|}
|-
|-
| /dev/nvhost-display || Display
| /dev/nvhost-display || Display
|-
| /dev/nvhost-tsec || TSEC
|}
|}
u32 syncpt_id;
u32 syncpt_id;
u32 syncpt_incrs;
u32 syncpt_incrs;
u32 reserved[3];
u32 id;
};
};
__in struct reloc_shift reloc_shifts[]; // depends on num_relocs
__in struct reloc_shift reloc_shifts[]; // depends on num_relocs
__in struct syncpt_incr syncpt_incrs[]; // depends on num_syncpt_incrs
__in struct syncpt_incr syncpt_incrs[]; // depends on num_syncpt_incrs
__out struct fence fences[]; // depends on num_fences
__out u32 fence_thresholds[]; // depends on num_fences
};
};
struct {
struct {
__in u32 num_entries;
__in u32 num_entries;
__in u32 flags;
__in u32 flags; // bit0: vpr_enabled
};
};
struct fence {
struct fence {
u32 id;
u32 id;
u32 thresh;
u32 value;
};
};
struct gpfifo_entry {
struct gpfifo_entry {
u32 entry0; // gpu_iova_lo
u32 entry1; // gpu_iova_hi | (allow_flush << 8) | (is_push_buf << 9) | (size << 10) | (sync << 31)
};
};
__in u64 gpfifo; // (ignored) pointer to gpfifo fence structs
__in u64 gpfifo; // (ignored) pointer to gpfifo fence structs
__in u32 num_entries; // number of fence objects being submitted
__in u32 num_entries; // number of fence objects being submitted
__in u32 flags;
union {
__out u32 detailed_error;
__in u32 flags; // bit0: fence_wait, bit1: fence_get, bit2: hw_format, bit3: sync_fence, bit4: suppress_wfi, bit5: skip_buffer_refcounting
};
__inout struct fence fence_out; // returned new fence object for others to wait on
__inout struct fence fence_out; // returned new fence object for others to wait on
__in struct gpfifo_entry entries[]; // depends on num_entries
__in struct gpfifo_entry entries[]; // depends on num_entries
struct {
struct {
__out u32 error_info[32]; // first word is an error code (0=no_error, 1=gr_error, 2=gr_error, 3=invalid, 4=invalid)
__out u32 type; // Error type (0=no_error, 1=mmu_error, 2=gr_error, 3=pbdma_error, 4=timeout)
};
__out u32 info[31]; // Infor depends on the error type
};
==== GR Error Code Format ====
When <code>type == 2</code> (GR Error), the returned data is formatted as follows:
struct {
__out u32 type; // 2=gr_error
__out u32 intr_value; // Interrupt bits
__out u32 addr; // Register address (in bytes)
__out u32 data_hi; // Data high 32 bits
__out u32 data_lo; // Data low 32 bits
__out u32 class_num; // GPU class number (e.g., 0xb197 for MAXWELL_B)
};
{| class="wikitable"
|+ GR Error Interrupt Bits
|-
! Bit(s)
! Description
|-
| 0
| GR_INTR_NOTIFY
|-
| 1
| GR_INTR_SEMAPHORE
|-
| 2
| unknown
|-
| 3
| unknown
|-
| 4
| GR_INTR_ILLEGAL_METHOD
|-
| 5
| GR_INTR_ILLEGAL_CLASS
|-
| 6
| GR_INTR_ILLEGAL_NOTIFY
|-
| 7
| unknown
|-
| 8
| GR_INTR_FIRMWARE_METHOD
|-
| 9–18
| unknown
|-
| 19
| GR_INTR_FECS_ERROR
|-
| 20
| GR_INTR_CLASS_ERROR
|-
| 21
| GR_INTR_EXCEPTION
|-
| 22–31
| unknown
|}
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
=== NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===
struct fence {
struct fence {
u32 id;
u32 id;
u32 thresh;
u32 value;
};
};
__in u32 num_entries;
__in u32 num_entries;
__in u32 num_jobs;
__in u32 num_jobs;
__in u32 flags;
__in u32 flags; // bit0: vpr_enabled
__out struct fence fence_out; // returned new fence object for others to wait on
__out struct fence fence_out; // returned new fence object for others to wait on
__in u32 reserved[3]; // ignored
__in u32 reserved[3]; // ignored
| 13
| 13
|
|
|
| Can use the GPU virtual address range 0xC0000 to 0x580000 instead of 0x0 to 0xC0000.
|-
|-
| 14
| 14
| 15
| 15
|
|
|
| Can use the virtual address ranges 0x0 to 0x100000000 (GPU) and 0x0 to 0xE0000000 (non-GPU) instead of 0x100000000 to 0x11FA50000 (GPU) and 0xE0000000 to 0xFFFE0000 (non-GPU).
|}
|}
When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done.
When the gpfifo data in the gpu_va buffers specified by the submitted gpfifo entries is invalid(?), eventually the user-process will be force-terminated after using the submit-gpfifo ioctl. It's unknown how exactly this is done.
GPU rendering (GPFIFO) is only used by applets/Applications. All sysmodules doing any gfx-display uses software rendering. During system-boot, GPU GPFIFO is not used until the applets are launched.
[[Category:Services]]
[[Category:Services]]