NV services: Difference between revisions

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    struct {
-     __out u32 error_info[32];    // first word is an error code (0=no_error, 1=mmu_error, 2=gr_error, 3=pbdma_error, 4=timeout)
+     __out u32 type;     // Error type (0=no_error, 1=mmu_error, 2=gr_error, 3=pbdma_error, 4=timeout)
-   };
+    __out u32 info[31]; // Infor depends on the error type
+   };
+==== GR Error Code Format ====
+When <code>type == 2</code> (GR Error), the returned data is formatted as follows:
+  struct {
+    __out u32 type;       // 2=gr_error
+    __out u32 intr_value; // Interrupt bits
+    __out u32 addr;       // Register address (in bytes)
+    __out u32 data_hi;    // Data high 32 bits
+    __out u32 data_lo;    // Data low 32 bits
+    __out u32 class_num;  // GPU class number (e.g., 0xb197 for MAXWELL_B)
+  };
+{| class="wikitable"
+|+ GR Error Interrupt Bits
+|-
+! Bit(s)
+! Description
+|-
+| 0
+| GR_INTR_NOTIFY
+|-
+| 1
+| GR_INTR_SEMAPHORE
+|-
+| 2
+| unknown
+|-
+| 3
+| unknown
+|-
+| 4
+| GR_INTR_ILLEGAL_METHOD
+|-
+| 5
+| GR_INTR_ILLEGAL_CLASS
+|-
+| 6
+| GR_INTR_ILLEGAL_NOTIFY
+|-
+| 7
+| unknown
+|-
+| 8
+| GR_INTR_FIRMWARE_METHOD
+|-
+| 9–18
+| unknown
+|-
+| 19
+| GR_INTR_FECS_ERROR
+|-
+| 20
+| GR_INTR_CLASS_ERROR
+|-
+| 21
+| GR_INTR_EXCEPTION
+|-
+| 22–31
+| unknown
+|}
 === NVGPU_IOCTL_CHANNEL_GET_ERROR_NOTIFICATION ===