Difference between revisions of "Tegra X1"
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* Storage interface e-MMC 5.1 (HS533), CMD Queuing | * Storage interface e-MMC 5.1 (HS533), CMD Queuing | ||
| − | + | Tegra X1 TRM datasheet | |
| − | * | + | * https://developer.nvidia.com/embedded/downloads#?search=X1 (2977 pages, requires free Nvidia developer account) |
Latest revision as of 01:03, 6 March 2024
NVIDIA Tegra X1 SoC Specifications
CPU
- Quad 64-bit A57 cores + Quad 64-bit A53 cores
Cache
- Cortex A57 cluster: 2 MB Shared L2 Cache, 48KB /32KB (I/D) L1 Cache per core
- Cortex A53 cluster: 512KB shared L2 Cache, 32KB/32KB (I/D) L1 Cache per core
Memory Frequency
- LPDDR3, LPDDR4-1600, 64-bit (25.6 GB/s)
Memory Size
- Up to 4 GB
GPU
- Cores 256-core Maxwell GPU with support for FP16
- API Support OpenGL ES 3.1, OpenGL4.5, DirectX 12.0, AEP, CUDA 6.0
Video
- Decode VP9, H.265, H.264 4K 60 fps; H.265 4K 60fps 10-bit color; VP8 1080p 60fps;
- Encode H.264, H.265 4K 30 fps; VP8 1080p 60 fps;
Imaging
- Image Processing Dual ISP, 1.3 GigaPixels/s, 4096 focus points, 100 MP Sensor support, up to 6 camera inputs
- JPEG Decode/Encode 600 MPixels/s
Display
- Display Controllers 2 Simultaneous
- HDMI HDMI 2.0, HDCP 2.2, 4K 60 fps
- Local Display 4K 60 fps VESA DSC compression
Storage
- Storage interface e-MMC 5.1 (HS533), CMD Queuing
Tegra X1 TRM datasheet
- https://developer.nvidia.com/embedded/downloads#?search=X1 (2977 pages, requires free Nvidia developer account)