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| [[#TSEC_THI_CONT_SYNCPT_L1|TSEC_THI_CONT_SYNCPT_L1]]
| [[#TSEC_THI_CONT_SYNCPT_L1|TSEC_THI_CONT_SYNCPT_L1]]
| 0x5450002C
| 0x5450002C
| 0x04
|-
| [[#TSEC_THI_STREAMID0|TSEC_THI_STREAMID0]]
| 0x54500030
| 0x04
|-
| [[#TSEC_THI_STREAMID1|TSEC_THI_STREAMID1]]
| 0x54500034
| 0x04
|-
| [[#TSEC_THI_THI_SEC|TSEC_THI_THI_SEC]]
| 0x54500038
| 0x04
| 0x04
|-
|-
Line 307: Line 295:
| 0x04
| 0x04
|-
|-
| TSEC_FALCON_UNK_E0
| [[#TSEC_FALCON_SIRQMASK|TSEC_FALCON_SIRQMASK]]
| 0x545010E0
| 0x545010E0
| 0x04
| 0x04
Line 547: Line 535:
| 0x04
| 0x04
|-
|-
| [[#TSEC_FALCON_SSTAT|TSEC_FALCON_SSTAT]]
| [[#TSEC_FALCON_SERRSTAT|TSEC_FALCON_SERRSTAT]]
| 0x54501244
| 0x54501244
| 0x04
| 0x04
|-
|-
| TSEC_FALCON_UNK_250
| [[#TSEC_FALCON_SERRVAL|TSEC_FALCON_SERRVAL]]
| 0x54501248
| 0x04
|-
| [[#TSEC_FALCON_SERRADDR|TSEC_FALCON_SERRADDR]]
| 0x5450124C
| 0x04
|-
| [[#TSEC_FALCON_SCTL1|TSEC_FALCON_SCTL1]]
| 0x54501250
| 0x54501250
| 0x04
| 0x04
|-
|-
| TSEC_FALCON_UNK_260
| [[#TSEC_FALCON_STEST|TSEC_FALCON_STEST]]
| 0x54501258
| 0x04
|-
| [[#TSEC_FALCON_SICD|TSEC_FALCON_SICD]]
| 0x54501260
| 0x54501260
| 0x04
| 0x04
Line 809: Line 809:
| [[#TSEC_TFBIF_DBG_R128COUNT|TSEC_TFBIF_DBG_R128COUNT]]
| [[#TSEC_TFBIF_DBG_R128COUNT|TSEC_TFBIF_DBG_R128COUNT]]
| 0x5450162C
| 0x5450162C
| 0x04
|-
| TSEC_TFBIF_UNK_30
| 0x54501630
| 0x04
| 0x04
|-
|-
| [[#TSEC_TFBIF_MCCIF_FIFOCTRL1|TSEC_TFBIF_MCCIF_FIFOCTRL1]]
| [[#TSEC_TFBIF_MCCIF_FIFOCTRL1|TSEC_TFBIF_MCCIF_FIFOCTRL1]]
| 0x54501634
| 0x54501634
| 0x04
|-
| [[#TSEC_TFBIF_WRR_RDP|TSEC_TFBIF_WRR_RDP]]
| 0x54501638
| 0x04
| 0x04
|-
|-
Line 833: Line 825:
| [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]]
| [[#TSEC_TFBIF_REGIONCFG|TSEC_TFBIF_REGIONCFG]]
| 0x54501648
| 0x54501648
| 0x04
|-
| [[#TSEC_TFBIF_ACTMON_ACTIVE_MASK|TSEC_TFBIF_ACTMON_ACTIVE_MASK]]
| 0x5450164C
| 0x04
|-
| [[#TSEC_TFBIF_ACTMON_ACTIVE_BORPS|TSEC_TFBIF_ACTMON_ACTIVE_BORPS]]
| 0x54501650
| 0x04
|-
| [[#TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT|TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT]]
| 0x54501654
| 0x04
|-
| [[#TSEC_TFBIF_ACTMON_MCB_MASK|TSEC_TFBIF_ACTMON_MCB_MASK]]
| 0x54501660
| 0x04
|-
| [[#TSEC_TFBIF_ACTMON_MCB_BORPS|TSEC_TFBIF_ACTMON_MCB_BORPS]]
| 0x54501664
| 0x04
|-
| [[#TSEC_TFBIF_ACTMON_MCB_WEIGHT|TSEC_TFBIF_ACTMON_MCB_WEIGHT]]
| 0x54501668
| 0x04
|-
| [[#TSEC_TFBIF_THI_TRANSPROP|TSEC_TFBIF_THI_TRANSPROP]]
| 0x54501670
| 0x04
| 0x04
|-
|-
Line 883: Line 847:
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_00
| [[#TSEC_VERSION|TSEC_VERSION]]
| 0x54501800
| 0x54501800
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_04
| [[#TSEC_SCRATCH0|TSEC_SCRATCH0]]
| 0x54501804
| 0x54501804
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_08
| [[#TSEC_SCRATCH1|TSEC_SCRATCH1]]
| 0x54501808
| 0x54501808
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_0C
| [[#TSEC_SCRATCH2|TSEC_SCRATCH2]]
| 0x5450180C
| 0x5450180C
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_10
| [[#TSEC_SCRATCH3|TSEC_SCRATCH3]]
| 0x54501810
| 0x54501810
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_14
| [[#TSEC_SCRATCH4|TSEC_SCRATCH4]]
| 0x54501814
| 0x54501814
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_18
| [[#TSEC_SCRATCH5|TSEC_SCRATCH5]]
| 0x54501818
| 0x54501818
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_1C
| [[#TSEC_SCRATCH6|TSEC_SCRATCH6]]
| 0x5450181C
| 0x5450181C
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_20
| [[#TSEC_SCRATCH7|TSEC_SCRATCH7]]
| 0x54501820
| 0x54501820
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_24
| [[#TSEC_GPTMRINT|TSEC_GPTMRINT]]
| 0x54501824
| 0x54501824
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_28
| [[#TSEC_GPTMRVAL|TSEC_GPTMRVAL]]
| 0x54501828
| 0x54501828
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_2C
| [[#TSEC_GPTMRCTL|TSEC_GPTMRCTL]]
| 0x5450182C
| 0x5450182C
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_30
| [[#TSEC_ITFEN|TSEC_ITFEN]]
| 0x54501830
| 0x54501830
| 0x04
| 0x04
|-
|-
| TSEC_TEGRA_UNK_34
| [[#TSEC_ITFSTAT|TSEC_ITFSTAT]]
| 0x54501834
| 0x54501834
| 0x04
| 0x04
Line 1,079: Line 1,043:
|}
|}


=== TSEC_THI_STREAMID0 ===
=== TSEC_THI_METHOD0 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-6
| 0-11
| TSEC_THI_STREAMID0_ID
| TSEC_THI_METHOD0_OFFSET
|}
|}


=== TSEC_THI_STREAMID1 ===
Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-6
| TSEC_THI_STREAMID1_ID
|}


=== TSEC_THI_THI_SEC ===
The following methods are available:
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  ID
!  Description
!  Method
|-
|-
| 0
| 0x100
| TSEC_THI_THI_SEC_TZ_LOCK
|-
| 4
| TSEC_THI_THI_SEC_TZ_AUTH
|-
| 8
| TSEC_THI_THI_SEC_CH_LOCK
|}
 
=== TSEC_THI_METHOD0 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-11
| TSEC_THI_METHOD0_OFFSET
|}
 
Used to encode and send a method's ID over HOST1X to TSEC. This register mirrors the functionality of HOST1X's channel opcode submission.
 
The following methods are available:
{| class="wikitable" border="1"
!  ID
!  Method
|-
| 0x100
| NOP
| NOP
|-
|-
Line 2,058: Line 1,989:
| 16
| 16
| TSEC_FALCON_DEBUG1_CTXSW_MODE
| TSEC_FALCON_DEBUG1_CTXSW_MODE
|-
| 17
| TSEC_FALCON_DEBUG1_TRACE_FORMAT
|}
|}


Line 2,341: Line 2,269:
=== TSEC_FALCON_RSTAT3 ===
=== TSEC_FALCON_RSTAT3 ===
Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 3]].
Mirror of the [[#TSEC_FALCON_ICD_RDATA|ICD status register 3]].
=== TSEC_FALCON_SIRQMASK ===
Unofficial name.
Same as [[#TSEC_FALCON_IRQMASK|TSEC_FALCON_IRQMASK]], but for LS mode.


=== TSEC_FALCON_CPUCTL ===
=== TSEC_FALCON_CPUCTL ===
Line 3,312: Line 3,245:
|-
|-
| 4-5
| 4-5
| Current access level
|-
| 8-9
| Unknown access level
|-
| 12
| Unknown
| Unknown
|-
|-
| 12-13
| 13
| Unknown
| Unknown
|-
|-
Line 3,321: Line 3,260:
|}
|}


=== TSEC_FALCON_SSTAT ===
=== TSEC_FALCON_SERRSTAT ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
| 0-23
| Unknown
|-
|-
| 30
| 30
Line 3,333: Line 3,275:
|}
|}


=== TSEC_FALCON_SPROT_IMEM ===
Unofficial name.
 
Used for detecting invalid CSB accesses in LS mode.
 
=== TSEC_FALCON_SERRVAL ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-3
| 0-31
| Read access level
| Error code
|-
| 4-7
| Write access level
|}
|}


Controls accesses to Falcon IMEM.
Unofficial name.


=== TSEC_FALCON_SPROT_DMEM ===
=== TSEC_FALCON_SERRADDR ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-3
| 0-31
| Read access level
| Error address
|-
| 4-7
| Write access level
|}
|}


Controls accesses to Falcon DMEM.
Unofficial name.


=== TSEC_FALCON_SPROT_CPUCTL ===
=== TSEC_FALCON_SCTL1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-3
| 0-1
| Read access level
| CSB access level
|-
|-
| 4-7
| 2-3
| Write access level
| Unknown access level
|}
|}


Controls accesses to the [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]] register.
Unofficial name.


=== TSEC_FALCON_SPROT_MISC ===
=== TSEC_FALCON_STEST ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-3
| 0-31
| Read access level
| Unknown
|-
| 4-7
| Write access level
|}
|}


Controls accesses to the following registers:
Unofficial name.
* [[#TSEC_FALCON_PRIVSTATE|TSEC_FALCON_PRIVSTATE]]
* [[#TSEC_FALCON_SFTRESET|TSEC_FALCON_SFTRESET]]
* [[#TSEC_FALCON_ADDR|TSEC_FALCON_ADDR]]
* [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]]
* [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]]
* [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]]
* TSEC_FALCON_UNK_250
* [[#TSEC_FALCON_DMAINFO_CTL|TSEC_FALCON_DMAINFO_CTL]]


=== TSEC_FALCON_SPROT_IRQ ===
=== TSEC_FALCON_SICD ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-3
| 0
| Read access level
| Enable access to ICD command STOP
|-
| 1
| Enable access to ICD command RUN
|-
| 2
| Enable access to ICD command RUNB
|-
|-
| 4-7
| 3
| Write access level
| Enable access to ICD command STEP
|}
|-
 
| 4
Controls accesses to the following registers:
| Enable access to ICD command EMASK
* [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]]
|-
* [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]]
| 5
* [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]]
| Enable access to ICD command RREG (only for SPRs)
* [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]]
|-
* [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]]
| 6
* [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]]
| Enable access to ICD command RSTAT
* [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]]
|-
* [[#TSEC_FALCON_IRQDEST2|TSEC_FALCON_IRQDEST2]]
| 7
* TSEC_FALCON_UNK_E0
| Enable access to IBRKPT registers
 
=== TSEC_FALCON_SPROT_MTHD ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0-3
| 8
| Read access level
| Enable access to ICD command RREG (only for GPRs)
|-
|-
| 4-7
| 9
| Write access level
| Enable access to ICD command RDM
|}
|}


Controls accesses to the following registers:
Unofficial name.
* [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]]
 
* [[#TSEC_FALCON_CURCTX|TSEC_FALCON_CURCTX]]
Controls access to the ICD in LS mode.
* [[#TSEC_FALCON_NXTCTX|TSEC_FALCON_NXTCTX]]
* [[#TSEC_FALCON_CTXACK|TSEC_FALCON_CTXACK]]
* [[#TSEC_FALCON_MTHDDATA|TSEC_FALCON_MTHDDATA]]
* [[#TSEC_FALCON_MTHDID|TSEC_FALCON_MTHDID]]
* [[#TSEC_FALCON_MTHDWDAT|TSEC_FALCON_MTHDWDAT]]
* [[#TSEC_FALCON_MTHDCOUNT|TSEC_FALCON_MTHDCOUNT]]
* [[#TSEC_FALCON_MTHDPOP|TSEC_FALCON_MTHDPOP]]
* [[#TSEC_FALCON_MTHDRAMSZ|TSEC_FALCON_MTHDRAMSZ]]
* [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]]


=== TSEC_FALCON_SPROT_SCTL ===
=== TSEC_FALCON_SPROT_IMEM ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-3
| 0-2
| Read access level
| Read access level
|-
|-
| 4-7
| 3
| Set on memory read access violation
|-
| 4-6
| Write access level
| Write access level
|-
| 7
| Set on memory write access violation
|}
|}


Controls accesses to the [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]] register.
Unofficial name.
 
Controls accesses to Falcon IMEM.


=== TSEC_FALCON_SPROT_WDTMR ===
=== TSEC_FALCON_SPROT_DMEM ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-3
| 0-2
| Read access level
| Read access level
|-
|-
| 4-7
| 3
| Set on memory read access violation
|-
| 4-6
| Write access level
| Write access level
|-
| 7
| Set on memory write access violation
|}
|}


Controls accesses to the following registers:
Unofficial name.
* [[#TSEC_FALCON_WDTMRVAL|TSEC_FALCON_WDTMRVAL]]
 
* [[#TSEC_FALCON_WDTMRCTL|TSEC_FALCON_WDTMRCTL]]
Controls accesses to Falcon DMEM.


=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW ===
=== TSEC_FALCON_SPROT_CPUCTL ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-31
| 0-2
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL
| Read access level
|-
| 3
| Set on memory read access violation
|-
| 4-6
| Write access level
|-
| 7
| Set on memory write access violation
|}
|}


=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH ===
Unofficial name.
 
Controls accesses to the [[#TSEC_FALCON_CPUCTL|TSEC_FALCON_CPUCTL]] register.
 
=== TSEC_FALCON_SPROT_MISC ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-30
| 0-2
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL
| Read access level
|-
|-
| 31
| 3
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT
| Set on memory read access violation
|-
| 4-6
| Write access level
|-
| 7
| Set on memory write access violation
|}
|}


=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW ===
Unofficial name.
 
Controls accesses to the following registers:
* [[#TSEC_FALCON_PRIVSTATE|TSEC_FALCON_PRIVSTATE]]
* [[#TSEC_FALCON_SFTRESET|TSEC_FALCON_SFTRESET]]
* [[#TSEC_FALCON_ADDR|TSEC_FALCON_ADDR]]
* [[#TSEC_FALCON_DMACTL|TSEC_FALCON_DMACTL]]
* [[#TSEC_FALCON_IMCTL|TSEC_FALCON_IMCTL]]
* [[#TSEC_FALCON_IMSTAT|TSEC_FALCON_IMSTAT]]
* [[#TSEC_FALCON_SCTL1|TSEC_FALCON_SCTL1]]
* [[#TSEC_FALCON_DMAINFO_CTL|TSEC_FALCON_DMAINFO_CTL]]
 
=== TSEC_FALCON_SPROT_IRQ ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-31
| 0-2
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL
| Read access level
|-
| 3
| Set on memory read access violation
|-
| 4-6
| Write access level
|-
| 7
| Set on memory write access violation
|}
|}


=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH ===
Unofficial name.
 
Controls accesses to the following registers:
* [[#TSEC_FALCON_IRQMODE|TSEC_FALCON_IRQMODE]]
* [[#TSEC_FALCON_IRQMSET|TSEC_FALCON_IRQMSET]]
* [[#TSEC_FALCON_IRQMCLR|TSEC_FALCON_IRQMCLR]]
* [[#TSEC_FALCON_IRQDEST|TSEC_FALCON_IRQDEST]]
* [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]]
* [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]]
* [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]]
* [[#TSEC_FALCON_IRQDEST2|TSEC_FALCON_IRQDEST2]]
* [[#TSEC_FALCON_SIRQMASK|TSEC_FALCON_SIRQMASK]]
 
=== TSEC_FALCON_SPROT_MTHD ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-30
| 0-2
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL
| Read access level
|-
|-
| 31
| 3
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT
| Set on memory read access violation
|-
| 4-6
| Write access level
|-
| 7
| Set on memory write access violation
|}
|}


=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW ===
Unofficial name.
 
Controls accesses to the following registers:
* [[#TSEC_FALCON_ITFEN|TSEC_FALCON_ITFEN]]
* [[#TSEC_FALCON_CURCTX|TSEC_FALCON_CURCTX]]
* [[#TSEC_FALCON_NXTCTX|TSEC_FALCON_NXTCTX]]
* [[#TSEC_FALCON_CTXACK|TSEC_FALCON_CTXACK]]
* [[#TSEC_FALCON_MTHDDATA|TSEC_FALCON_MTHDDATA]]
* [[#TSEC_FALCON_MTHDID|TSEC_FALCON_MTHDID]]
* [[#TSEC_FALCON_MTHDWDAT|TSEC_FALCON_MTHDWDAT]]
* [[#TSEC_FALCON_MTHDCOUNT|TSEC_FALCON_MTHDCOUNT]]
* [[#TSEC_FALCON_MTHDPOP|TSEC_FALCON_MTHDPOP]]
* [[#TSEC_FALCON_MTHDRAMSZ|TSEC_FALCON_MTHDRAMSZ]]
* [[#TSEC_FALCON_DEBUG1|TSEC_FALCON_DEBUG1]]
 
=== TSEC_FALCON_SPROT_SCTL ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-31
| 0-2
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL
| Read access level
|-
| 3
| Set on memory read access violation
|-
| 4-6
| Write access level
|-
| 7
| Set on memory write access violation
|}
|}


=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH ===
Unofficial name.
 
Controls accesses to the [[#TSEC_FALCON_SCTL|TSEC_FALCON_SCTL]] register.
 
=== TSEC_FALCON_SPROT_WDTMR ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-30
| 0-2
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL
| Read access level
|-
|-
| 31
| 3
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT
| Set on memory read access violation
|-
| 4-6
| Write access level
|-
| 7
| Set on memory write access violation
|}
|}


=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW ===
Unofficial name.
 
Controls accesses to the following registers:
* [[#TSEC_FALCON_WDTMRVAL|TSEC_FALCON_WDTMRVAL]]
* [[#TSEC_FALCON_WDTMRCTL|TSEC_FALCON_WDTMRCTL]]
 
=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 3,544: Line 3,578:
|-
|-
| 0-31
| 0-31
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL
|}
|}


=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH ===
=== TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 3,553: Line 3,587:
|-
|-
| 0-30
| 0-30
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL
|-
|-
| 31
| 31
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT
| TSEC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT
|}
|}


=== TSEC_FALCON_DMAINFO_CTL ===
=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 0-31
| TSEC_FALCON_DMAINFO_CTL_CLR_FBRD
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL
|-
| 1
| TSEC_FALCON_DMAINFO_CTL_CLR_FBWR
|}
|}


=== TSEC_SCP_CTL0 ===
=== TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 10
| 0-30
| Enable [[#LOAD|Falcon<->LOAD]] interface
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL
|-
|-
| 12
| 31
| Enable [[#STORE|Falcon<->STORE]] interface
| TSEC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT
|}
 
=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 14
| 0-31
| Enable [[#CMD|Falcon<->CMD]] interface
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL
|-
| 16
| Enable [[#SEQ|SEQ]]
|-
| 20
| Enable [[#CTL|CTL]]
|}
|}


=== TSEC_SCP_CTL1 ===
=== TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 0-30
| Clear [[#SEQ|SEQ]]
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL
|-
|-
| 8
| 31
| Clear [[#SCP|SCP]]'s internal pipeline
| TSEC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT
|-
| 11
| Enable [[#RNG|RNG]]'s test mode
|-
| 12
| Enable [[#RNG|RNG]]
|-
| 16
| Enable [[#LOAD|Falcon<->LOAD]] interface's dummy mode (all reads return 0)
|-
| 20
| Enable [[#LOAD|Falcon<->LOAD]] interface bypassing (all reads are dropped)
|-
| 24
| Enable [[#STORE|Falcon<->STORE]] interface bypassing (all writes are dropped)
|}
|}


=== TSEC_SCP_CTL_STAT ===
=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 20
| 0-31
| TSEC_SCP_CTL_STAT_DEBUG_MODE
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL
|}
|}


=== TSEC_SCP_CTL_LOCK ===
=== TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 0-30
| Enable lockdown mode (locks IMEM and DMEM)
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL
|-
|-
| 4
| 31
| Lock [[#SCP|SCP]]'s MMIO register space
| TSEC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT
|}
|}


Controls lockdown mode and can only be cleared in Heavy Secure mode.
=== TSEC_FALCON_DMAINFO_CTL ===
 
=== TSEC_SCP_CFG ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 3,648: Line 3,662:
|-
|-
| 0
| 0
| Endianness for ADD
| TSEC_FALCON_DMAINFO_CTL_CLR_FBRD
0: Little
1: Big
|-
|-
| 1
| 1
| Endianness for GFMUL
| TSEC_FALCON_DMAINFO_CTL_CLR_FBWR
0: Little
1: Big
|-
| 2
| Endianness for [[#LOAD|LOAD]]
0: Little
1: Big
|-
| 3
| Endianness for [[#STORE|STORE]]
0: Little
1: Big
|-
| 4
| Endianness for [[#AES|AES]]
0: Little
1: Big
|-
| 8
| Flush [[#CMD|CMD]]
|-
| 12-13
| Carry chain's size
0: 32 bits
1: 64 bits
2: 96 bits
3: 128 bits
|-
| 16-31
| [[#SCP|SCP]]'s internal pipeline stall timeout value
|}
|}


=== TSEC_SCP_CTL_SCP ===
=== TSEC_SCP_CTL0 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 10
| Swap [[#SCP|SCP]]'s master
| Enable [[#LOAD|Falcon<->LOAD]] interface
|-
| 12
| Enable [[#STORE|Falcon<->STORE]] interface
|-
| 14
| Enable [[#CMD|Falcon<->CMD]] interface
|-
| 16
| Enable [[#SEQ|SEQ]]
|-
|-
| 1
| 20
| Current [[#SCP|SCP]]'s master
| Enable [[#CTL|CTL]]
0: Falcon
1: External
|}
|}


=== TSEC_SCP_CTL_PKEY ===
Unofficial name.
 
=== TSEC_SCP_CTL1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 3,706: Line 3,697:
|-
|-
| 0
| 0
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
| Clear [[#SEQ|SEQ]]
|-
| 8
| Clear [[#SCP|SCP]]'s internal pipeline
|-
| 11
| Enable [[#RNG|RNG]]'s test mode
|-
| 12
| Enable [[#RNG|RNG]]
|-
| 16
| Enable [[#LOAD|Falcon<->LOAD]] interface's dummy mode (all reads return 0)
|-
| 20
| Enable [[#LOAD|Falcon<->LOAD]] interface bypassing (all reads are dropped)
|-
|-
| 1
| 24
| TSEC_SCP_CTL_PKEY_LOADED
| Enable [[#STORE|Falcon<->STORE]] interface bypassing (all writes are dropped)
|}
|}


=== TSEC_SCP_CTL_DBG ===
Unofficial name.
 
=== TSEC_SCP_CTL_STAT ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 20
| TSEC_SCP_CTL_STAT_DEBUG_MODE
|}
 
=== TSEC_SCP_CTL_LOCK ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 3,718: Line 3,735:
|-
|-
| 0
| 0
| Unknown
| Enable lockdown mode (locks IMEM and DMEM)
|-
| 1
| Lockdown has pending exit request
|-
| 2
| Lockdown has been enabled before
|-
|-
| 4
| 4
| Unknown
| Enable SCP lockdown mode (locks [[#SCP|SCP]]'s MMIO register space)
|-
|-
| 8
| 6
| Unknown
| SCP lockdown has been enabled before
|-
| 12
| Unknown
|}
|}


=== TSEC_SCP_DBG0 ===
Unofficial name.
 
Controls lockdown mode. Can only be cleared in HS mode.
 
=== TSEC_SCP_CFG ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-3
| 0
| Index
| Endianness for ADD
0: Little
1: Big
|-
| 1
| Endianness for GFMUL
0: Little
1: Big
|-
|-
| 4
| 2
| Auto-increment
| Endianness for [[#LOAD|LOAD]]
0: Little
1: Big
|-
|-
| 5-6
| 3
| Target
| Endianness for [[#STORE|STORE]]
  0: None
  0: Little
  1: STORE
  1: Big
2: LOAD
3: SEQ
|-
|-
| 8-12
| 4
| [[#SEQ|SEQ]]'s current sequence's size
| Endianness for [[#AES|AES]]
0: Little
1: Big
|-
|-
| 13-16
| 8
| [[#SEQ|SEQ]]'s current instruction's address
| Flush [[#CMD|CMD]]
|-
|-
| 17
| 12-13
| [[#SEQ|SEQ]]'s current instruction is valid
| Carry chain's size
0: 32 bits
1: 64 bits
2: 96 bits
3: 128 bits
|-
|-
| 18
| 16-31
| [[#SEQ|SEQ]] is running in HS mode
| [[#SCP|SCP]]'s internal pipeline stall timeout value
|}
 
Unofficial name.
 
=== TSEC_SCP_CTL_SCP ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 19-22
| 0
| [[#LOAD|LOAD]]'s queue's size
| Swap [[#SCP|SCP]]'s master
|-
|-
| 23
| 1
| [[#LOAD|LOAD]]'s current operation is valid
| Current [[#SCP|SCP]]'s master
|-
0: Falcon
| 24
1: External
| [[#LOAD|LOAD]] is running in HS mode
|-
| 25-26
| [[#STORE|STORE]]'s queue's size
|-
| 30
| [[#STORE|STORE]]'s current operation is valid
|-
| 31
| [[#STORE|STORE]] is running in HS mode
|}
|}


Used for debugging the [[#LOAD|LOAD]], [[#STORE|STORE]] and [[#SEQ|SEQ]] blocks.
Unofficial name.


=== TSEC_SCP_DBG1 ===
=== TSEC_SCP_CTL_PKEY ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-31
| 0
| Data
| TSEC_SCP_CTL_PKEY_REQUEST_RELOAD
If target is SEQ:
|-
  Bits 0-3: current instruction's first operand
| 1
  Bits 4-9: current instruction's second operand
| TSEC_SCP_CTL_PKEY_LOADED
  Bits 10-14: current instruction's opcode
|}
|}


Used for retrieving debug data. Contains information on the last crypto sequence created when debugging the [[#SEQ|SEQ]] block.
=== TSEC_SCP_CTL_DBG ===
 
=== TSEC_SCP_DBG2 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-1
| 4
| [[#SEQ|SEQ]]'s state
| Disable lockdown mode
0: Idle
1: Recording (cs0begin/cs1begin)
2: Executing (cs0exec/cs1exec)
|-
|-
| 4-7
| 8
| Number of cycles left for [[#SEQ|SEQ]]'s current sequence
| Disable SCP lockdown mode
|-
| 12-15
| Active crypto key register (ckeyreg)
|}
|}


Used for retrieving additional debug data associated with the [[#SEQ|SEQ]] block.
Unofficial name.
 
Overrides lockdown mode. Can only be set in debug mode.


=== TSEC_SCP_CMD ===
=== TSEC_SCP_DBG0 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 3,822: Line 3,850:
|-
|-
| 0-3
| 0-3
| Destination register
| Index
|-
|-
| 8-13
| 4
| Source register or immediate value
| Auto-increment
|-
|-
| 20-24
| 5-6
| Command opcode
| Target
  0x0: nop (fuc5 opcode 0x00)
  0: None
0x1:  cmov (fuc5 opcode 0x84)
  1: STORE
0x2:  cxsin (fuc5 opcode 0x88) or xdst (with cxset)
  2: LOAD
0x3:  cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
  3: SEQ
0x4:  crnd (fuc5 opcode 0x90)
0x5:  cs0begin (fuc5 opcode 0x94)
0x6:  cs0exec (fuc5 opcode 0x98)
0x7:  cs1begin (fuc5 opcode 0x9C)
0x8:  cs1exec (fuc5 opcode 0xA0)
0x9:  invalid (fuc5 opcode 0xA4)
0xA:  cchmod (fuc5 opcode 0xA8)
0xB:  cxor (fuc5 opcode 0xAC)
0xC:  cadd (fuc5 opcode 0xB0)
0xD:  cand (fuc5 opcode 0xB4)
0xE:  crev (fuc5 opcode 0xB8)
0xF:  cgfmul (fuc5 opcode 0xBC)
0x10: csecret (fuc5 opcode 0xC0)
0x11: ckeyreg (fuc5 opcode 0xC4)
0x12: ckexp (fuc5 opcode 0xC8)
0x13: ckrexp (fuc5 opcode 0xCC)
0x14: cenc (fuc5 opcode 0xD0)
0x15: cdec (fuc5 opcode 0xD4)
  0x16: csigcmp (fuc5 opcode 0xD8)
  0x17: csigenc (fuc5 opcode 0xDC)
  0x18: csigclr (fuc5 opcode 0xE0)
|-
|-
| 28
| 8-12
| [[#CMD|CMD]]'s current instruction is valid
| [[#SEQ|SEQ]]'s current sequence's size
|-
|-
| 31
| 13-16
| [[#CMD|CMD]] is running in HS mode
| [[#SEQ|SEQ]]'s current instruction's address
|}
 
Contains information on the last crypto command executed.
 
=== TSEC_SCP_STAT0 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0
| 17
| [[#SCP|SCP]] is active
| [[#SEQ|SEQ]]'s current instruction is valid
|-
|-
| 2
| 18
| [[#CMD|CMD]] is active
| [[#SEQ|SEQ]] is running in HS mode
|-
|-
| 4
| 19-22
| [[#STORE|STORE]] is active
| [[#LOAD|LOAD]]'s queue's size
|-
|-
| 6
| 23
| [[#SEQ|SEQ]] is active
| [[#LOAD|LOAD]]'s current operation is valid
|-
|-
| 8
| 24
| [[#CTL|CTL]] is active
| [[#LOAD|LOAD]] is running in HS mode
|-
|-
| 10
| 25-26
| [[#LOAD|LOAD]] is active
| [[#STORE|STORE]]'s queue's size
|-
|-
| 14
| 30
| [[#AES|AES]] is active
| [[#STORE|STORE]]'s current operation is valid
|-
|-
| 16
| 31
| [[#RNG|RNG]] is active
| [[#STORE|STORE]] is running in HS mode
|}
|}


Contains the statuses of hardware blocks.
Unofficial name.
 
Used for debugging the [[#LOAD|LOAD]], [[#STORE|STORE]] and [[#SEQ|SEQ]] blocks.


=== TSEC_SCP_STAT1 ===
=== TSEC_SCP_DBG1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-1
| 0-31
| Signature comparison result
| Data
  0: None
  If target is SEQ:
1: Running
  Bits 0-3: current instruction's first operand
2: Failed
  Bits 4-9: current instruction's second operand
3: Succeeded
  Bits 10-14: current instruction's opcode
|-
| 4
| [[#LOAD|Falcon<->LOAD]] interface is running in HS mode
|-
| 6
| [[#LOAD|Falcon<->LOAD]] interface is ready
|-
| 8
| [[#STORE|Falcon<->STORE]] interface is running in HS mode
|-
| 10
| [[#STORE|Falcon<->STORE]] interface received a valid operation
|-
| 12
| [[#CMD|Falcon<->CMD]] interface is running in HS mode
|-
| 14
| [[#CMD|Falcon<->CMD]] interface received a valid instruction
|}
|}


Contains the statuses of hardware interfaces and the result of the last authentication attempt.
Unofficial name.
 
Used for retrieving debug data. Contains information on the last crypto sequence created when debugging the [[#SEQ|SEQ]] block.


=== TSEC_SCP_STAT2 ===
=== TSEC_SCP_DBG2 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-4
| 0-1
| Current opcode in [[#SEQ|SEQ]]
| [[#SEQ|SEQ]]'s state
0: Idle
1: Recording (cs0begin/cs1begin)
2: Executing (cs0exec/cs1exec)
|-
|-
| 5-9
| 4-7
| Current opcode in [[#CMD|Falcon<->CMD]] interface
| Number of cycles left for [[#SEQ|SEQ]]'s current sequence
|-
|-
| 10-14
| 12-15
| Pending opcode in [[#CMD|CMD]]
| Active crypto key register (ckeyreg)
|-
| 15-16
| Current opcode in [[#AES|AES]]
0: Encryption
1: Decryption
2: Key expansion
3: Key reverse expansion
|-
| 24
| [[#SCP|SCP]]'s internal pipeline is stalled on hazard
|-
| 25
| [[#STORE|STORE]] is stalled
|-
| 26
| [[#LOAD|LOAD]] is stalled
|-
| 27
| [[#RNG|RNG]] is stalled
|-
| 28
| [[#SCP|SCP]]'s internal pipeline is stalled on writeback
|-
| 29
| [[#AES|AES]] is stalled
|}
|}


Contains the status of crypto operations.
Unofficial name.
 
Used for retrieving additional debug data associated with the [[#SEQ|SEQ]] block.


=== TSEC_SCP_RNG_STAT0 ===
=== TSEC_SCP_CMD ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 0-3
| [[#RND|RND]] is ready
| Destination register
|-
|-
| 4-7
| 8-13
| Unknown
| Source register or immediate value
|-
|-
| 8-11
| 20-24
| Unknown
| Command opcode
0x0:  nop (fuc5 opcode 0x00)
0x1:  cmov (fuc5 opcode 0x84)
0x2:  cxsin (fuc5 opcode 0x88) or xdst (with cxset)
0x3:  cxsout (fuc5 opcode 0x8C) or xdld (with cxset)
0x4:  crnd (fuc5 opcode 0x90)
0x5:  cs0begin (fuc5 opcode 0x94)
0x6:  cs0exec (fuc5 opcode 0x98)
0x7:  cs1begin (fuc5 opcode 0x9C)
0x8:  cs1exec (fuc5 opcode 0xA0)
0x9:  invalid (fuc5 opcode 0xA4)
0xA:  cchmod (fuc5 opcode 0xA8)
0xB:  cxor (fuc5 opcode 0xAC)
0xC:  cadd (fuc5 opcode 0xB0)
0xD:  cand (fuc5 opcode 0xB4)
0xE:  crev (fuc5 opcode 0xB8)
0xF:  cgfmul (fuc5 opcode 0xBC)
0x10: csecret (fuc5 opcode 0xC0)
0x11: ckeyreg (fuc5 opcode 0xC4)
0x12: ckexp (fuc5 opcode 0xC8)
0x13: ckrexp (fuc5 opcode 0xCC)
0x14: cenc (fuc5 opcode 0xD0)
0x15: cdec (fuc5 opcode 0xD4)
0x16: csigcmp (fuc5 opcode 0xD8)
0x17: csigenc (fuc5 opcode 0xDC)
0x18: csigclr (fuc5 opcode 0xE0)
|-
|-
| 16
| 28
| Unknown
| [[#CMD|CMD]]'s current instruction is valid
|-
|-
| 20
| 31
| Unknown
| [[#CMD|CMD]] is running in HS mode
|}
|}


=== TSEC_SCP_RNG_STAT1 ===
Unofficial name.
 
Contains information on the last crypto command executed.
 
=== TSEC_SCP_STAT0 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-15
| 0
| Unknown
| [[#SCP|SCP]] is active
|-
| 2
| [[#CMD|CMD]] is active
|-
|-
| 16-31
| 4
| Unknown
| [[#STORE|STORE]] is active
|}
 
=== TSEC_SCP_IRQSTAT ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0
| 6
| [[#RND|RND]] ready
| [[#SEQ|SEQ]] is active
|-
|-
| 8
| 8
| ACL error
| [[#CTL|CTL]] is active
|-
| 10
| [[#LOAD|LOAD]] is active
|-
|-
| 12
| 14
| SEC error
| [[#AES|AES]] is active
|-
|-
| 16
| 16
| [[#CMD|CMD]] error
| [[#RNG|RNG]] is active
|-
| 20
| Single step
|-
| 24
| [[#RND|RND]] clock trigger
|-
| 28
| Stall timeout
|}
|}


=== TSEC_SCP_IRQMASK ===
Unofficial name.
 
Contains the statuses of hardware blocks.
 
=== TSEC_SCP_STAT1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 0-1
| [[#RND|RND]] ready
| Signature comparison result
0: None
1: Running
2: Failed
3: Succeeded
|-
|-
| 8
| 4
| ACL error
| [[#LOAD|Falcon<->LOAD]] interface is running in HS mode
|-
|-
| 12
| 6
| SEC error
| [[#LOAD|Falcon<->LOAD]] interface is ready
|-
|-
| 16
| 8
| [[#CMD|CMD]] error
| [[#STORE|Falcon<->STORE]] interface is running in HS mode
|-
|-
| 20
| 10
| Single step
| [[#STORE|Falcon<->STORE]] interface received a valid operation
|-
|-
| 24
| 12
| [[#RND|RND]] clock trigger
| [[#CMD|Falcon<->CMD]] interface is running in HS mode
|-
|-
| 28
| 14
| Stall timeout
| [[#CMD|Falcon<->CMD]] interface received a valid instruction
|}
|}


=== TSEC_SCP_ACL_ERR ===
Unofficial name.
 
Contains the statuses of hardware interfaces and the result of the last authentication attempt.
 
=== TSEC_SCP_STAT2 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 0-4
| Writing to a crypto register without the correct ACL
| Current opcode in [[#SEQ|SEQ]]
|-
|-
| 4
| 5-9
| Reading from a crypto register without the correct ACL
| Current opcode in [[#CMD|Falcon<->CMD]] interface
|-
|-
| 8
| 10-14
| Invalid ACL change (cchmod)
| Pending opcode in [[#CMD|CMD]]
|-
|-
| 31
| 15-16
| ACL error occurred
| Current opcode in [[#AES|AES]]
|}
0: Encryption
1: Decryption
2: Key expansion
3: Key reverse expansion
|-
| 24
| [[#SCP|SCP]]'s internal pipeline is stalled on hazard
|-
| 25
| [[#STORE|STORE]] is stalled
|-
| 26
| [[#LOAD|LOAD]] is stalled
|-
| 27
| [[#RNG|RNG]] is stalled
|-
| 28
| [[#SCP|SCP]]'s internal pipeline is stalled on writeback
|-
| 29
| [[#AES|AES]] is stalled
|}
 
Unofficial name.


Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|ACL error]] IRQ.
Contains the status of crypto operations.


=== TSEC_SCP_SEC_ERR ===
=== TSEC_SCP_RNG_STAT0 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 4,084: Line 4,105:
|-
|-
| 0
| 0
| Security mode changed during sequence execution (cs0exec/cs1exec)
| [[#RND|RND]] is ready
|-
|-
| 1-2
| 4-7
| Security mode at the beginning of sequence execution
| Unknown
0: Non-secure
1: Heavy Secure
|-
|-
| 4
| 8-11
| Security mode changed during sequence recording (cs0begin/cs1begin)
| Unknown
|-
| 5-6
| Security mode at the beginning of sequence recording
0: Non-secure
1: Heavy Secure
|-
|-
| 16
| 16
| Security mode changed while reading from crypto register/stream (cxsout or xdld)
| Unknown
|-
| 17-18
| Security mode at the beginning of reading from crypto register/stream
0: Non-secure
1: Heavy Secure
|-
|-
| 20
| 20
| Security mode and memory source changed while writing to crypto register/stream (cxsin or xdst)
| Unknown
|}
 
Unofficial name.
 
=== TSEC_SCP_RNG_STAT1 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 21-22
| 0-15
| Security mode when memory source changed while writing to crypto register/stream
| Unknown
0: Non-secure
1: Heavy Secure
|-
|-
| 24
| 16-31
| Security mode changed while writing to crypto register/stream (cxsin or xdst)
| Unknown
|-
| 25-26
| Security mode at the beginning of writing to crypto register/stream
0: Non-secure
1: Heavy Secure
|-
| 31
| SEC error occurred
|}
|}


Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|SEC error]] IRQ.
Unofficial name.


=== TSEC_SCP_CMD_ERR ===
=== TSEC_SCP_IRQSTAT ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 4,135: Line 4,142:
|-
|-
| 0
| 0
| [[#CMD|CMD]]'s instruction is invalid
| [[#RND|RND]] ready
|-
| 4
| [[#SEQ|SEQ]]'s sequence is empty
|-
|-
| 8
| 8
| [[#SEQ|SEQ]]'s sequence is too long
| ACL error
|-
|-
| 12
| 12
| [[#SEQ|SEQ]]'s sequence was not finished
| SEC error
|-
|-
| 16
| 16
| Forbidden signature operation (csigcmp, csigenc or csigclr in NS mode)
| [[#CMD|CMD]] error
|-
|-
| 20
| 20
| Invalid signature operation (csigcmp in HS mode)
| Single step
|-
|-
| 24
| 24
| Forbidden ACL change (cchmod in NS mode)
| [[#RND|RND]] clock trigger
|-
| 28
| Stall timeout
|}
|}


Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ.
Unofficial name.


=== TSEC_SCP_RND_CTL0 ===
=== TSEC_SCP_IRQMASK ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-31
| 0
| [[#RND|RND]] clock trigger's lower limit
| [[#RND|RND]] ready
|}
|-
 
| 8
=== TSEC_SCP_RND_CTL1 ===
| ACL error
{| class="wikitable" border="1"
|-
!  Bits
| 12
!  Description
| SEC error
|-
| 16
| [[#CMD|CMD]] error
|-
| 20
| Single step
|-
|-
| 0-15
| 24
| [[#RND|RND]] clock trigger's upper limit
| [[#RND|RND]] clock trigger
|-
|-
| 16-31
| 28
| [[#RND|RND]] clock trigger's mask
| Stall timeout
|}
|}


=== TSEC_SCP_RND_CTL2 ===
Unofficial name.
 
=== TSEC_SCP_ACL_ERR ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-15
| 0
| Unknown
| Writing to a crypto register without the correct ACL
|}
 
=== TSEC_SCP_RND_CTL3 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 12
| 4
| Trigger first LFSR
| Reading from a crypto register without the correct ACL
|-
|-
| 16
| 8
| Trigger second LFSR
| Invalid ACL change (cchmod)
|}
 
=== TSEC_SCP_RND_CTL4 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0-31
| 31
| First LFSR's polynomial for [[#RNG|RNG]]'s test mode
| ACL error occurred
|}
|}


=== TSEC_SCP_RND_CTL5 ===
Unofficial name.
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| First LFSR's initial state for [[#RNG|RNG]]'s test mode
|}


=== TSEC_SCP_RND_CTL6 ===
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|ACL error]] IRQ.
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| Second LFSR's polynomial for [[#RNG|RNG]]'s test mode
|}


=== TSEC_SCP_RND_CTL7 ===
=== TSEC_SCP_SEC_ERR ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-31
| 0
| Second LFSR's initial state for [[#RNG|RNG]]'s test mode
| Security mode changed during sequence execution (cs0exec/cs1exec)
|}
 
=== TSEC_SCP_RND_CTL8 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0-15
| 1-2
| Unknown
| Security mode at the beginning of sequence execution
0: Non-secure
1: Heavy Secure
|-
|-
| 16-31
| 4
| Unknown
| Security mode changed during sequence recording (cs0begin/cs1begin)
|}
 
=== TSEC_SCP_RND_CTL9 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0-15
| 5-6
| Unknown
| Security mode at the beginning of sequence recording
0: Non-secure
1: Heavy Secure
|-
|-
| 16-31
| 16
| Unknown
| Security mode changed while reading from crypto register/stream (cxsout or xdld)
|}
 
=== TSEC_SCP_RND_CTL10 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0-15
| 17-18
| Unknown
| Security mode at the beginning of reading from crypto register/stream
0: Non-secure
1: Heavy Secure
|-
|-
| 16-31
| 20
| Unknown
| Security mode and memory source changed while writing to crypto register/stream (cxsin or xdst)
|-
| 21-22
| Security mode when memory source changed while writing to crypto register/stream
0: Non-secure
1: Heavy Secure
|-
| 24
| Security mode changed while writing to crypto register/stream (cxsin or xdst)
|-
| 25-26
| Security mode at the beginning of writing to crypto register/stream
0: Non-secure
1: Heavy Secure
|-
| 31
| SEC error occurred
|}
|}


=== TSEC_SCP_RND_CTL11 ===
Unofficial name.
 
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|SEC error]] IRQ.
 
=== TSEC_SCP_CMD_ERR ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 4,278: Line 4,275:
|-
|-
| 0
| 0
| Unknown
| [[#CMD|CMD]]'s instruction is invalid
|-
| 4
| [[#SEQ|SEQ]]'s sequence is empty
|-
|-
| 1
| 8
| Unknown
| [[#SEQ|SEQ]]'s sequence is too long
|-
|-
| 2
| 12
| Unknown
| [[#SEQ|SEQ]]'s sequence was not finished
|-
|-
| 3
| 16
| Unknown
| Forbidden signature operation (csigcmp, csigenc or csigclr in NS mode)
|-
|-
| 4-5
| 20
| First sampler's source
| Invalid signature operation (csigcmp in HS mode)
0: Oscillator
1: Unknown
2: LFSR
3: Dummy
|-
|-
| 6-7
| 24
| Second sampler's source
| Forbidden ACL change (cchmod in NS mode)
0: Oscillator
|}
1: Unknown
 
  2: LFSR
Unofficial name.
  3: Dummy
 
Contains information on errors generated by the [[#TSEC_SCP_IRQSTAT|CMD error]] IRQ.
 
=== TSEC_SCP_RND_CTL0 ===
{| class="wikitable" border="1"
! Bits
! Description
|-
|-
| 8-11
| 0-31
| First sampler's tap value
| [[#RND|RND]] clock trigger's lower limit
|-
| 12-15
| Second sampler's tap value
|-
| 16-19
| Unknown
|-
| 20-23
| Unknown
|-
| 24-30
| Unknown
|-
| 31
| Unknown
|}
|}


=== TSEC_TFBIF_CTL ===
Unofficial name.
 
=== TSEC_SCP_RND_CTL1 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 0-15
| TSEC_TFBIF_CTL_CLR_BWCOUNT
| [[#RND|RND]] clock trigger's upper limit
|-
|-
| 1
| 16-31
| TSEC_TFBIF_CTL_ENABLE
| [[#RND|RND]] clock trigger's mask
|}
 
Unofficial name.
 
=== TSEC_SCP_RND_CTL2 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 2
| 0-15
| TSEC_TFBIF_CTL_CLR_IDLEWDERR
| Unknown
|-
| 3
| TSEC_TFBIF_CTL_RESET
|-
| 4
| TSEC_TFBIF_CTL_IDLE
|-
| 5
| TSEC_TFBIF_CTL_IDLEWDERR
|-
| 6
| TSEC_TFBIF_CTL_SRTOUT
|-
| 7
| TSEC_TFBIF_CTL_CLR_SRTOUT
|-
| 8-11
| TSEC_TFBIF_CTL_SRTOVAL
|-
| 12
| TSEC_TFBIF_CTL_VPR
|}
|}


=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
Unofficial name.
 
=== TSEC_SCP_RND_CTL3 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 12
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
| Trigger first LFSR
|-
|-
| 1
| 16
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
| Trigger second LFSR
|-
| 2
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
|-
| 3
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDMC_RDFAST
|-
| 4
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRMC_CLLE2X
|-
| 5
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDCL_RDFAST
|-
| 6
| TSEC_TFBIF_MCCIF_FIFOCTRL_CCLK_OVERRIDE
|-
| 7
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVR_MODE
|-
| 8
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVR_MODE
|}
|}


=== TSEC_TFBIF_THROTTLE ===
Unofficial name.
 
=== TSEC_SCP_RND_CTL4 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-11
| 0-31
| TSEC_TFBIF_THROTTLE_BUCKET_SIZE
| First LFSR's polynomial for [[#RNG|RNG]]'s test mode
|-
| 16-27
| TSEC_TFBIF_THROTTLE_LEAK_COUNT
|-
| 30-31
| TSEC_TFBIF_THROTTLE_LEAK_SIZE
|}
|}


=== TSEC_TFBIF_DBG_STAT0 ===
Unofficial name.
 
=== TSEC_SCP_RND_CTL5 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 0-31
| TSEC_TFBIF_DBG_STAT0_1K_TRANSFER
| First LFSR's initial state for [[#RNG|RNG]]'s test mode
|-
|}
| 1
 
| TSEC_TFBIF_DBG_STAT0_RREQ_ISSUED
Unofficial name.
 
=== TSEC_SCP_RND_CTL6 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 2
| 0-31
| TSEC_TFBIF_DBG_STAT0_WREQ_ISSUED
| Second LFSR's polynomial for [[#RNG|RNG]]'s test mode
|}
 
Unofficial name.
 
=== TSEC_SCP_RND_CTL7 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 3
| 0-31
| TSEC_TFBIF_DBG_STAT0_TAGQ_ISSUED
| Second LFSR's initial state for [[#RNG|RNG]]'s test mode
|}
 
Unofficial name.
 
=== TSEC_SCP_RND_CTL8 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 4
| 0-15
| TSEC_TFBIF_DBG_STAT0_STALL_RDATQ
| Unknown
|-
|-
| 5
| 16-31
| TSEC_TFBIF_DBG_STAT0_STALL_RACKQ
| Unknown
|}
 
Unofficial name.
 
=== TSEC_SCP_RND_CTL9 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 6
| 0-15
| TSEC_TFBIF_DBG_STAT0_STALL_WREQQ
| Unknown
|-
|-
| 7
| 16-31
| TSEC_TFBIF_DBG_STAT0_STALL_WDATQ
| Unknown
|}
 
Unofficial name.
 
=== TSEC_SCP_RND_CTL10 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 8
| 0-15
| TSEC_TFBIF_DBG_STAT0_STALL_WACKQ
| Unknown
|-
|-
| 9
| 16-31
| TSEC_TFBIF_DBG_STAT0_STALL_RREQ_PENDING
| Unknown
|}
 
Unofficial name.
 
=== TSEC_SCP_RND_CTL11 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 10
| 0
| TSEC_TFBIF_DBG_STAT0_STALL_WREQ_PENDING
| Unknown
|-
|-
| 11
| 1
| TSEC_TFBIF_DBG_STAT0_STALL_MREQ
| Unknown
|-
|-
| 12
| 2
| TSEC_TFBIF_DBG_STAT0_ENGINE_IDLE
| Unknown
|-
|-
| 13
| 3
| TSEC_TFBIF_DBG_STAT0_RMCCIF_IDLE
| Unknown
|-
|-
| 14
| 4-5
| TSEC_TFBIF_DBG_STAT0_WMCCIF_IDLE
| First sampler's source
0: Oscillator
1: Unknown
2: LFSR
3: Dummy
|-
| 6-7
| Second sampler's source
0: Oscillator
1: Unknown
2: LFSR
3: Dummy
|-
| 8-11
| First sampler's tap value
|-
|-
| 15
| 12-15
| TSEC_TFBIF_DBG_STAT0_CSB_IDLE
| Second sampler's tap value
|-
|-
| 16
| 16-19
| TSEC_TFBIF_DBG_STAT0_RU_IDLE
| Unknown
|-
|-
| 17
| 20-23
| TSEC_TFBIF_DBG_STAT0_WU_IDLE
| Unknown
|-
|-
| 19
| 24-30
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_ACTIVE
| Unknown
|-
|-
| 20
| 31
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_MCB
| Unknown
|}
|}


=== TSEC_TFBIF_DBG_STAT1 ===
Unofficial name.
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| TSEC_TFBIF_DBG_STAT1_DATA
|}


=== TSEC_TFBIF_DBG_RDCOUNT_LO ===
=== TSEC_TFBIF_CTL ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-31
| 0
| TSEC_TFBIF_DBG_RDCOUNT_LO_DATA
| TSEC_TFBIF_CTL_CLR_BWCOUNT
|-
| 1
| TSEC_TFBIF_CTL_ENABLE
|-
| 2
| TSEC_TFBIF_CTL_CLR_IDLEWDERR
|-
| 3
| TSEC_TFBIF_CTL_RESET
|-
| 4
| TSEC_TFBIF_CTL_IDLE
|-
| 5
| TSEC_TFBIF_CTL_IDLEWDERR
|-
| 6
| TSEC_TFBIF_CTL_SRTOUT
|-
| 7
| TSEC_TFBIF_CTL_CLR_SRTOUT
|-
| 8-11
| TSEC_TFBIF_CTL_SRTOVAL
|-
| 12
| TSEC_TFBIF_CTL_VPR
|}
|}


=== TSEC_TFBIF_DBG_RDCOUNT_HI ===
=== TSEC_TFBIF_MCCIF_FIFOCTRL ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-31
| 0
| TSEC_TFBIF_DBG_RDCOUNT_HI_DATA
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVERRIDE
|}
 
=== TSEC_TFBIF_DBG_WRCOUNT_LO ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0-31
| 1
| TSEC_TFBIF_DBG_WRCOUNT_LO_DATA
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVERRIDE
|}
|-
 
| 2
=== TSEC_TFBIF_DBG_WRCOUNT_HI ===
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRCL_MCLE2X
{| class="wikitable" border="1"
|-
!  Bits
| 3
!  Description
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDMC_RDFAST
|-
| 4
| TSEC_TFBIF_MCCIF_FIFOCTRL_WRMC_CLLE2X
|-
| 5
| TSEC_TFBIF_MCCIF_FIFOCTRL_RDCL_RDFAST
|-
| 6
| TSEC_TFBIF_MCCIF_FIFOCTRL_CCLK_OVERRIDE
|-
| 7
| TSEC_TFBIF_MCCIF_FIFOCTRL_RCLK_OVR_MODE
|-
|-
| 0-31
| 8
| TSEC_TFBIF_DBG_WRCOUNT_HI_DATA
| TSEC_TFBIF_MCCIF_FIFOCTRL_WCLK_OVR_MODE
|}
|}


=== TSEC_TFBIF_DBG_R32COUNT ===
=== TSEC_TFBIF_THROTTLE ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-31
| 0-11
| TSEC_TFBIF_DBG_R32COUNT_DATA
| TSEC_TFBIF_THROTTLE_BUCKET_SIZE
|-
| 16-27
| TSEC_TFBIF_THROTTLE_LEAK_COUNT
|-
| 30-31
| TSEC_TFBIF_THROTTLE_LEAK_SIZE
|}
|}


=== TSEC_TFBIF_DBG_R64COUNT ===
=== TSEC_TFBIF_DBG_STAT0 ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-31
| 0
| TSEC_TFBIF_DBG_R64COUNT_DATA
| TSEC_TFBIF_DBG_STAT0_1K_TRANSFER
|}
 
=== TSEC_TFBIF_DBG_R128COUNT ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0-31
| 1
| TSEC_TFBIF_DBG_R128COUNT_DATA
| TSEC_TFBIF_DBG_STAT0_RREQ_ISSUED
|}
 
=== TSEC_TFBIF_MCCIF_FIFOCTRL1 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0-15
| 2
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SRD2MC_REORDER_DEPTH_LIMIT
| TSEC_TFBIF_DBG_STAT0_WREQ_ISSUED
|-
|-
| 16-31
| 3
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
| TSEC_TFBIF_DBG_STAT0_TAGQ_ISSUED
|}
 
=== TSEC_TFBIF_WRR_RDP ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0-15
| 4
| TSEC_TFBIF_WRR_RDP_EXT_WEIGHT
| TSEC_TFBIF_DBG_STAT0_STALL_RDATQ
|-
|-
| 16-31
| 5
| TSEC_TFBIF_WRR_RDP_INT_WEIGHT
| TSEC_TFBIF_DBG_STAT0_STALL_RACKQ
|}
 
=== TSEC_TFBIF_SPROT_EMEM ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0-3
| 6
| Read access level
| TSEC_TFBIF_DBG_STAT0_STALL_WREQQ
|-
|-
| 4-7
| 7
| Write access level
| TSEC_TFBIF_DBG_STAT0_STALL_WDATQ
|}
|-
 
| 8
Controls accesses to external memory regions. Accessible in HS mode only.
| TSEC_TFBIF_DBG_STAT0_STALL_WACKQ
 
=== TSEC_TFBIF_TRANSCFG ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 0
| 9
| TSEC_TFBIF_TRANSCFG_ATT0_SWID
| TSEC_TFBIF_DBG_STAT0_STALL_RREQ_PENDING
|-
|-
| 4
| 10
| TSEC_TFBIF_TRANSCFG_ATT1_SWID
| TSEC_TFBIF_DBG_STAT0_STALL_WREQ_PENDING
|-
|-
| 8
| 11
| TSEC_TFBIF_TRANSCFG_ATT2_SWID
| TSEC_TFBIF_DBG_STAT0_STALL_MREQ
|-
|-
| 12
| 12
| TSEC_TFBIF_TRANSCFG_ATT3_SWID
| TSEC_TFBIF_DBG_STAT0_ENGINE_IDLE
|-
| 13
| TSEC_TFBIF_DBG_STAT0_RMCCIF_IDLE
|-
|-
| 16
| 14
| TSEC_TFBIF_TRANSCFG_ATT4_SWID
| TSEC_TFBIF_DBG_STAT0_WMCCIF_IDLE
|-
|-
| 20
| 15
| TSEC_TFBIF_TRANSCFG_ATT5_SWID
| TSEC_TFBIF_DBG_STAT0_CSB_IDLE
|-
|-
| 24
| 16
| TSEC_TFBIF_TRANSCFG_ATT6_SWID
| TSEC_TFBIF_DBG_STAT0_RU_IDLE
|-
|-
| 28
| 17
| TSEC_TFBIF_TRANSCFG_ATT7_SWID
| TSEC_TFBIF_DBG_STAT0_WU_IDLE
|-
| 19
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_ACTIVE
|-
| 20
| TSEC_TFBIF_DBG_STAT0_UNWEIGHT_ACTMON_MCB
|}
|}


Configures the software ID per CTXDMA port for memory transactions. Software ID 0 (HW_SWID) forces all transactions to go through the SMMU while software ID 1 (PHY_SWID) bypasses it. Accessible in HS mode only.
=== TSEC_TFBIF_DBG_STAT1 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| TSEC_TFBIF_DBG_STAT1_DATA
|}


[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
=== TSEC_TFBIF_DBG_RDCOUNT_LO ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| TSEC_TFBIF_DBG_RDCOUNT_LO_DATA
|}


=== TSEC_TFBIF_REGIONCFG ===
=== TSEC_TFBIF_DBG_RDCOUNT_HI ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-2
| 0-31
| TSEC_TFBIF_REGIONCFG_T0_APERT_ID
| TSEC_TFBIF_DBG_RDCOUNT_HI_DATA
|}
 
=== TSEC_TFBIF_DBG_WRCOUNT_LO ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 3
| 0-31
| TSEC_TFBIF_REGIONCFG_T0_VPR
| TSEC_TFBIF_DBG_WRCOUNT_LO_DATA
|-
|}
| 4-6
 
| TSEC_TFBIF_REGIONCFG_T1_APERT_ID
=== TSEC_TFBIF_DBG_WRCOUNT_HI ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 7
| 0-31
| TSEC_TFBIF_REGIONCFG_T1_VPR
| TSEC_TFBIF_DBG_WRCOUNT_HI_DATA
|}
 
=== TSEC_TFBIF_DBG_R32COUNT ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 8-10
| 0-31
| TSEC_TFBIF_REGIONCFG_T2_APERT_ID
| TSEC_TFBIF_DBG_R32COUNT_DATA
|}
 
=== TSEC_TFBIF_DBG_R64COUNT ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 11
| 0-31
| TSEC_TFBIF_REGIONCFG_T2_VPR
| TSEC_TFBIF_DBG_R64COUNT_DATA
|}
 
=== TSEC_TFBIF_DBG_R128COUNT ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 12-14
| 0-31
| TSEC_TFBIF_REGIONCFG_T3_APERT_ID
| TSEC_TFBIF_DBG_R128COUNT_DATA
|}
 
=== TSEC_TFBIF_MCCIF_FIFOCTRL1 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
|-
| 15
| 0-15
| TSEC_TFBIF_REGIONCFG_T3_VPR
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SRD2MC_REORDER_DEPTH_LIMIT
|-
|-
| 16-18
| 16-31
| TSEC_TFBIF_REGIONCFG_T4_APERT_ID
| TSEC_TFBIF_MCCIF_FIFOCTRL1_SWR2MC_REORDER_DEPTH_LIMIT
|-
| 19
| TSEC_TFBIF_REGIONCFG_T4_VPR
|-
| 20-22
| TSEC_TFBIF_REGIONCFG_T5_APERT_ID
|-
| 23
| TSEC_TFBIF_REGIONCFG_T5_VPR
|-
| 24-26
| TSEC_TFBIF_REGIONCFG_T6_APERT_ID
|-
| 27
| TSEC_TFBIF_REGIONCFG_T6_VPR
|-
| 28-30
| TSEC_TFBIF_REGIONCFG_T7_APERT_ID
|-
| 31
| TSEC_TFBIF_REGIONCFG_T7_VPR
|}
|}


Configures the aperture ID and VPR mode per CTXDMA port for memory region accessing. Accessible in HS mode only.
=== TSEC_TFBIF_SPROT_EMEM ===
 
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
 
=== TSEC_TFBIF_ACTMON_ACTIVE_MASK ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 0-2
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_STARVED_MC
| Read access level
|-
|-
| 1
| 3
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_STALLED_MC
| Set on memory read access violation
|-
|-
| 2
| 4-6
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_DELAYED_MC
| Write access level
|-
|-
| 3
| 7
| TSEC_TFBIF_ACTMON_ACTIVE_MASK_ACTIVE
| Set on memory write access violation
|}
|}


Takes the memory access mask for the Activity Monitor. Disconnected on the TSEC.
Unofficial name.


=== TSEC_TFBIF_ACTMON_ACTIVE_BORPS ===
Controls accesses to external memory regions. Accessible in HS mode only.
 
=== TSEC_TFBIF_TRANSCFG ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
Line 4,700: Line 4,750:
|-
|-
| 0
| 0
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_POLARITY
| TSEC_TFBIF_TRANSCFG_ATT0_SWID
|-
|-
| 1
| 4
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STARVED_MC_OPERATION
| TSEC_TFBIF_TRANSCFG_ATT1_SWID
|-
|-
| 2
| 8
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_POLARITY
| TSEC_TFBIF_TRANSCFG_ATT2_SWID
|-
|-
| 3
| 12
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_STALLED_MC_OPERATION
| TSEC_TFBIF_TRANSCFG_ATT3_SWID
|-
|-
| 4
| 16
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_POLARITY
| TSEC_TFBIF_TRANSCFG_ATT4_SWID
|-
|-
| 5
| 20
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_DELAYED_MC_OPERATION
| TSEC_TFBIF_TRANSCFG_ATT5_SWID
|-
|-
| 6
| 24
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_POLARITY
| TSEC_TFBIF_TRANSCFG_ATT6_SWID
|-
|-
| 7
| 28
| TSEC_TFBIF_ACTMON_ACTIVE_BORPS_ACTIVE_OPERATION
| TSEC_TFBIF_TRANSCFG_ATT7_SWID
|}
|}


Takes the billions of records per second count for the Activity Monitor. Disconnected on the TSEC.
Configures the software ID per CTXDMA port for memory transactions. Software ID 0 (HW_SWID) forces all transactions to go through the SMMU while software ID 1 (PHY_SWID) bypasses it. Accessible in HS mode only.


=== TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT ===
[6.0.0+] The nvhost_tsec firmware sets this register to 0x10 or 0x111110 before reading memory from the GPU UCODE carveout.
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| TSEC_TFBIF_ACTMON_ACTIVE_WEIGHT_VAL
|}


Controls the Activity Monitor. Disconnected on the TSEC.
=== TSEC_TFBIF_REGIONCFG ===
 
=== TSEC_TFBIF_ACTMON_MCB_MASK ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0
| 0-2
| TSEC_TFBIF_ACTMON_MCB_MASK_STARVED_MC
| TSEC_TFBIF_REGIONCFG_T0_APERT_ID
|-
|-
| 1
| 3
| TSEC_TFBIF_ACTMON_MCB_MASK_STALLED_MC
| TSEC_TFBIF_REGIONCFG_T0_VPR
|-
|-
| 2
| 4-6
| TSEC_TFBIF_ACTMON_MCB_MASK_DELAYED_MC
| TSEC_TFBIF_REGIONCFG_T1_APERT_ID
|-
|-
| 3
| 7
| TSEC_TFBIF_ACTMON_MCB_MASK_ACTIVE
| TSEC_TFBIF_REGIONCFG_T1_VPR
|}
|-
 
| 8-10
Disconnected on the TSEC.
| TSEC_TFBIF_REGIONCFG_T2_APERT_ID
 
|-
=== TSEC_TFBIF_ACTMON_MCB_BORPS ===
| 11
{| class="wikitable" border="1"
| TSEC_TFBIF_REGIONCFG_T2_VPR
!  Bits
|-
!  Description
| 12-14
| TSEC_TFBIF_REGIONCFG_T3_APERT_ID
|-
| 15
| TSEC_TFBIF_REGIONCFG_T3_VPR
|-
|-
| 0
| 16-18
| TSEC_TFBIF_ACTMON_MCB_BORPS_STARVED_MC_POLARITY
| TSEC_TFBIF_REGIONCFG_T4_APERT_ID
|-
|-
| 1
| 19
| TSEC_TFBIF_ACTMON_MCB_BORPS_STARVED_MC_OPERATION
| TSEC_TFBIF_REGIONCFG_T4_VPR
|-
|-
| 2
| 20-22
| TSEC_TFBIF_ACTMON_MCB_BORPS_STALLED_MC_POLARITY
| TSEC_TFBIF_REGIONCFG_T5_APERT_ID
|-
|-
| 3
| 23
| TSEC_TFBIF_ACTMON_MCB_BORPS_STALLED_MC_OPERATION
| TSEC_TFBIF_REGIONCFG_T5_VPR
|-
|-
| 4
| 24-26
| TSEC_TFBIF_ACTMON_MCB_BORPS_DELAYED_MC_POLARITY
| TSEC_TFBIF_REGIONCFG_T6_APERT_ID
|-
|-
| 5
| 27
| TSEC_TFBIF_ACTMON_MCB_BORPS_DELAYED_MC_OPERATION
| TSEC_TFBIF_REGIONCFG_T6_VPR
|-
|-
| 6
| 28-30
| TSEC_TFBIF_ACTMON_MCB_BORPS_ACTIVE_POLARITY
| TSEC_TFBIF_REGIONCFG_T7_APERT_ID
|-
|-
| 7
| 31
| TSEC_TFBIF_ACTMON_MCB_BORPS_ACTIVE_OPERATION
| TSEC_TFBIF_REGIONCFG_T7_VPR
|}
|}


Disconnected on the TSEC.
Configures the aperture ID and VPR mode per CTXDMA port for memory region accessing. Accessible in HS mode only.


=== TSEC_TFBIF_ACTMON_MCB_WEIGHT ===
[6.0.0+] The nvhost_tsec firmware sets this register to 0x20 or 0x140 before reading memory from the GPU UCODE carveout.
 
=== TSEC_CG ===
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  Bits
!  Bits
!  Description
!  Description
|-
|-
| 0-31
| 0-5
| TSEC_TFBIF_ACTMON_MCB_WEIGHT_VAL
|}
 
Disconnected on the TSEC.
 
=== TSEC_TFBIF_THI_TRANSPROP ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-6
| TSEC_TFBIF_THI_TRANSPROP_STREAMID0
|-
| 8-14
| TSEC_TFBIF_THI_TRANSPROP_STREAMID1
|-
| 16
| TSEC_TFBIF_THI_TRANSPROP_TZ_AUTH
|}
 
=== TSEC_CG ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-5
| TSEC_CG_IDLE_CG_DLY_CNT
| TSEC_CG_IDLE_CG_DLY_CNT
|-
|-
Line 4,864: Line 4,885:
| TSEC_BAR0_CTL_INIT
| TSEC_BAR0_CTL_INIT
|}
|}
Unofficial name.


Controls DMA transfers between TSEC and HOST1X (master and clients).
Controls DMA transfers between TSEC and HOST1X (master and clients).
Line 4,877: Line 4,900:
| TSEC_BAR0_ADDR_VAL
| TSEC_BAR0_ADDR_VAL
|}
|}
Unofficial name.


Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
Takes the address for DMA transfers between TSEC and HOST1X (master and clients).
Line 4,888: Line 4,913:
| TSEC_BAR0_DATA_VAL
| TSEC_BAR0_DATA_VAL
|}
|}
Unofficial name.


Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
Takes the data for DMA transfers between TSEC and HOST1X (master and clients).
Line 4,899: Line 4,926:
| TSEC_BAR0_TIMEOUT_VAL
| TSEC_BAR0_TIMEOUT_VAL
|}
|}
Unofficial name.


Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients).
Takes the timeout value for DMA transfers between TSEC and HOST1X (master and clients).
=== TSEC_VERSION ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| Version
|}
Unofficial name.
=== TSEC_SCRATCH0 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| Value
|}
Unofficial name.
=== TSEC_SCRATCH1 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| Value
|}
Unofficial name.
=== TSEC_SCRATCH2 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| Value
|}
Unofficial name.
=== TSEC_SCRATCH3 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| Value
|}
Unofficial name.
=== TSEC_SCRATCH4 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| Value
|}
Unofficial name.
=== TSEC_SCRATCH5 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| Value
|}
Unofficial name.
=== TSEC_SCRATCH6 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| Value
|}
Unofficial name.
=== TSEC_SCRATCH7 ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0-31
| Value
|}
Unofficial name.
=== TSEC_GPTMRINT ===
Unofficial name.
Same as [[#TSEC_FALCON_GPTMRINT|TSEC_FALCON_GPTMRINT]], but for an unknown hardware block.
=== TSEC_GPTMRVAL ===
Unofficial name.
Same as [[#TSEC_FALCON_GPTMRVAL|TSEC_FALCON_GPTMRVAL]], but for an unknown hardware block.
=== TSEC_GPTMRCTL ===
Unofficial name.
Same as [[#TSEC_FALCON_GPTMRCTL|TSEC_FALCON_GPTMRCTL]], but for an unknown hardware block.
=== TSEC_ITFEN ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0
| Enable [[#TSEC_GPTMRINT|TSEC_GPTMRINT]]
|-
| 1
| Unknown
|-
| 2
| Unknown
|-
| 3
| Unknown
|}
Unofficial name.
=== TSEC_ITFSTAT ===
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0
| [[#TSEC_GPTMRINT|TSEC_GPTMRINT]] is enabled
|-
| 1
| Unknown
|-
| 2
| Unknown
|-
| 3
| Unknown
|}
Unofficial name.


=== TSEC_TEGRA_CTL ===
=== TSEC_TEGRA_CTL ===
Line 5,209: Line 5,392:
| 2 || xsin || $cX || N/A || <code><nowiki>$cX = read_from_stream();</nowiki></code> || N/A || <code><nowiki>ACL($cX) = is_mode_hs ? 0x3 : 0x1F;</nowiki></code>
| 2 || xsin || $cX || N/A || <code><nowiki>$cX = read_from_stream();</nowiki></code> || N/A || <code><nowiki>ACL($cX) = is_mode_hs ? 0x3 : 0x1F;</nowiki></code>
|-
|-
| 3 || xsout || $cX || N/A || <code><nowiki>write_to_stream($cX);</nowiki></code> || <code><nowiki>(is_mode_hs && (ACL($cX) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0xA))</nowiki></code> || N/A
| 3 || xsout || $cX || N/A || <code><nowiki>write_to_stream($cX);</nowiki></code> || <code><nowiki>((is_mode_hs && (ACL($cX) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0xA)))</nowiki></code> || N/A
|-
|-
| 4 || [[#rnd|rnd]] || $cX || N/A || <code><nowiki>$cX = read_from_rnd();</nowiki></code> || N/A || <code><nowiki>ACL($cX) = is_mode_hs ? 0x3 : 0x1F;</nowiki></code>
| 4 || [[#rnd|rnd]] || $cX || N/A || <code><nowiki>$cX = read_from_rnd();</nowiki></code> || N/A || <code><nowiki>ACL($cX) = is_mode_hs ? 0x3 : 0x1F;</nowiki></code>
Line 5,225: Line 5,408:
| 0xA || [[#chmod|chmod]] || $cX || immY || <code><nowiki>ACL($cX) = immY;</nowiki></code> || See [[#ACLs|ACLs]] || N/A
| 0xA || [[#chmod|chmod]] || $cX || immY || <code><nowiki>ACL($cX) = immY;</nowiki></code> || See [[#ACLs|ACLs]] || N/A
|-
|-
| 0xB || xor || $cX || $cY || <code><nowiki>$cX ^= $cY;</nowiki></code> || <code><nowiki>(is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
| 0xB || xor || $cX || $cY || <code><nowiki>$cX ^= $cY;</nowiki></code> || <code><nowiki>((is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
|-
|-
| 0xC || add || $cX || immY || <code><nowiki>$cX += immY;</nowiki></code> || <code><nowiki>(is_mode_hs && (ACL($cX) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A))</nowiki></code> || N/A
| 0xC || add || $cX || immY || <code><nowiki>$cX += immY;</nowiki></code> || <code><nowiki>((is_mode_hs && (ACL($cX) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A)))</nowiki></code> || N/A
|-
|-
| 0xD || and || $cX || $cY || <code><nowiki>$cX &= $cY;</nowiki></code> || <code><nowiki>(is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
| 0xD || and || $cX || $cY || <code><nowiki>$cX &= $cY;</nowiki></code> || <code><nowiki>((is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
|-
|-
| 0xE || rev || $cX || $cY || <code><nowiki>$cX = endian_swap128($cY);</nowiki></code> || <code><nowiki>(!is_mode_hs && (ACL($cX) & 0x10))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
| 0xE || rev || $cX || $cY || <code><nowiki>$cX = endian_swap128($cY);</nowiki></code> || <code><nowiki>(is_mode_hs || (!is_mode_hs && (ACL($cX) & 0x10)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
|-
|-
| 0xF || gfmul || $cX || $cY || <code><nowiki>$cX = gfmul($cY);</nowiki></code>|| <code><nowiki>(is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
| 0xF || gfmul || $cX || $cY || <code><nowiki>$cX = gfmul($cY);</nowiki></code>|| <code><nowiki>((is_mode_hs && (ACL($cX) & 0x2) && (ACL($cY) & 0x2)) || (!is_mode_hs && (ACL($cX) & 0x1A) && (ACL($cY) & 0xA)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
|-
|-
| 0x10 || secret || $cX || immY || <code><nowiki>$cX = load_secret(immY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = load_secret_acl(immY);</nowiki></code>
| 0x10 || secret || $cX || immY || <code><nowiki>$cX = load_secret(immY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = load_secret_acl(immY);</nowiki></code>
Line 5,239: Line 5,422:
| 0x11 || keyreg || $cX || N/A || <code><nowiki>active_key = $cX;</nowiki></code> || N/A || N/A
| 0x11 || keyreg || $cX || N/A || <code><nowiki>active_key = $cX;</nowiki></code> || N/A || N/A
|-
|-
| 0x12 || kexp || $cX || $cY || <code><nowiki>$cX = aes_key_expand($cY);</nowiki></code> || <code><nowiki>(!is_mode_hs && (ACL($cX) & 0x10))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
| 0x12 || kexp || $cX || $cY || <code><nowiki>$cX = aes_key_expand($cY);</nowiki></code> || <code><nowiki>(is_mode_hs || (!is_mode_hs && (ACL($cX) & 0x10)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
|-
|-
| 0x13 || krexp || $cX || $cY || <code><nowiki>$cX = aes_key_reverse_expand($cY);</nowiki></code> || <code><nowiki>(!is_mode_hs && (ACL($cX) & 0x10))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
| 0x13 || krexp || $cX || $cY || <code><nowiki>$cX = aes_key_reverse_expand($cY);</nowiki></code> || <code><nowiki>(is_mode_hs || (!is_mode_hs && (ACL($cX) & 0x10)))</nowiki></code> || <code><nowiki>ACL($cX) = ACL($cY);</nowiki></code>
|-
|-
| 0x14 || enc || $cX || $cY || <code><nowiki>$cX = aes_enc(active_key, $cY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = (ACL(active_key) & ACL($cY));</nowiki></code>
| 0x14 || enc || $cX || $cY || <code><nowiki>$cX = aes_enc(active_key, $cY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = (ACL(active_key) & ACL($cY));</nowiki></code>
Line 5,247: Line 5,430:
| 0x15 || dec || $cX || $cY || <code><nowiki>$cX = aes_dec(active_key, $cY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = (ACL(active_key) & ACL($cY));</nowiki></code>
| 0x15 || dec || $cX || $cY || <code><nowiki>$cX = aes_dec(active_key, $cY);</nowiki></code> || N/A || <code><nowiki>ACL($cX) = (ACL(active_key) & ACL($cY));</nowiki></code>
|-
|-
| 0x16 || [[#sigcmp|sigcmp]] || $cX || $cY || <code><nowiki>current_sig = memcmp($cX, $cY) ? NULL : $cX;</nowiki></code> || <code><nowiki>is_secure_bootrom</nowiki></code> || <code><nowiki>has_sig = true; is_mode_hs = true;</nowiki></code>
| 0x16 || [[#sigcmp|sigcmp]] || $cX || $cY || <code><nowiki>current_sig = memcmp($cX, $cY) ? NULL : $cX;</nowiki></code> || <code><nowiki>(is_mode_secure_bootrom && (ACL($cY) & 0x2))</nowiki></code> || <code><nowiki>is_mode_hs = has_sig = (current_sig != NULL);</nowiki></code>
|-
|-
| 0x17 || sigenc || $cX || $cY || <code><nowiki>$cX = aes_enc($cY, current_sig);</nowiki></code> || <code><nowiki>has_sig</nowiki></code> || <code><nowiki>ACL($cX) = 0x3;</nowiki></code>
| 0x17 || sigenc || $cX || $cY || <code><nowiki>$cX = aes_enc($cY, current_sig);</nowiki></code> || <code><nowiki>(is_mode_hs && has_sig)</nowiki></code> || <code><nowiki>ACL($cX) = 0x3;</nowiki></code>
|-
|-
| 0x18 || [[#sigclr|sigclr]] || N/A || N/A || <code><nowiki>current_sig = NULL;</nowiki></code> || <code><nowiki>has_sig</nowiki></code> || <code><nowiki>has_sig = false;</nowiki></code>
| 0x18 || [[#sigclr|sigclr]] || N/A || N/A || <code><nowiki>current_sig = NULL;</nowiki></code> || <code><nowiki>(is_mode_hs && has_sig)</nowiki></code> || <code><nowiki>has_sig = false;</nowiki></code>
|}
|}


Retrieved from "https://switchbrew.org/wiki/TSEC"