Fuses: Difference between revisions

Deejay87 (talk | contribs)
No edit summary
Fix multiple old inaccuracies
Line 358: Line 358:
|-
|-
| 9
| 9
| FUSE_PRIV2RESHIFT_TRIG_1_SCPU_VAL
|-
| 10
| FUSE_PRIV2RESHIFT_TRIG_1_SL2_TBANK_VAL
|-
| 11
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU0_VAL
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU0_VAL
|-
|-
| 10
| 12
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU1_VAL
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU1_VAL
|-
|-
| 11
| 13
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU2_VAL
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU2_VAL
|-
|-
| 12
| 14
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU3_VAL
| FUSE_PRIV2RESHIFT_STATUS_1_FCPU3_VAL
|-
|-
| 13
| 15
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK0_VAL
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK0_VAL
|-
|-
| 14
| 16
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK1_VAL
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK1_VAL
|-
|-
| 15
| 17
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK2_VAL
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK2_VAL
|-
|-
| 16
| 18
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK3_VAL
| FUSE_PRIV2RESHIFT_STATUS_1_FL2_TBANK3_VAL
|-
| 19
| FUSE_PRIV2RESHIFT_STATUS_1_SCPU_VAL
|-
| 20
| FUSE_PRIV2RESHIFT_STATUS_1_SL2_TBANK_VAL
|}
|}


Line 620: Line 632:
| 0x7000F9F0
| 0x7000F9F0
|-
|-
| FUSE_SKU_DIRECT_CONFIG
| [[#FUSE_SKU_DIRECT_CONFIG|FUSE_SKU_DIRECT_CONFIG]]
| 0x7000F9F4
| 0x7000F9F4
|-
|-
Line 1,092: Line 1,104:
==== FUSE_RESERVED_ODM7 ====
==== FUSE_RESERVED_ODM7 ====
Returns the value of the [[#reserved_odm7|reserved_odm7]] anti-downgrade fuse.
Returns the value of the [[#reserved_odm7|reserved_odm7]] anti-downgrade fuse.
==== FUSE_SKU_DIRECT_CONFIG ====
{| class="wikitable" border="1"
!  Bits
!  Description
|-
| 0
| Disable SCPU
|-
| 1
| Disable FCPU0
|-
| 2
| Disable FCPU1
|-
| 3
| Disable FCPU2
|-
| 4
| Disable FCPU3
|-
| 5
| Disable all CPUs
|}
Controls which CPUs can be used.
Erista units have this value set to 0x00 (both Cortex-A53 and Cortex-A57 clusters are usable).
Mariko units have this value set to 0x01 (only the Cortex-A57 cluster is usable).


==== FUSE_OPT_SEC_DEBUG_EN ====
==== FUSE_OPT_SEC_DEBUG_EN ====
Line 2,348: Line 2,390:
| 0-1
| 0-1
|-
|-
| reshift_fcpu0
| [[#irom_patch|irom_patch]]
| 106
| None
| 0-31
|-
| reshift_fcpu1
| 107
| None
| 0-31
|-
| reshift_fcpu2
| 108
| None
| 0-31
|-
| reshift_fcpu3
| 109
| None
| 0-31
|-
| reshift_fl2_tbank0
| 110
| None
| 0-31
|-
| reshift_fl2_tbank1
| 111
| None
| 0-31
|-
| reshift_fl2_tbank2
| 112
| 112
| None
| None
| 0-31
| 0-2560
|-
| reshift_fl2_tbank3
| 113
| None
| 0-31
|-
| [[#irom_patch|irom_patch]]
| 114
| None
| Variable
|}
|}


Line 3,240: Line 3,242:
| None
| None
| 31
| 31
|-
| reshift_fcpu0
| 168
| None
| 0-31
|-
| reshift_fcpu1
| 169
| None
| 0-31
|-
| reshift_fcpu2
| 170
| None
| 0-31
|-
| reshift_fcpu3
| 171
| None
| 0-31
|-
| reshift_fl2_tbank0
| 172
| None
| 0-31
|-
| reshift_fl2_tbank1
| 173
| None
| 0-31
|-
| reshift_fl2_tbank2
| 174
| None
| 0-31
|-
| reshift_fl2_tbank3
| 175
| None
| 0-31
|-
|-
| [[#irom_patch_2|irom_patch]]
| [[#irom_patch_2|irom_patch]]
| 176
| 176
| None
| None
| Variable
| 0-2560
|}
|}