Testpads: Difference between revisions
JTAG pins and UART-A ball names |
Notes on JTAG and lockout |
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=== Cluster C === | === Cluster C === | ||
The JTAG pins are multiplexed between NV_JTAG and ARM_JTAG by the TRST pin: | |||
* NV_JTAG contains a single TAP (ID 0x221173D7) for boundary scan board verification. | |||
* ARM_JTAG contains two debugging TAPs for CoreSight (ID 0x5BA00477) and BPMP (ID 0x4F1F0F0F). | |||
Note: NV_JTAG and ARM_JTAG are locked out by [[Fuses#Cache|FUSE_ARM_JTAG_DIS]] on production devices. | |||
{| class=wikitable | {| class=wikitable | ||
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| 4 || JTAG_TCK || || 0-1.8V || || || | | 4 || JTAG_TCK || || 0-1.8V || || || | ||
|- | |- | ||
| 5 || JTAG_RTCK || || 0-1.8V || || || | | 5 || JTAG_RTCK || || 0-1.8V || || || Unused for NV_JTAG | ||
|- | |- | ||
| 6 || UART1_RTS || || 0-1.8V || || || UART-A RTS Flow control | | 6 || UART1_RTS || || 0-1.8V || || || UART-A RTS Flow control | ||
| Line 81: | Line 87: | ||
| 9 || JTAG_TMS || || 0-1.8V || || || | | 9 || JTAG_TMS || || 0-1.8V || || || | ||
|- | |- | ||
| 10 || JTAG_TRST_N || || 0-1.8V || || || | | 10 || JTAG_TRST_N || || 0-1.8V || || || Not a TAP reset; Multiplexes between NV_JTAG (HI) and ARM_JTAG (LO) | ||
|- | |- | ||
| 11 || +1.8V || || 0-1.8V || || || | | 11 || +1.8V || || 0-1.8V || || || | ||