NV services - Revision history

Hexkyz at 01:40, 18 October 2025

2025-10-17T23:40:01Z

← Older revision		Revision as of 03:40, 18 October 2025
Line 2,426:		Line 2,426:
	\| 0xC008481F \|\| Inout \|\| 8 \|\| [S2] [[#NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE\|NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE]]		\| 0xC008481F \|\| Inout \|\| 8 \|\| [S2] [[#NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE\|NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE]]
	\|-		\|-
	\| 0x40044820 \|\| In \|\| 4 \|\| [S2]		\| 0x40044820 \|\| In \|\| 4 \|\| [S2] [[#NVGPU_IOCTL_CHANNEL_OPEN\|NVGPU_IOCTL_CHANNEL_OPEN]]
	\|-		\|-
	\| 0xC0504821 \|\| Inout \|\| 80 \|\| [S2] [[#NVGPU_IOCTL_CHANNEL_SETUP_BIND\|NVGPU_IOCTL_CHANNEL_SETUP_BIND]]		\| 0xC0504821 \|\| Inout \|\| 80 \|\| [S2] [[#NVGPU_IOCTL_CHANNEL_SETUP_BIND\|NVGPU_IOCTL_CHANNEL_SETUP_BIND]]
Line 2,840:		Line 2,840:
	__in u32 graphics_preempt_mode;		__in u32 graphics_preempt_mode;
	__in u32 compute_preempt_mode;		__in u32 compute_preempt_mode;
			};

			=== NVGPU_IOCTL_CHANNEL_OPEN ===
			Opens the channel for a given runlist.

			struct {
			__in s32 runlist_id;
	};		};

2025-10-17T23:30:42Z

@@ Line 1,767: / Line 1,767: @@
 | 0xC010471E || Inout || 16 || [S2] [[#NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS|NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS]]
 |-
-| 0xC010471F || Inout || 16 || [S2]
+| 0xC010471F || Inout || 16 || [S2] [[#NVGPU_GPU_IOCTL_GET_ENGINE_INFO|NVGPU_GPU_IOCTL_GET_ENGINE_INFO]]
 |}
@@ Line 2,124: / Line 2,124: @@
    struct in_buf2 {
-     __in u32 channels[];
+     __in u32 channels[num_channels];
    };
    struct out_buf {
      __out struct deterministic_opts opts;
    };

2025-10-16T21:05:07Z

← Older revision		Revision as of 01:05, 17 October 2025
Line 1,400:		Line 1,400:
	\| 0xC020410C \|\| Inout \|\| 32 \|\| [S2] [[#NVGPU_AS_IOCTL_MAPPING_MODIFY\|NVGPU_AS_IOCTL_MAPPING_MODIFY]]		\| 0xC020410C \|\| Inout \|\| 32 \|\| [S2] [[#NVGPU_AS_IOCTL_MAPPING_MODIFY\|NVGPU_AS_IOCTL_MAPPING_MODIFY]]
	\|-		\|-
	\| 0xC???410D \|\| Inout \|\| Variable \|\| [S2] [[#~~NVGPU_AS_IOCTL_REMAP~~\|NVGPU_AS_IOCTL_REMAP]]		\| 0xC???410D \|\| Inout \|\| Variable \|\| [S2] [[#NVGPU_AS_IOCTL_REMAP_2\|NVGPU_AS_IOCTL_REMAP]]
	\|-		\|-
	\| 0xC0??4114 \|\| Inout \|\| Variable \|\| [[#~~NVGPU_AS_IOCTL_REMAP_2~~\|NVGPU_AS_IOCTL_REMAP]]		\| 0xC0??4114 \|\| Inout \|\| Variable \|\| [[#NVGPU_AS_IOCTL_REMAP\|NVGPU_AS_IOCTL_REMAP]]
	\|}		\|}

2025-10-16T21:04:15Z

← Older revision		Revision as of 01:04, 17 October 2025
Line 2,392:		Line 2,392:
	\| 0xC004481D \|\| Inout \|\| 4 \|\| [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE\|NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]		\| 0xC004481D \|\| Inout \|\| 4 \|\| [[#NVGPU_IOCTL_CHANNEL_SET_TIMESLICE\|NVGPU_IOCTL_CHANNEL_SET_TIMESLICE]]
	\|-		\|-
	\| 0xC010481E \|\| Inout \|\| 16 \|\| [S2]		\| 0xC010481E \|\| Inout \|\| 16 \|\| [S2] [[#NVGPU_IOCTL_CHANNEL_GET_USER_SYNCPOINT\|NVGPU_IOCTL_CHANNEL_GET_USER_SYNCPOINT]]
	\|-		\|-
	\| 0xC008481F \|\| Inout \|\| 8 \|\| [S2] [[#NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE\|NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE]]		\| 0xC008481F \|\| Inout \|\| 8 \|\| [S2] [[#NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE\|NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE]]
Line 2,793:		Line 2,793:
	struct {		struct {
	__out u64 data;		__out u64 data;
			};

			=== NVGPU_IOCTL_CHANNEL_GET_USER_SYNCPOINT ===
			Returns information on the user syncpoint.

			struct {
			__out u64 gpu_va;
			__out u64 syncpoint_id;
			__out u64 syncpoint_max;
	};		};

2025-10-11T22:54:19Z

2025-09-23T22:09:48Z

/dev/nvhost-dbg-gpu

← Older revision		Revision as of 02:09, 24 September 2025
Line 1,578:		Line 1,578:
	\| 0xC0184421 \|\| Inout \|\| 24 \|\| [S2]		\| 0xC0184421 \|\| Inout \|\| 24 \|\| [S2]
	\|-		\|-
	\| 0x40084422 \|\| In \|\| 8 \|\| [S2]		\| 0x40084422 \|\| In \|\| 8 \|\| [S2] NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE
	\|-		\|-
	\| 0xC0084423 \|\| Inout \|\| 8 \|\| [S2]		\| 0xC0084423 \|\| Inout \|\| 8 \|\| [S2] NVGPU_DBG_GPU_IOCTL_HWPM_CTXSW_MODE
	\|-		\|-
	\| 0x40084424 \|\| In \|\| 8 \|\| [S2]		\| 0x40084424 \|\| In \|\| 8 \|\| [S2] NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK
	\|-		\|-
	\| 0xC0104425 \|\| Inout \|\| 16 \|\| [S2]		\| 0xC0104425 \|\| Inout \|\| 16 \|\| [S2] NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_CONTEXTS
	\|-		\|-
	\| 0xC0184426 \|\| Inout \|\| 24 \|\| [S2]		\| 0xC0184426 \|\| Inout \|\| 24 \|\| [S2] NVGPU_DBG_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE
	\|-		\|-
	\| 0x40084427 \|\| In \|\| 8 \|\| [S2]		\| 0x40084427 \|\| In \|\| 8 \|\| [S2] NVGPU_DBG_GPU_IOCTL_CLEAR_SINGLE_SM_ERROR_STATE
	\|-		\|-
	\| 0x40044428 \|\| In \|\| 4 \|\| [S2]		\| 0x40044428 \|\| In \|\| 4 \|\| [S2] NVGPU_DBG_GPU_IOCTL_SET_SCHED_EXIT_WAIT_FOR_ERRBAR
	\|-		\|-
	\| 0xC0184429 \|\| Inout \|\| 24 \|\| [S2]		\| 0xC0184429 \|\| Inout \|\| 24 \|\| [S2]

2025-09-23T21:49:12Z

(Switch 2) /dev/nvhost-tsg-gpu

← Older revision		Revision as of 01:49, 24 September 2025
Line 2,055:		Line 2,055:
	\| 0xC0045402 \|\| Inout \|\| 4 \|\| NVGPU_TSG_IOCTL_UNBIND_CHANNEL		\| 0xC0045402 \|\| Inout \|\| 4 \|\| NVGPU_TSG_IOCTL_UNBIND_CHANNEL
	\|-		\|-
	\| 0x00005403 \|\| None \|\| 0 \|\| ~~NVGPU_IOCTL_TSG_ENABLE~~		\| 0x00005403 \|\| None \|\| 0 \|\| NVGPU_TSG_IOCTL_ENABLE
	\|-		\|-
	\| 0x00005404 \|\| None \|\| 0 \|\| ~~NVGPU_IOCTL_TSG_DISABLE~~		\| 0x00005404 \|\| None \|\| 0 \|\| NVGPU_TSG_IOCTL_DISABLE
	\|-		\|-
	\| 0x00005405 \|\| None \|\| 0 \|\| ~~NVGPU_IOCTL_TSG_PREEMPT~~		\| 0x00005405 \|\| None \|\| 0 \|\| NVGPU_TSG_IOCTL_PREEMPT
	\|-		\|-
	\| 0xC0085407 \|\| Inout \|\| 8 \|\| ~~NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE~~		\| 0xC0085407 \|\| Inout \|\| 8 \|\| NVGPU_TSG_IOCTL_SET_RUNLIST_INTERLEAVE
	\|-		\|-
	\| 0xC0045408 \|\| Inout \|\| 4 \|\| ~~NVGPU_IOCTL_TSG_SET_TIMESLICE~~		\| 0xC0045408 \|\| Inout \|\| 4 \|\| NVGPU_TSG_IOCTL_SET_TIMESLICE
	\|-		\|-
	\| 0xC0105409 \|\| Inout \|\| 16 \|\|		\| 0xC0105409 \|\| Inout \|\| 16 \|\| NVGPU_TSG_IOCTL_EVENT_ID_CTRL
	\|-		\|-
	\| 0x8004540A \|\| Out \|\| 4 \|\|		\| 0x8004540A \|\| Out \|\| 4 \|\| NVGPU_TSG_IOCTL_GET_TIMESLICE
	\|-		\|-
	\| 0xC018540B \|\| Inout \|\| 24 \|\|		\| 0xC018540B \|\| Inout \|\| 24 \|\| NVGPU_TSG_IOCTL_BIND_CHANNEL_EX
	\|-		\|-
	\| 0xC018540C \|\| Inout \|\| 24 \|\|		\| 0xC018540C \|\| Inout \|\| 24 \|\| NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE
	\|-		\|-
	\| 0xC008540D \|\| Inout \|\| 8 \|\| NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION		\| 0xC008540D \|\| Inout \|\| 8 \|\| NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION

2025-09-23T20:35:24Z

/dev/nvhost-ctrl-gpu

← Older revision		Revision as of 00:35, 24 September 2025
Line 1,673:		Line 1,673:
	\| 0xC108471D \|\| Inout \|\| 264 \|\| [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]		\| 0xC108471D \|\| Inout \|\| 264 \|\| [[#NVGPU_GPU_IOCTL_GET_CPU_TIME_CORRELATION_INFO]]
	\|-		\|-
	\| 0xC010471E \|\| Inout \|\| 16 \|\| [S2]		\| 0xC010471E \|\| Inout \|\| 16 \|\| [S2] NVGPU_GPU_IOCTL_SET_DETERMINISTIC_OPTS
	\|-		\|-
	\| 0xC010471F \|\| Inout \|\| 16 \|\| [S2]		\| 0xC010471F \|\| Inout \|\| 16 \|\| [S2]

2025-09-23T19:43:19Z

Ioctls

← Older revision		Revision as of 23:43, 23 September 2025
Line 2,183:		Line 2,183:
	\| 0xC010481E \|\| Inout \|\| 16 \|\| [S2]		\| 0xC010481E \|\| Inout \|\| 16 \|\| [S2]
	\|-		\|-
	\| 0xC008481F \|\| Inout \|\| 8 \|\| [S2]		\| 0xC008481F \|\| Inout \|\| 8 \|\| [S2] NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE
	\|-		\|-
	\| 0x40044820 \|\| In \|\| 4 \|\| [S2]		\| 0x40044820 \|\| In \|\| 4 \|\| [S2]
	\|-		\|-
	\| 0xC0504821 \|\| Inout \|\| 80 \|\| [S2]		\| 0xC0504821 \|\| Inout \|\| 80 \|\| [S2] NVGPU_IOCTL_CHANNEL_SETUP_BIND
	\|}		\|}

2025-09-10T18:01:38Z

/dev/nvhost-ctrl

← Older revision		Revision as of 22:01, 10 September 2025
Line 339:		Line 339:
	\| 0xC0040022 \|\| Inout \|\| 4 \|\| [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]		\| 0xC0040022 \|\| Inout \|\| 4 \|\| [[#NVHOST_IOCTL_CTRL_SYNCPT_GET_SHIFT]]
	\|-		\|-
	\| 0xC0080027 \|\| Inout \|\| 8 \|\| [S2]		\| 0xC0080027 \|\| Inout \|\| 8 \|\| [S2] NVHOST_IOCTL_CTRL_ALLOC_SYNCPT
	\|-		\|-
	\| 0x40040028 \|\| In \|\| 4 \|\| [S2]		\| 0x40040028 \|\| In \|\| 4 \|\| [S2] NVHOST_IOCTL_CTRL_FREE_SYNCPT
	\|-		\|-
	\| 0xC010002A \|\| Inout \|\| 16 \|\| [S2]		\| 0xC010002A \|\| Inout \|\| 16 \|\| [S2] NVHOST_IOCTL_CTRL_GET_CHARACTERISTICS
	\|-		\|-
	\| 0xC008002B \|\| Inout \|\| 8 \|\| [S2]		\| 0xC008002B \|\| Inout \|\| 8 \|\| [S2] NVHOST_IOCTL_CTRL_CHECK_MODULE_SUPPORT
	\|}		\|}