Kernel Loader - Revision history

Hexkyz: /* KernelLdr_MapInitialIdentityMapping */

2019-12-05T02:01:12Z

KernelLdr_MapInitialIdentityMapping

← Older revision		Revision as of 05:01, 5 December 2019
Line 271:		Line 271:
	// Architecture is 0xD07 (Cortex-A57).		// Architecture is 0xD07 (Cortex-A57).
	cpuactlr_value = 0x1000000; // Non-cacheable load forwarding enabled		cpuactlr_value = 0x1000000; // Non-cacheable load forwarding enabled
	cpuectlr_value = 0x1B00000040; // ~~TODO: What is this?~~		cpuectlr_value = 0x1B00000040; // Enable the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster; set the L2 load/store data prefetch distance to 8 requests; set the L2 instruction fetch prefetch distance to 3 requests.
	if (hw_variant == 0 \|\| (hw_variant == 1 && hw_revision <= 1)) {		if (hw_variant == 0 \|\| (hw_variant == 1 && hw_revision <= 1)) {
	// If supported, disable load-pass DMB.		// If supported, disable load-pass DMB.
Line 282:		Line 282:
	} else if (architecture == 0xD03) { // 9.0.0+		} else if (architecture == 0xD03) { // 9.0.0+
	// Architecture is 0xD03 (Cortex-A53).		// Architecture is 0xD03 (Cortex-A53).
	cpuactlr_value = 0x90CA000; // ~~TODO: What is this?~~		cpuactlr_value = 0x90CA000; // Set L1 data prefetch control to allow 5 outstanding prefetches; enable device split throttle; set the number of independent data prefetch streams to 2; disable transient and no-read-allocate hints for loads; set write streaming no-allocate threshold so the 128th consecutive streaming cache line does not allocate in the L1 or L2 cache.
	cpuectlr_value = 0x40; // ~~TODO: What is this?~~		cpuectlr_value = 0x40; // Enable hardware management of data coherency with other cores in the cluster.
	if (hw_variant != 0 \|\| (hw_variant == 0 && hw_revision > 2)) {		if (hw_variant != 0 \|\| (hw_variant == 0 && hw_revision > 2)) {
	// ~~TODO: What is this?~~		// If supported, enable data cache clean as data cache clean/invalidate.
	cpuactlr_value \|= 0x100000000000;		cpuactlr_value \|= 0x100000000000;
	}		}

SciresM: /* KernelLdr_LoadKernel */ .rel.ro

2019-09-10T05:56:19Z

KernelLdr_LoadKernel: .rel.ro

← Older revision		Revision as of 09:56, 10 September 2019
Line 183:		Line 183:
	// Maps .rodata as R--		// Maps .rodata as R--
	attribute = 0x60000000000788;		attribute = 0x60000000000788;

			// 9.0.0+
			{
			// On 9.0.0+, .rodata is initially RW- to facilitate .rel.ro.
			attribute = 0x60000000000708;
			}

	ttbr1_page_table.Map(final_virtual_kernel_base + ro_offset, ro_end_offset - ro_offset, kernel_base + ro_offset, &attribute, &g_InitialPageAllocator);		ttbr1_page_table.Map(final_virtual_kernel_base + ro_offset, ro_end_offset - ro_offset, kernel_base + ro_offset, &attribute, &g_InitialPageAllocator);

Line 197:		Line 204:
	// Applies all R_AARCH64_RELATIVE relocations.		// Applies all R_AARCH64_RELATIVE relocations.
	KernelLdr_ApplyRelocations(final_kernel_virtual_base, final_kernel_virtual_base + dynamic_offset);		KernelLdr_ApplyRelocations(final_kernel_virtual_base, final_kernel_virtual_base + dynamic_offset);

			// 9.0.0+: Reprotects .rodata as R--.
			ttbr1_page_table.ReprotectToReadOnly(final_virtual_kernel_base + ro_offset, ro_end_offset - ro_offset);

	// This is standard libc init_array code, but called for the kernel's binary instead of kernelldr's.		// This is standard libc init_array code, but called for the kernel's binary instead of kernelldr's.

SciresM: /* KInitialPageTable::IsFree */

2019-09-10T05:54:02Z

KInitialPageTable::IsFree

← Older revision		Revision as of 09:54, 10 September 2019
Line 500:		Line 500:

	This is just standard aarch64 page table code. Walks the page table, verifying that all entries it would map for size + range are free.		This is just standard aarch64 page table code. Walks the page table, verifying that all entries it would map for size + range are free.

			== KInitialPageTable::ReprotectToReadOnly ==

			This is just standard aarch64 page table code. Walks the page table, reprotects the read-write pages in the specified region as read-only.

			This is probably a compiler-optimized version of a function that does an arbitrary reprotection.

	== KInitialPageTable::GetL1Table ==		== KInitialPageTable::GetL1Table ==

SciresM: /* KernelLdr_ExceptionTable */

2019-09-10T05:53:09Z

KernelLdr_ExceptionTable

@@ Line 414: / Line 414: @@
 * Restores X19-X30 + SP from the memory pointed to by TPIDR_EL1.
 * Returns to the saved LR stored in the context save struct.
 == KInitialPageAllocator::KInitialPageAllocator ==

SciresM: /* KernelLdr_MapInitialIdentityMapping */

2019-09-10T05:51:08Z

KernelLdr_MapInitialIdentityMapping

← Older revision		Revision as of 09:51, 10 September 2019
Line 251:		Line 251:

	// 9.0.0+: Save X19-X30 + SP, save context struct in TPIDR_EL1.		// 9.0.0+: Save X19-X30 + SP, save context struct in TPIDR_EL1.
	~~KernelLdr_SaveRegistersToTpidr~~();		KernelLdr_SaveRegistersToTpidrEl1();

	if (implementer == 0x41) {		if (implementer == 0x41) {

SciresM: /* KernelLdr_MapInitialIdentityMapping */

2019-09-10T05:50:53Z

KernelLdr_MapInitialIdentityMapping

@@ Line 248: / Line 248: @@
      // Check what CPU we're running on to configure CPUECTLR, CPUACTLR appropriately.
      manufacture_id = MIDR_EL1;
-     implemeter = manufacturer_id >> 24) & 0xFF;
+     implementer = manufacturer_id >> 24) & 0xFF;
      if (implementer == 0x41) {
          // Implementer ID is 0x41 (ARM Limited).
@@ Line 261: / Line 265: @@
                  // If supported, disable load-pass DMB.
                  cpuactlr_value |= 0x800000000000000;
+             }
              CPUACTLR_EL1 = cpuactlr_value;
@@ Line 268: / Line 284: @@
+         }
+     }
 </pre>

SciresM: /* KernelLdr_InvalidateCacheShared */

2019-09-10T05:46:31Z

KernelLdr_InvalidateCacheShared

← Older revision		Revision as of 09:46, 10 September 2019
Line 384:		Line 384:

	Standard ARM cache clean code, uses LoUIS from CLIDR_EL1.		Standard ARM cache clean code, uses LoUIS from CLIDR_EL1.

			== KernelLdr_ExceptionTable ==

			Standard aarch64 exception table, only function that doesn't infinite loop is synchronous exception from same EL (synch_spx_exception)

			synch_spx_exception does the following:
			* Moves TPIDR_EL1 into X0
			* Infinite loops if it is 0/NULL.
			* Restores X19-X30 + SP from the memory pointed to by TPIDR_EL1.
			* Returns to the saved LR stored in the context save struct.

	== KInitialPageAllocator::KInitialPageAllocator ==		== KInitialPageAllocator::KInitialPageAllocator ==

SciresM: /* KernelLdr_Main */

2019-09-10T05:44:08Z

KernelLdr_Main

← Older revision		Revision as of 09:44, 10 September 2019
Line 21:		Line 21:
	KernelLdr_ApplyRelocations(&KernelLdr_Main, __dynamic_start);		KernelLdr_ApplyRelocations(&KernelLdr_Main, __dynamic_start);
	KernelLdr_libc_init_array();		KernelLdr_libc_init_array();
			</pre>

			[9.0.0+]
			Then it clears TPIDR_EL1 to 0, and sets VBAR_EL1.
			<pre>
			// 9.0.0+
			TPIDR_EL1 = 0
			VBAR_EL1 = KernelLdr_ExceptionTable
	</pre>		</pre>

SciresM: /* KernelLdr_MapInitialIdentityMapping */

2019-08-31T05:34:00Z

KernelLdr_MapInitialIdentityMapping

← Older revision		Revision as of 09:34, 31 August 2019
Line 232:		Line 232:
	// Set TTBR0/TTBR1 with initial page tables.		// Set TTBR0/TTBR1 with initial page tables.
	TTBR0_EL1 = ttbr0_page_table.GetL1Table();		TTBR0_EL1 = ttbr0_page_table.GetL1Table();
	TTBR1_EL1 = ttbr1_page_table.GetL1Table();		TTBR1_EL1 = ttbr1_page_table->GetL1Table();

	// Configure MAIR, TCR. TODO: Document here what bits these are.		// Configure MAIR, TCR. TODO: Document here what bits these are.

SciresM: /* KInitialPageTable::IsFree */

2019-08-31T05:33:26Z

KInitialPageTable::IsFree

← Older revision		Revision as of 09:33, 31 August 2019
Line 446:		Line 446:

	This is just standard aarch64 page table code. Walks the page table, verifying that all entries it would map for size + range are free.		This is just standard aarch64 page table code. Walks the page table, verifying that all entries it would map for size + range are free.

			== KInitialPageTable::GetL1Table ==

			This is an inferred getter for a (presumably) private member.

			<pre>

			void *KInitialPageTable::GetL1Table() const {
			return this->l1_table_ptr;
			}

			</pre>

	= Structures =		= Structures =